Rev 0 – ?author? – ?age? (?date?)
?log?
Subversion Repositories
–
MLAB
MLAB
library
svnkaklik
MLAB_E
8magsvn
Català-Valencià – Catalan
中文 – Chinese (Simplified)
中文 – Chinese (Traditional)
Česky – Czech
Dansk – Danish
Nederlands – Dutch
English – English
Suomi – Finnish
Français – French
Deutsch – German
עברית – Hebrew
हिंदी – Hindi
Magyar – Hungarian
Bahasa Indonesia – Indonesian
Italiano – Italian
日本語 – Japanese
한국어 – Korean
Македонски – Macedonian
मराठी – Marathi
Norsk – Norwegian
Polski – Polish
Português – Portuguese
Português – Portuguese (Brazil)
Русский – Russian
Slovenčina – Slovak
Slovenščina – Slovenian
Español – Spanish
Svenska – Swedish
Türkçe – Turkish
Українська – Ukrainian
Oëzbekcha – Uzbek
(root)
/
Designs
/
HAM Constructions
/
SDRX02B
/
HDL
/
README.txt
@ 4817
Rev 0
Hide changed files
Details
Blame
Compare with Previous
From rev:
To rev:
Max revs:
Search history for:
Rev
Age
Author
Path
Log message
Diff
Changes
3643
3752 d 5 h
kaklik
/
zarozena nova dokumentacni slozka pro modul urceny symetrizaci signalu.
Diff
/Modules/CommRF/SMA2SATA01A
/Modules/CommRF/SMA2SATA01A/CAM_AMA
/Modules/CommRF/SMA2SATA01A/CAM_DOC
/Modules/CommRF/SMA2SATA01A/CAM_PROFI
/Modules/CommRF/SMA2SATA01A/CAM_PROFI/Preview.gvp
/Modules/CommRF/SMA2SATA01A/DOC
/Modules/CommRF/SMA2SATA01A/DOC/HTML
/Modules/CommRF/SMA2SATA01A/DOC/SRC
/Modules/CommRF/SMA2SATA01A/PrjInfo.txt
/Modules/CommRF/SMA2SATA01A/SCH_PCB
/Modules/CommRF/SMA2SATA01A/SCH_PCB/SMA2SATA.pro
/Modules/CommRF/SMA2SATA01A/SW
/Modules/CommRF/SMA2SATA01A/pdf
/Designs/HAM Constructions/SDRX02B/HDL/README.txt
/Modules/Measuring/GPS01A/TODO.txt
3641
3756 d 1 h
kaklik
/Designs/HAM Constructions/SDRX02B/HDL/
Pridani HDL zdrojovych kodu.
Diff
/Designs/HAM Constructions/SDRX02B/HDL
/Designs/HAM Constructions/SDRX02B/HDL/README.txt
/Designs/HAM Constructions/SDRX02B/HDL/modules
/Designs/HAM Constructions/SDRX02B/HDL/modules/comm
/Designs/HAM Constructions/SDRX02B/HDL/modules/comm/spi_master_transmit.vhd
/Designs/HAM Constructions/SDRX02B/HDL/modules/core_generator_ml605
/Designs/HAM Constructions/SDRX02B/HDL/modules/core_generator_ml605/clk_125MHz_to_6MHz.xco
/Designs/HAM Constructions/SDRX02B/HDL/modules/core_generator_ml605/fifo_32x512.xco
/Designs/HAM Constructions/SDRX02B/HDL/modules/core_generator_ml605/fifo_32x512_dualclk_fwft.xco
/Designs/HAM Constructions/SDRX02B/HDL/modules/core_generator_ml605/fifo_32x512_walmostfull.xco
/Designs/HAM Constructions/SDRX02B/HDL/modules/fifo_related
/Designs/HAM Constructions/SDRX02B/HDL/modules/fifo_related/fifo_to_enable.vhd
/Designs/HAM Constructions/SDRX02B/HDL/modules/information
/Designs/HAM Constructions/SDRX02B/HDL/modules/information/information_block.vhd
/Designs/HAM Constructions/SDRX02B/HDL/modules/sychro1
/Designs/HAM Constructions/SDRX02B/HDL/modules/sychro1/clock_divider.vhd
/Designs/HAM Constructions/SDRX02B/HDL/modules/sychro1/up_counter.vhd
/Designs/HAM Constructions/SDRX02B/HDL/modules/sychro1/up_counter_stdlv.vhd
/Designs/HAM Constructions/SDRX02B/HDL/modules/xilly
/Designs/HAM Constructions/SDRX02B/HDL/modules/xilly/xilly_userlogiccmp_wrapper.vhd
/Designs/HAM Constructions/SDRX02B/HDL/project_src
/Designs/HAM Constructions/SDRX02B/HDL/project_src/bitslip_compensation.vhd
/Designs/HAM Constructions/SDRX02B/HDL/project_src/glue_data.vhd
/Designs/HAM Constructions/SDRX02B/HDL/project_src/information_data.vhd
/Designs/HAM Constructions/SDRX02B/HDL/project_src/iserdes_clock_generator.vhd
/Designs/HAM Constructions/SDRX02B/HDL/project_src/kakona_package.vhd
/Designs/HAM Constructions/SDRX02B/HDL/project_src/lo_divider_wrapper.vhd
/Designs/HAM Constructions/SDRX02B/HDL/project_src/multiplexer_from_fifos.vhd
/Designs/HAM Constructions/SDRX02B/HDL/project_src/myserdes_ddr.vhd
/Designs/HAM Constructions/SDRX02B/HDL/project_src/myserdes_ddr_wrapper.vhd
/Designs/HAM Constructions/SDRX02B/HDL/project_src/processing_block.vhd
/Designs/HAM Constructions/SDRX02B/HDL/project_src/saw_generator_wrapper.vhd
/Designs/HAM Constructions/SDRX02B/HDL/project_src/spi_transmitter_wrapper2.vhd
/Designs/HAM Constructions/SDRX02B/HDL/project_src/swap_endianness.vhd
/Designs/HAM Constructions/SDRX02B/HDL/project_src/userlogiccmp_template.vhd
/Designs/HAM Constructions/SDRX02B/HDL/project_src/xilly
/Designs/HAM Constructions/SDRX02B/HDL/project_src/xilly/xilly_toplevel.userlogiccmp_kakona.vhd
/Designs/HAM Constructions/SDRX02B/HDL/project_src/xillybus_ml605_kakona.ucf