Rev Age Author Path Log message Diff Changes
4608 3143 d 5 h kaklik / uprava modelu. Diff
/Designs/Laser_pulser/HDL/PulseGen/PulseGen.xise
/Modules/ARM/ODROID-C2/CAD/ODROID-C2_MLAB_breakout_frame.stl
/Modules/ARM/ODROID-C2/CAD/src/ODROID-C2_MLAB_breakout_frame.scad
/Modules/CPLD_FPGA/XILINX_XVC/XVC_SOFTWARE/XVC_1x/buildLinux.sh
3690 3822 d 3 h kaklik / presunuti zdrojaku ke generatoru pulzu. Diff
/Designs/Laser_pulser/HDL
/Modules/CPLD_FPGA/S3AN01B/HDL
3243 4169 d 18 h kaklik /Modules/CPLD_FPGA/ uprava jmenne konvence projektovych slozek. Diff
/Modules/CPLD_FPGA/S3AN01B/HDL
/Modules/CPLD_FPGA/XILINX_CHIPSCOPE/HDL
/Modules/CPLD_FPGA/S3AN01B/VHDL
/Modules/CPLD_FPGA/XILINX_CHIPSCOPE/VHDL
2534 4497 d 0 h kakl /Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen/src/ Pridano generovani baliku pulzu a prepinatelna opakovaci frekvence na DOPSW. Vynulovani na TL. Diff
/Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen/src/PulseGen.vhd
2533 4497 d 1 h kakl /Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen/ Pridano automaticke verzovani. Diff
/Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen/PulseGen.xise
/Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen/pulsegen.bit
/Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen/src/PulseGen.vhd
2528 4501 d 15 h kakl /Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen/ Pulzni generator.
Prvni funkcni verze.
Prekryvajici se impulzy 10ns az 2us.
Opakovaci frekvence cca 1,6kHz.		 Diff
/Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen
/Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen/PulseGen.ipf
/Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen/PulseGen.xise
/Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen/pulsegen.bit
/Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen/src
/Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen/src/LIB
/Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen/src/LIB/PS2.vhd
/Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen/src/PulseGen.vhd
/Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen/src/S3AN01B.ucf