Rev 4608 – kaklik – 3101 d 23 h (2016-05-18 09:19:14)
uprava modelu.
Subversion Repositories
–
MLAB
MLAB
library
svnkaklik
MLAB_E
8magsvn
Català-Valencià – Catalan
中文 – Chinese (Simplified)
中文 – Chinese (Traditional)
Česky – Czech
Dansk – Danish
Nederlands – Dutch
English – English
Suomi – Finnish
Français – French
Deutsch – German
עברית – Hebrew
हिंदी – Hindi
Magyar – Hungarian
Bahasa Indonesia – Indonesian
Italiano – Italian
日本語 – Japanese
한국어 – Korean
Македонски – Macedonian
मराठी – Marathi
Norsk – Norwegian
Polski – Polish
Português – Portuguese
Português – Portuguese (Brazil)
Русский – Russian
Slovenčina – Slovak
Slovenščina – Slovenian
Español – Spanish
Svenska – Swedish
Türkçe – Turkish
Українська – Ukrainian
Oëzbekcha – Uzbek
(root)
/
Designs
/
Laser_pulser
/
HDL
/
PulseGen
/
PulseGen.xise
Rev 4608
Hide changed files
Details
Blame
Compare with Previous
From rev:
To rev:
Max revs:
Search history for:
Rev
Age
Author
Path
Log message
Diff
Changes
4608
3101 d 23 h
kaklik
/
uprava modelu.
Diff
/Designs/Laser_pulser/HDL/PulseGen/PulseGen.xise
/Modules/ARM/ODROID-C2/CAD/ODROID-C2_MLAB_breakout_frame.stl
/Modules/ARM/ODROID-C2/CAD/src/ODROID-C2_MLAB_breakout_frame.scad
/Modules/CPLD_FPGA/XILINX_XVC/XVC_SOFTWARE/XVC_1x/buildLinux.sh
3690
3780 d 22 h
kaklik
/
presunuti zdrojaku ke generatoru pulzu.
Diff
/Designs/Laser_pulser/HDL
/Modules/CPLD_FPGA/S3AN01B/HDL
3243
4128 d 12 h
kaklik
/Modules/CPLD_FPGA/
uprava jmenne konvence projektovych slozek.
Diff
/Modules/CPLD_FPGA/S3AN01B/HDL
/Modules/CPLD_FPGA/XILINX_CHIPSCOPE/HDL
/Modules/CPLD_FPGA/S3AN01B/VHDL
/Modules/CPLD_FPGA/XILINX_CHIPSCOPE/VHDL
2533
4455 d 19 h
kakl
/Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen/
Pridano automaticke verzovani.
Diff
/Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen/PulseGen.xise
/Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen/pulsegen.bit
/Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen/src/PulseGen.vhd
2528
4460 d 10 h
kakl
/Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen/
Pulzni generator.
Prvni funkcni verze.
Prekryvajici se impulzy 10ns az 2us.
Opakovaci frekvence cca 1,6kHz.
Diff
/Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen
/Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen/PulseGen.ipf
/Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen/PulseGen.xise
/Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen/pulsegen.bit
/Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen/src
/Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen/src/LIB
/Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen/src/LIB/PS2.vhd
/Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen/src/PulseGen.vhd
/Modules/CPLD_FPGA/S3AN01B/VHDL/PulseGen/src/S3AN01B.ucf