Rev Age Author Path Log message Diff
3230 4001 d 9 h kakl /Designs/Measuring_instruments/ Prejmenovani slozek VHDL na HDL. Diff
3223 4001 d 19 h kakl /Designs/Measuring_instruments/RMDS01A/VHDL/gtime/ 23 tiku hodin na 32 bitu
pred tim bylo treba 33		 Diff
3220 4002 d 8 h kakl /Designs/Measuring_instruments/RMDS01A/VHDL/gtime/ Pridan vysledek prekladu. Diff
3219 4002 d 9 h kakl /Designs/Measuring_instruments/RMDS01A/VHDL/gtime/ Funkcni vycitani frekvence pres posuvny registr. Diff
3177 4009 d 18 h kakl /Designs/Measuring_instruments/RMDS01A/VHDL/gtime/ Atomovej BCD citac. Diff
3176 4010 d 3 h kakl /Designs/Measuring_instruments/RMDS01A/VHDL/gtime/ Meziverze. Diff
3173 4011 d 20 h kakl /Designs/Measuring_instruments/RMDS01A/VHDL/gtime/src/ Atomovej citac. Diff
3172 4011 d 22 h kakl /Designs/Measuring_instruments/RMDS01A/VHDL/gtime/src/ Pridan asynchronni reset citace. Diff
3166 4012 d 19 h kakl /Designs/Measuring_instruments/RMDS01A/VHDL/gtime/ Pokus o citac. Diff
3165 4012 d 21 h kakl /Designs/Measuring_instruments/RMDS01A/VHDL/ Prejmenovani projektu z PulseGenDiff Diff