Rev Age Author Path Log message Diff
3230 4021 d 8 h kakl /Designs/Measuring_instruments/ Prejmenovani slozek VHDL na HDL. Diff
3223 4021 d 18 h kakl /Designs/Measuring_instruments/RMDS01A/VHDL/gtime/ 23 tiku hodin na 32 bitu
pred tim bylo treba 33		 Diff
3220 4022 d 8 h kakl /Designs/Measuring_instruments/RMDS01A/VHDL/gtime/ Pridan vysledek prekladu. Diff
3219 4022 d 8 h kakl /Designs/Measuring_instruments/RMDS01A/VHDL/gtime/ Funkcni vycitani frekvence pres posuvny registr. Diff
3177 4029 d 17 h kakl /Designs/Measuring_instruments/RMDS01A/VHDL/gtime/ Atomovej BCD citac. Diff
3176 4030 d 2 h kakl /Designs/Measuring_instruments/RMDS01A/VHDL/gtime/ Meziverze. Diff
3173 4031 d 20 h kakl /Designs/Measuring_instruments/RMDS01A/VHDL/gtime/src/ Atomovej citac. Diff
3172 4031 d 22 h kakl /Designs/Measuring_instruments/RMDS01A/VHDL/gtime/src/ Pridan asynchronni reset citace. Diff
3166 4032 d 18 h kakl /Designs/Measuring_instruments/RMDS01A/VHDL/gtime/ Pokus o citac. Diff
3165 4032 d 20 h kakl /Designs/Measuring_instruments/RMDS01A/VHDL/ Prejmenovani projektu z PulseGenDiff Diff