Rev Age Author Path Log message Diff
3230 4006 d 3 h kakl /Designs/Measuring_instruments/ Prejmenovani slozek VHDL na HDL. Diff
3223 4006 d 14 h kakl /Designs/Measuring_instruments/RMDS01A/VHDL/gtime/ 23 tiku hodin na 32 bitu
pred tim bylo treba 33		 Diff
3220 4007 d 3 h kakl /Designs/Measuring_instruments/RMDS01A/VHDL/gtime/ Pridan vysledek prekladu. Diff
3219 4007 d 3 h kakl /Designs/Measuring_instruments/RMDS01A/VHDL/gtime/ Funkcni vycitani frekvence pres posuvny registr. Diff
3177 4014 d 13 h kakl /Designs/Measuring_instruments/RMDS01A/VHDL/gtime/ Atomovej BCD citac. Diff
3176 4014 d 22 h kakl /Designs/Measuring_instruments/RMDS01A/VHDL/gtime/ Meziverze. Diff
3173 4016 d 15 h kakl /Designs/Measuring_instruments/RMDS01A/VHDL/gtime/src/ Atomovej citac. Diff
3172 4016 d 17 h kakl /Designs/Measuring_instruments/RMDS01A/VHDL/gtime/src/ Pridan asynchronni reset citace. Diff
3166 4017 d 13 h kakl /Designs/Measuring_instruments/RMDS01A/VHDL/gtime/ Pokus o citac. Diff
3165 4017 d 16 h kakl /Designs/Measuring_instruments/RMDS01A/VHDL/ Prejmenovani projektu z PulseGenDiff Diff