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Rev Age Author Path Log message Diff
1753 4918 d 14 h kakl /Modules/TDC/GP201A/SW/PICinterface/ zakonzervovani kodu pred vytvorenim funkci pro nastaveni TDC. Diff
1751 4920 d 13 h kaklik / zaznam nalezenych chyb Diff
1745 4923 d 15 h kakl /Modules/TDC/GP201A/SW/PICinterface/ prvni verze funkcni komunikace s TDC. Zbyva doresit nastavovani registru. Diff
1744 4924 d 7 h kakl /Modules/TDC/GP201A/ opravena chyba v popisu napajeni. zacatek psani firmwaru Diff
1743 4925 d 7 h kakl /Modules/CommSerial/ETH01A/ Vytvořena první část schéma pro Ethernet modul. Chybí PoE část a dokreslení ETH konektoru. Diff
1742 4925 d 18 h kaklik /Modules/ADconverters/ADCmonoPPI01A/ nalezene chyby Diff
1741 4925 d 20 h kakl /Modules/PIC/PIC18F8xTQ8001A/ vylepseni osazovaku Diff
1740 4926 d 16 h kakl /Modules/ opravy PCB Diff
1739 4927 d 8 h kakl /Modules/ARM/STM32F10xRxT/ Uprava PCB Diff
1738 4928 d 8 h kaklik /Modules/ARM/STM32F10xRxT/PCB/ zbyva vyhazet nove zmrsene cesty. Diff
1737 4928 d 9 h kaklik /Modules/ARM/STM32F10xRxT/ Diff
1736 4928 d 10 h kaklik /Modules/ARM/STM32F10xRxT/ meziverze se synchronizaci schematu a PCB. Diff
1727 4930 d 17 h kaklik /Modules/ARM/STM32F10xRxT/ vylepseni dokumentace. Diff
1718 4940 d 14 h kaklik / Opravy a doplneni Diff
1717 4941 d 9 h kaklik /Modules/PIC/PIC18F8xTQ8001A/ oprava potisku Diff
1715 4941 d 15 h kaklik /Modules/Clock/CLKGEN01A/ Diff
1714 4941 d 23 h kaklik /Modules/ARM/STM32F10xRxT/ priprava novych modulu. Diff
1713 4942 d 18 h kaklik / priprava novych modulu. Diff
1712 4943 d 8 h kaklik /Modules/Clock/CLKGEN01B/ Diff
1711 4943 d 8 h kaklik /Modules/Clock/CLKGEN01B/ uprava zemeni a rozlozeni soucastek Diff