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Rev Age Author Path Log message Diff
1934 4816 d 23 h kaklik /Modules/Clock/CLKGEN01B/DOC/ kus anglickeho prekladu Diff
1933 4816 d 23 h kaklik /Modules/Clock/CLKGEN01B/DOC/ kus anglickeho prekladu Diff
1932 4819 d 2 h kaklik /Modules/Clock/CLKGEN01B/DOC/ prejmenovani podle konvence Diff
1931 4821 d 18 h kaklik /Modules/TDC/GP201A/SW/PICinterface/ testovani TDC Diff
1930 4821 d 22 h kaklik / preklad kodu Diff
1914 4832 d 2 h kaklik /Modules/CommSerial/ETH02A/ Vygenerovani potisku Diff
1913 4832 d 2 h kaklik /Modules/CommSerial/ETH02A/ prace na modulu pro ethernet Diff
1912 4832 d 3 h kaklik /Modules/CommSerial/ETH02A/ prace na modulu pro ethernet Diff
1911 4832 d 20 h kaklik /Modules/ Vyvoj tistaku pro ETHERNET. Diff
1910 4833 d 21 h kaklik /Modules/ARM/STM32F10xRxT/ nalezene chyby Diff
1908 4835 d 16 h klimma /Modules/PowerSupply/klimma/ Diff
1907 4835 d 21 h kaklik /Modules/PowerSupply/MC3406301A/pdf/ dokumentace Diff
1906 4837 d 8 h miho /Modules/CPLD_FPGA/S3AN01A/ S3AN01A doplnění obrázků Diff
1899 4838 d 0 h miho /Modules/CPLD_FPGA/S3AN01A/ S3AN01A je již zastaralá konstrukce Diff
1898 4838 d 0 h miho /Modules/CPLD_FPGA/S3AN01B/ S3AN01B revize desky S3AN01A (s opravami) Diff
1897 4838 d 0 h miho /Modules/CPLD_FPGA/S3AN01A/SCH/ S3AN01A doplněny texty Diff
1896 4841 d 22 h miho /Modules/CPLD_FPGA/S3AN01A/ S3AN01A opravy schématu (doplnění Errata) a přenesení změn do PCB. Diff
1894 4842 d 17 h kaklik /Modules/CommSerial/ETH02A/ Diff
1892 4851 d 17 h kaklik /Modules/CommSerial/ETH02A/ zacatek kresleni PCB Diff
1891 4851 d 18 h kaklik /Modules/ schema modulu s ehternet konektorem. Diff