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Rev Age Author Path Log message Diff
1934 4849 d 4 h kaklik /Modules/Clock/CLKGEN01B/DOC/ kus anglickeho prekladu Diff
1933 4849 d 4 h kaklik /Modules/Clock/CLKGEN01B/DOC/ kus anglickeho prekladu Diff
1932 4851 d 8 h kaklik /Modules/Clock/CLKGEN01B/DOC/ prejmenovani podle konvence Diff
1931 4853 d 23 h kaklik /Modules/TDC/GP201A/SW/PICinterface/ testovani TDC Diff
1930 4854 d 3 h kaklik / preklad kodu Diff
1914 4864 d 7 h kaklik /Modules/CommSerial/ETH02A/ Vygenerovani potisku Diff
1913 4864 d 7 h kaklik /Modules/CommSerial/ETH02A/ prace na modulu pro ethernet Diff
1912 4864 d 8 h kaklik /Modules/CommSerial/ETH02A/ prace na modulu pro ethernet Diff
1911 4865 d 2 h kaklik /Modules/ Vyvoj tistaku pro ETHERNET. Diff
1910 4866 d 2 h kaklik /Modules/ARM/STM32F10xRxT/ nalezene chyby Diff
1908 4867 d 21 h klimma /Modules/PowerSupply/klimma/ Diff
1907 4868 d 2 h kaklik /Modules/PowerSupply/MC3406301A/pdf/ dokumentace Diff
1906 4869 d 13 h miho /Modules/CPLD_FPGA/S3AN01A/ S3AN01A doplnění obrázků Diff
1899 4870 d 5 h miho /Modules/CPLD_FPGA/S3AN01A/ S3AN01A je již zastaralá konstrukce Diff
1898 4870 d 5 h miho /Modules/CPLD_FPGA/S3AN01B/ S3AN01B revize desky S3AN01A (s opravami) Diff
1897 4870 d 5 h miho /Modules/CPLD_FPGA/S3AN01A/SCH/ S3AN01A doplněny texty Diff
1896 4874 d 3 h miho /Modules/CPLD_FPGA/S3AN01A/ S3AN01A opravy schématu (doplnění Errata) a přenesení změn do PCB. Diff
1894 4874 d 22 h kaklik /Modules/CommSerial/ETH02A/ Diff
1892 4883 d 22 h kaklik /Modules/CommSerial/ETH02A/ zacatek kresleni PCB Diff
1891 4884 d 0 h kaklik /Modules/ schema modulu s ehternet konektorem. Diff