Rev 1790 – ?author? – ?age? (?date?)
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CPLD_FPGA/
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Rev 1790
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1790
5034 d 8 h
miho
/Modules/
Přejmenování podstromu CPLD na CPLD_FPGA
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1062
6106 d 12 h
kakl
/Modules/CPLD/
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1049
6107 d 10 h
kakl
/Modules/
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1001
6129 d 6 h
miho
/Modules/
Doplněny metainformace pro sekci Modules (nejvyšší úroveň)
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927
6160 d 8 h
spirek
/Modules/CPLD/ISPLSI1016A/SCH/
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926
6160 d 8 h
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/Modules/CPLD/ISPLSI1016A/SCH/
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923
6164 d 10 h
kaklik
/Modules/CPLD/
upravy schematu chybi dodelat programovaci konektor.
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921
6165 d 12 h
spirek
/Modules/CPLD/ISPLSI1016A/SCH/
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920
6165 d 14 h
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