Rev Age Author Path Log message Diff Changes
1935 4969 d 9 h miho /Modules/CPLD_FPGA/S3AN01B/SCH/ Aktualizace schématu (formální změny). Pracovní verze seznamu součástek. Diff
/Modules/CPLD_FPGA/S3AN01B/SCH/S3AN01B_BOM.xls
/Modules/CPLD_FPGA/S3AN01B/SCH/S3AN01B_SCH.PDF
/Modules/CPLD_FPGA/S3AN01B/SCH/S3AN01B.ASC
/Modules/CPLD_FPGA/S3AN01B/SCH/S3AN01B.DSN
1906 4990 d 8 h miho /Modules/CPLD_FPGA/S3AN01A/ S3AN01A doplnění obrázků Diff
/Modules/CPLD_FPGA/S3AN01A/DOC
/Modules/CPLD_FPGA/S3AN01A/DOC/SRC
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/Modules/CPLD_FPGA/S3AN01A/S3AN01A_Top_Small.jpg
1899 4991 d 0 h miho /Modules/CPLD_FPGA/S3AN01A/ S3AN01A je již zastaralá konstrukce Diff
/Modules/CPLD_FPGA/S3AN01A/PrjInfo.txt
1898 4991 d 0 h miho /Modules/CPLD_FPGA/S3AN01B/ S3AN01B revize desky S3AN01A (s opravami) Diff
/Modules/CPLD_FPGA/S3AN01B
/Modules/CPLD_FPGA/S3AN01B/CAM_AMA
/Modules/CPLD_FPGA/S3AN01B/CAM_AMA/T1_AMA.pdf
/Modules/CPLD_FPGA/S3AN01B/CAM_AMA/V2_AMA.pdf
/Modules/CPLD_FPGA/S3AN01B/CAM_AMA/V2_DOC.pdf
/Modules/CPLD_FPGA/S3AN01B/CAM_AMA/V2_REAL.pdf
/Modules/CPLD_FPGA/S3AN01B/CAM_DOC
/Modules/CPLD_FPGA/S3AN01B/CAM_DOC/DRILL.pdf
/Modules/CPLD_FPGA/S3AN01B/CAM_DOC/O1.pdf
/Modules/CPLD_FPGA/S3AN01B/CAM_DOC/O2.pdf
/Modules/CPLD_FPGA/S3AN01B/CAM_PROFI
/Modules/CPLD_FPGA/S3AN01B/CAM_PROFI/!____!.txt
/Modules/CPLD_FPGA/S3AN01B/CAM_PROFI/BOARD.PHO
/Modules/CPLD_FPGA/S3AN01B/CAM_PROFI/DRILL.DRL
/Modules/CPLD_FPGA/S3AN01B/CAM_PROFI/DRILL.rep
/Modules/CPLD_FPGA/S3AN01B/CAM_PROFI/M1.PHO
/Modules/CPLD_FPGA/S3AN01B/CAM_PROFI/M2.PHO
/Modules/CPLD_FPGA/S3AN01B/CAM_PROFI/P2.PHO
/Modules/CPLD_FPGA/S3AN01B/CAM_PROFI/T1.PHO
/Modules/CPLD_FPGA/S3AN01B/CAM_PROFI/V1.PHO
/Modules/CPLD_FPGA/S3AN01B/CAM_PROFI/V2.PHO
/Modules/CPLD_FPGA/S3AN01B/PCB
/Modules/CPLD_FPGA/S3AN01B/PCB/S3AN01B.pcb
/Modules/CPLD_FPGA/S3AN01B/PrjInfo.txt
/Modules/CPLD_FPGA/S3AN01B/SCH
/Modules/CPLD_FPGA/S3AN01B/SCH/S3AN01B.ASC
/Modules/CPLD_FPGA/S3AN01B/SCH/S3AN01B.DSN
/Modules/CPLD_FPGA/S3AN01B/SCH/S3AN01B.OLB
/Modules/CPLD_FPGA/S3AN01B/VHDL
1897 4991 d 0 h miho /Modules/CPLD_FPGA/S3AN01A/SCH/ S3AN01A doplněny texty Diff
/Modules/CPLD_FPGA/S3AN01A/SCH/S3AN01A.DSN
/Modules/CPLD_FPGA/S3AN01A/SCH/S3AN01A_SCH.pdf
1896 4994 d 22 h miho /Modules/CPLD_FPGA/S3AN01A/ S3AN01A opravy schématu (doplnění Errata) a přenesení změn do PCB. Diff
/Modules/CPLD_FPGA/S3AN01A/PCB/S3AN01A.pcb
/Modules/CPLD_FPGA/S3AN01A/SCH/S3AN01A.ASC
/Modules/CPLD_FPGA/S3AN01A/SCH/S3AN01A.DSN
/Modules/CPLD_FPGA/S3AN01A/SCH/S3AN01A_BOM.xls
/Modules/CPLD_FPGA/S3AN01A/SCH/S3AN01A_SCH.pdf
1792 5051 d 23 h miho /Modules/CPLD_FPGA/S3AN01A/SCH/ Ještě pracovní knihovna projektu S3AN01A Diff
/Modules/CPLD_FPGA/S3AN01A/SCH/S3AN01A.OLB
1791 5051 d 23 h miho /Modules/CPLD_FPGA/S3AN01A/ Created FPGA module (school board) for XILINX Spartan 3 XC3S50AN gate array S3AN01A Diff
/Modules/CPLD_FPGA/S3AN01A
/Modules/CPLD_FPGA/S3AN01A/CAM_AMA
/Modules/CPLD_FPGA/S3AN01A/CAM_AMA/T1_AMA.pdf
/Modules/CPLD_FPGA/S3AN01A/CAM_AMA/V2_AMA.pdf
/Modules/CPLD_FPGA/S3AN01A/CAM_AMA/V2_REAL.pdf
/Modules/CPLD_FPGA/S3AN01A/CAM_DOC
/Modules/CPLD_FPGA/S3AN01A/CAM_DOC/Drill.pdf
/Modules/CPLD_FPGA/S3AN01A/CAM_DOC/O1.pdf
/Modules/CPLD_FPGA/S3AN01A/CAM_DOC/O2.pdf
/Modules/CPLD_FPGA/S3AN01A/CAM_DOC/V1.pdf
/Modules/CPLD_FPGA/S3AN01A/CAM_DOC/V2.pdf
/Modules/CPLD_FPGA/S3AN01A/CAM_PROFI
/Modules/CPLD_FPGA/S3AN01A/CAM_PROFI/BOARD.PHO
/Modules/CPLD_FPGA/S3AN01A/CAM_PROFI/DRILL.DRL
/Modules/CPLD_FPGA/S3AN01A/CAM_PROFI/DRILL.rep
/Modules/CPLD_FPGA/S3AN01A/CAM_PROFI/M1.PHO
/Modules/CPLD_FPGA/S3AN01A/CAM_PROFI/M2.PHO
/Modules/CPLD_FPGA/S3AN01A/CAM_PROFI/P2.PHO
/Modules/CPLD_FPGA/S3AN01A/CAM_PROFI/T1.PHO
/Modules/CPLD_FPGA/S3AN01A/CAM_PROFI/V1.PHO
/Modules/CPLD_FPGA/S3AN01A/CAM_PROFI/V2.PHO
/Modules/CPLD_FPGA/S3AN01A/PCB
/Modules/CPLD_FPGA/S3AN01A/PCB/S3AN01A.pcb
/Modules/CPLD_FPGA/S3AN01A/PrjInfo.txt
/Modules/CPLD_FPGA/S3AN01A/SCH
/Modules/CPLD_FPGA/S3AN01A/SCH/S3AN01A.ASC
/Modules/CPLD_FPGA/S3AN01A/SCH/S3AN01A.DSN
/Modules/CPLD_FPGA/S3AN01A/SCH/S3AN01A_BOM.xls
/Modules/CPLD_FPGA/S3AN01A/SCH/S3AN01A_SCH.pdf
1790 5051 d 23 h miho /Modules/ Přejmenování podstromu CPLD na CPLD_FPGA Diff
/Modules/CPLD_FPGA
/Modules/CPLD
/Modules/CPLD_FPGA/ISPLSI1016A/SCH/ISPLSI1016A.DBK
/Modules/CPLD_FPGA/ISPLSI1016A/SCH/ISPLSI1016A.ONL
/Modules/CPLD_FPGA/ISPLSI1016A/SCH/LATTICE.OBK
/Modules/CPLD_FPGA/ISPLSI1016A/SCH/isplsi1016a.opj
/Modules/CPLD_FPGA/DirInfo.txt
1062 6124 d 3 h kakl /Modules/CPLD/ Diff
/Modules/CPLD/DirInfo.txt
1049 6125 d 1 h kakl /Modules/ Diff
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/Modules/PowerSupply/Supply_Small.jpg
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1001 6146 d 21 h miho /Modules/ Doplněny metainformace pro sekci Modules (nejvyšší úroveň) Diff
/Modules/CPLD/DirInfo.txt
/Modules/CommSerial/DirInfo.txt
/Modules/PowerSW/DirInfo.txt
/Modules/AVR/info.cs.txt
/Modules/AVR/info.en.txt
/Modules/Audio/info.cs.txt
/Modules/Audio/info.en.txt
/Modules/CPLD/info.cs.txt
/Modules/CommIR/info.cs.txt
/Modules/CommIR/info.en.txt
/Modules/CommSerial/info.cs.txt
/Modules/H_Bridge/info.cs.txt
/Modules/H_Bridge/info.en.txt
/Modules/HumanInterfaces/info.cs.txt
/Modules/HumanInterfaces/info.en.txt
/Modules/CommIR/DirInfo.txt
/Modules/CommRF/DirInfo.txt
/Modules/H_Bridge/DirInfo.txt
/Modules/HumanInterfaces/DirInfo.txt
/Modules/Measuring/DirInfo.txt
/Modules/OpAmps/DirInfo.txt
/Modules/PIC/DirInfo.txt
/Modules/PowerSupply/DirInfo.txt
/Modules/Sensors/DirInfo.txt
/Modules/Universal/DirInfo.txt
927 6177 d 23 h spirek /Modules/CPLD/ISPLSI1016A/SCH/ Diff
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/Modules/CPLD/ISPLSI1016A/SCH/isplsi1016a.opj
926 6177 d 23 h spirek /Modules/CPLD/ISPLSI1016A/SCH/ Diff
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/Modules/CPLD/ISPLSI1016A/SCH/LATTICE.OLB
923 6182 d 2 h kaklik /Modules/CPLD/ upravy schematu chybi dodelat programovaci konektor. Diff
/Modules/CPLD/info.cs.txt
/Modules/CPLD/ISPLSI1016A/SCH/ISPLSI1016A.DBK
/Modules/CPLD/ISPLSI1016A/SCH/ISPLSI1016A.ONL
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921 6183 d 3 h spirek /Modules/CPLD/ISPLSI1016A/SCH/ Diff
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920 6183 d 5 h spirek /Modules/CPLD/ Diff
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/Modules/CPLD/ISPLSI1016A/SCH/ISPLSI1016A.DBK
/Modules/CPLD/ISPLSI1016A/SCH/ISPLSI1016A.DSN
/Modules/CPLD/ISPLSI1016A/SCH/ISPLSI1016A.ONL
/Modules/CPLD/ISPLSI1016A/SCH/ISPLSI1016A.opj
/Modules/CPLD/ISPLSI1016A/SCH/LATTICE.OBK
/Modules/CPLD/ISPLSI1016A/SCH/LATTICE.OLB