1906 |
4906 d 5 h |
miho |
/Modules/CPLD_FPGA/S3AN01A/ |
S3AN01A doplnění obrázků |
Diff |
/Modules/CPLD_FPGA/S3AN01A/DOC /Modules/CPLD_FPGA/S3AN01A/DOC/SRC /Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Drát1.jpg /Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Drát2a.jpg /Modules/CPLD_FPGA/S3AN01A/DOC/SRC/Drát2b.jpg /Modules/CPLD_FPGA/S3AN01A/DOC/SRC/S3AN01A_Bot_Big.jpg /Modules/CPLD_FPGA/S3AN01A/DOC/SRC/S3AN01A_Bot_Small.jpg /Modules/CPLD_FPGA/S3AN01A/DOC/SRC/S3AN01A_Top_Big.jpg /Modules/CPLD_FPGA/S3AN01A/DOC/SRC/S3AN01A_Top_Small.jpg /Modules/CPLD_FPGA/S3AN01A/S3AN01A_Bot_Small.jpg /Modules/CPLD_FPGA/S3AN01A/S3AN01A_Top_Small.jpg |
|
1899 |
4906 d 21 h |
miho |
/Modules/CPLD_FPGA/S3AN01A/ |
S3AN01A je již zastaralá konstrukce |
Diff |
/Modules/CPLD_FPGA/S3AN01A/PrjInfo.txt |
|
1898 |
4906 d 21 h |
miho |
/Modules/CPLD_FPGA/S3AN01B/ |
S3AN01B revize desky S3AN01A (s opravami) |
Diff |
/Modules/CPLD_FPGA/S3AN01B /Modules/CPLD_FPGA/S3AN01B/CAM_AMA /Modules/CPLD_FPGA/S3AN01B/CAM_AMA/T1_AMA.pdf /Modules/CPLD_FPGA/S3AN01B/CAM_AMA/V2_AMA.pdf /Modules/CPLD_FPGA/S3AN01B/CAM_AMA/V2_DOC.pdf /Modules/CPLD_FPGA/S3AN01B/CAM_AMA/V2_REAL.pdf /Modules/CPLD_FPGA/S3AN01B/CAM_DOC /Modules/CPLD_FPGA/S3AN01B/CAM_DOC/DRILL.pdf /Modules/CPLD_FPGA/S3AN01B/CAM_DOC/O1.pdf /Modules/CPLD_FPGA/S3AN01B/CAM_DOC/O2.pdf /Modules/CPLD_FPGA/S3AN01B/CAM_PROFI /Modules/CPLD_FPGA/S3AN01B/CAM_PROFI/!____!.txt /Modules/CPLD_FPGA/S3AN01B/CAM_PROFI/BOARD.PHO /Modules/CPLD_FPGA/S3AN01B/CAM_PROFI/DRILL.DRL /Modules/CPLD_FPGA/S3AN01B/CAM_PROFI/DRILL.rep /Modules/CPLD_FPGA/S3AN01B/CAM_PROFI/M1.PHO /Modules/CPLD_FPGA/S3AN01B/CAM_PROFI/M2.PHO /Modules/CPLD_FPGA/S3AN01B/CAM_PROFI/P2.PHO /Modules/CPLD_FPGA/S3AN01B/CAM_PROFI/T1.PHO /Modules/CPLD_FPGA/S3AN01B/CAM_PROFI/V1.PHO /Modules/CPLD_FPGA/S3AN01B/CAM_PROFI/V2.PHO /Modules/CPLD_FPGA/S3AN01B/PCB /Modules/CPLD_FPGA/S3AN01B/PCB/S3AN01B.pcb /Modules/CPLD_FPGA/S3AN01B/PrjInfo.txt /Modules/CPLD_FPGA/S3AN01B/SCH /Modules/CPLD_FPGA/S3AN01B/SCH/S3AN01B.ASC /Modules/CPLD_FPGA/S3AN01B/SCH/S3AN01B.DSN /Modules/CPLD_FPGA/S3AN01B/SCH/S3AN01B.OLB /Modules/CPLD_FPGA/S3AN01B/VHDL |
|
1897 |
4906 d 21 h |
miho |
/Modules/CPLD_FPGA/S3AN01A/SCH/ |
S3AN01A doplněny texty |
Diff |
/Modules/CPLD_FPGA/S3AN01A/SCH/S3AN01A.DSN /Modules/CPLD_FPGA/S3AN01A/SCH/S3AN01A_SCH.pdf |
|
1896 |
4910 d 19 h |
miho |
/Modules/CPLD_FPGA/S3AN01A/ |
S3AN01A opravy schématu (doplnění Errata) a přenesení změn do PCB. |
Diff |
/Modules/CPLD_FPGA/S3AN01A/PCB/S3AN01A.pcb /Modules/CPLD_FPGA/S3AN01A/SCH/S3AN01A.ASC /Modules/CPLD_FPGA/S3AN01A/SCH/S3AN01A.DSN /Modules/CPLD_FPGA/S3AN01A/SCH/S3AN01A_BOM.xls /Modules/CPLD_FPGA/S3AN01A/SCH/S3AN01A_SCH.pdf |
|
1792 |
4967 d 20 h |
miho |
/Modules/CPLD_FPGA/S3AN01A/SCH/ |
Ještě pracovní knihovna projektu S3AN01A |
Diff |
/Modules/CPLD_FPGA/S3AN01A/SCH/S3AN01A.OLB |
|
1791 |
4967 d 20 h |
miho |
/Modules/CPLD_FPGA/S3AN01A/ |
Created FPGA module (school board) for XILINX Spartan 3 XC3S50AN gate array S3AN01A |
Diff |
/Modules/CPLD_FPGA/S3AN01A /Modules/CPLD_FPGA/S3AN01A/CAM_AMA /Modules/CPLD_FPGA/S3AN01A/CAM_AMA/T1_AMA.pdf /Modules/CPLD_FPGA/S3AN01A/CAM_AMA/V2_AMA.pdf /Modules/CPLD_FPGA/S3AN01A/CAM_AMA/V2_REAL.pdf /Modules/CPLD_FPGA/S3AN01A/CAM_DOC /Modules/CPLD_FPGA/S3AN01A/CAM_DOC/Drill.pdf /Modules/CPLD_FPGA/S3AN01A/CAM_DOC/O1.pdf /Modules/CPLD_FPGA/S3AN01A/CAM_DOC/O2.pdf /Modules/CPLD_FPGA/S3AN01A/CAM_DOC/V1.pdf /Modules/CPLD_FPGA/S3AN01A/CAM_DOC/V2.pdf /Modules/CPLD_FPGA/S3AN01A/CAM_PROFI /Modules/CPLD_FPGA/S3AN01A/CAM_PROFI/BOARD.PHO /Modules/CPLD_FPGA/S3AN01A/CAM_PROFI/DRILL.DRL /Modules/CPLD_FPGA/S3AN01A/CAM_PROFI/DRILL.rep /Modules/CPLD_FPGA/S3AN01A/CAM_PROFI/M1.PHO /Modules/CPLD_FPGA/S3AN01A/CAM_PROFI/M2.PHO /Modules/CPLD_FPGA/S3AN01A/CAM_PROFI/P2.PHO /Modules/CPLD_FPGA/S3AN01A/CAM_PROFI/T1.PHO /Modules/CPLD_FPGA/S3AN01A/CAM_PROFI/V1.PHO /Modules/CPLD_FPGA/S3AN01A/CAM_PROFI/V2.PHO /Modules/CPLD_FPGA/S3AN01A/PCB /Modules/CPLD_FPGA/S3AN01A/PCB/S3AN01A.pcb /Modules/CPLD_FPGA/S3AN01A/PrjInfo.txt /Modules/CPLD_FPGA/S3AN01A/SCH /Modules/CPLD_FPGA/S3AN01A/SCH/S3AN01A.ASC /Modules/CPLD_FPGA/S3AN01A/SCH/S3AN01A.DSN /Modules/CPLD_FPGA/S3AN01A/SCH/S3AN01A_BOM.xls /Modules/CPLD_FPGA/S3AN01A/SCH/S3AN01A_SCH.pdf |
|
1790 |
4967 d 20 h |
miho |
/Modules/ |
Přejmenování podstromu CPLD na CPLD_FPGA |
Diff |
/Modules/CPLD_FPGA |
/Modules/CPLD /Modules/CPLD_FPGA/ISPLSI1016A/SCH/ISPLSI1016A.DBK /Modules/CPLD_FPGA/ISPLSI1016A/SCH/ISPLSI1016A.ONL /Modules/CPLD_FPGA/ISPLSI1016A/SCH/LATTICE.OBK /Modules/CPLD_FPGA/ISPLSI1016A/SCH/isplsi1016a.opj |
/Modules/CPLD_FPGA/DirInfo.txt |
|
1062 |
6040 d 0 h |
kakl |
/Modules/CPLD/ |
|
Diff |
/Modules/CPLD/DirInfo.txt |
|
1049 |
6040 d 22 h |
kakl |
/Modules/ |
|
Diff |
/Modules/CPLD/cpld_Small.jpg /Modules/CommRF/RC_Small.jpg /Modules/H_Bridge/stepper_Small.jpg /Modules/Measuring/probe_Small.jpg /Modules/OpAmps/opamp_Small.jpg /Modules/PowerSW/fet_Small.jpg /Modules/PowerSupply/Supply_Small.jpg /Modules/Sensors/sensors_Small.jpg /Modules/Universal/BASE162101A_Small.jpg |
|
1001 |
6062 d 18 h |
miho |
/Modules/ |
Doplněny metainformace pro sekci Modules (nejvyšší úroveň) |
Diff |
/Modules/CPLD/DirInfo.txt /Modules/CommSerial/DirInfo.txt /Modules/PowerSW/DirInfo.txt |
/Modules/AVR/info.cs.txt /Modules/AVR/info.en.txt /Modules/Audio/info.cs.txt /Modules/Audio/info.en.txt /Modules/CPLD/info.cs.txt /Modules/CommIR/info.cs.txt /Modules/CommIR/info.en.txt /Modules/CommSerial/info.cs.txt /Modules/H_Bridge/info.cs.txt /Modules/H_Bridge/info.en.txt /Modules/HumanInterfaces/info.cs.txt /Modules/HumanInterfaces/info.en.txt |
/Modules/CommIR/DirInfo.txt /Modules/CommRF/DirInfo.txt /Modules/H_Bridge/DirInfo.txt /Modules/HumanInterfaces/DirInfo.txt /Modules/Measuring/DirInfo.txt /Modules/OpAmps/DirInfo.txt /Modules/PIC/DirInfo.txt /Modules/PowerSupply/DirInfo.txt /Modules/Sensors/DirInfo.txt /Modules/Universal/DirInfo.txt |
|
927 |
6093 d 20 h |
spirek |
/Modules/CPLD/ISPLSI1016A/SCH/ |
|
Diff |
/Modules/CPLD/ISPLSI1016A/SCH/ISPLSI1016A.DBK /Modules/CPLD/ISPLSI1016A/SCH/ISPLSI1016A.ONL /Modules/CPLD/ISPLSI1016A/SCH/LIBRARY1.OLB /Modules/CPLD/ISPLSI1016A/SCH/isplsi1016a.opj |
|
926 |
6093 d 20 h |
spirek |
/Modules/CPLD/ISPLSI1016A/SCH/ |
|
Diff |
/Modules/CPLD/ISPLSI1016A/SCH/ISPLSI1016A.ASC /Modules/CPLD/ISPLSI1016A/SCH/ISPLSI1016A.DSN /Modules/CPLD/ISPLSI1016A/SCH/LATTICE.OBK /Modules/CPLD/ISPLSI1016A/SCH/LATTICE.OLB |
|
923 |
6097 d 23 h |
kaklik |
/Modules/CPLD/ |
upravy schematu chybi dodelat programovaci konektor. |
Diff |
/Modules/CPLD/info.cs.txt |
/Modules/CPLD/ISPLSI1016A/SCH/ISPLSI1016A.DBK /Modules/CPLD/ISPLSI1016A/SCH/ISPLSI1016A.ONL /Modules/CPLD/ISPLSI1016A/SCH/ISPLSI1016A.opj |
/Modules/CPLD/ISPLSI1016A/SCH/ISPLSI1016A.DSN |
|
921 |
6099 d 0 h |
spirek |
/Modules/CPLD/ISPLSI1016A/SCH/ |
|
Diff |
/Modules/CPLD/ISPLSI1016A/SCH/ISPLSI1016A.ASC /Modules/CPLD/ISPLSI1016A/SCH/ISPLSI1016A.DBK /Modules/CPLD/ISPLSI1016A/SCH/ISPLSI1016A.DSN /Modules/CPLD/ISPLSI1016A/SCH/ISPLSI1016A.ONL /Modules/CPLD/ISPLSI1016A/SCH/ISPLSI1016A.opj |
|
920 |
6099 d 2 h |
spirek |
/Modules/CPLD/ |
|
Diff |
/Modules/CPLD /Modules/CPLD/ISPLSI1016A /Modules/CPLD/ISPLSI1016A/SCH /Modules/CPLD/ISPLSI1016A/SCH/ISPLSI1016A.ASC /Modules/CPLD/ISPLSI1016A/SCH/ISPLSI1016A.DBK /Modules/CPLD/ISPLSI1016A/SCH/ISPLSI1016A.DSN /Modules/CPLD/ISPLSI1016A/SCH/ISPLSI1016A.ONL /Modules/CPLD/ISPLSI1016A/SCH/ISPLSI1016A.opj /Modules/CPLD/ISPLSI1016A/SCH/LATTICE.OBK /Modules/CPLD/ISPLSI1016A/SCH/LATTICE.OLB |
|