Rev Age Author Path Log message Diff Changes
3091 4161 d 8 h miho /Modules/CPLD_FPGA/XILINX_CHIPSCOPE/ Demo aplikace Xilinx ChipScope pro S3AN01 s použitím Xilinx Virtual Cable technologie Diff
/Modules/CPLD_FPGA/XILINX_CHIPSCOPE
/Modules/CPLD_FPGA/XILINX_CHIPSCOPE/ANALYSER
/Modules/CPLD_FPGA/XILINX_CHIPSCOPE/ANALYSER/Analyser.ini
/Modules/CPLD_FPGA/XILINX_CHIPSCOPE/ANALYSER/Analyser_18_1024.cpj
/Modules/CPLD_FPGA/XILINX_CHIPSCOPE/ANALYSER/Analyser_9_2048.cpj
/Modules/CPLD_FPGA/XILINX_CHIPSCOPE/BIN
/Modules/CPLD_FPGA/XILINX_CHIPSCOPE/BIN/13.3
/Modules/CPLD_FPGA/XILINX_CHIPSCOPE/BIN/13.3/S3AN01_ChipScope_18x1024.bit
/Modules/CPLD_FPGA/XILINX_CHIPSCOPE/BIN/13.3/S3AN01_ChipScope_9x2048.bit
/Modules/CPLD_FPGA/XILINX_CHIPSCOPE/BIN/13.3/Version
/Modules/CPLD_FPGA/XILINX_CHIPSCOPE/BIN/14.5
/Modules/CPLD_FPGA/XILINX_CHIPSCOPE/BIN/14.5/S3AN01_ChipScope_18x1024.bit
/Modules/CPLD_FPGA/XILINX_CHIPSCOPE/BIN/14.5/S3AN01_ChipScope_9x2048.bit
/Modules/CPLD_FPGA/XILINX_CHIPSCOPE/BIN/14.5/Version
/Modules/CPLD_FPGA/XILINX_CHIPSCOPE/COREGEN
/Modules/CPLD_FPGA/XILINX_CHIPSCOPE/COREGEN/!____!.txt
/Modules/CPLD_FPGA/XILINX_CHIPSCOPE/COREGEN/ChipScope_ICON.xco
/Modules/CPLD_FPGA/XILINX_CHIPSCOPE/COREGEN/ChipScope_ILA_18_1024.xco
/Modules/CPLD_FPGA/XILINX_CHIPSCOPE/COREGEN/ChipScope_ILA_9_2048.xco
/Modules/CPLD_FPGA/XILINX_CHIPSCOPE/COREGEN/ChipScope_VIO_FreqSel.xco
/Modules/CPLD_FPGA/XILINX_CHIPSCOPE/COREGEN/ChipScope_VIO_UserOut.xco
/Modules/CPLD_FPGA/XILINX_CHIPSCOPE/COREGEN/coregen.cgp
/Modules/CPLD_FPGA/XILINX_CHIPSCOPE/DirInfo.txt
/Modules/CPLD_FPGA/XILINX_CHIPSCOPE/MAKE
/Modules/CPLD_FPGA/XILINX_CHIPSCOPE/MAKE/FindXilinxTools.cmd
/Modules/CPLD_FPGA/XILINX_CHIPSCOPE/MAKE/make_CoreGen.cmd
/Modules/CPLD_FPGA/XILINX_CHIPSCOPE/MAKE/make_S3AN01_ChipScope.cmd
/Modules/CPLD_FPGA/XILINX_CHIPSCOPE/MAKE/make_all.cmd
/Modules/CPLD_FPGA/XILINX_CHIPSCOPE/MAKE/run_ChipScopeAnalyser_18_1024.cmd
/Modules/CPLD_FPGA/XILINX_CHIPSCOPE/MAKE/run_ChipScopeAnalyser_9_2048.cmd
/Modules/CPLD_FPGA/XILINX_CHIPSCOPE/VHDL
/Modules/CPLD_FPGA/XILINX_CHIPSCOPE/VHDL/S3AN01_ChipScope.ucf
/Modules/CPLD_FPGA/XILINX_CHIPSCOPE/VHDL/S3AN01_ChipScope.vhd