Rev Age Author Path Log message Diff Changes
3396 3983 d 22 h kaklik /Modules/Clock/CLKDIV01A/ vygenerovanitechnologickych vystupu Diff
/Modules/Clock/CLKDIV01A/CAM_PROFI/BOARD.PHO
/Modules/Clock/CLKDIV01A/CAM_PROFI/DRILL.DRL
/Modules/Clock/CLKDIV01A/CAM_PROFI/M1.PHO
/Modules/Clock/CLKDIV01A/CAM_PROFI/M2.PHO
/Modules/Clock/CLKDIV01A/CAM_PROFI/T1.PHO
/Modules/Clock/CLKDIV01A/CAM_PROFI/V1.PHO
/Modules/Clock/CLKDIV01A/CAM_PROFI/V2.PHO
/Modules/Clock/CLKDIV01A/PCB/CLKDIV.pcb
3395 3983 d 23 h kaklik /Modules/Clock/CLKDIV01A/ Diff
/Modules/Clock/CLKDIV01A/PCB/CLKDIV.pcb
/Modules/Clock/CLKDIV01A/SCH/CLKDIV.DSN
/Modules/Clock/CLKDIV01A/SCH/CLKDIV.asc
3394 3983 d 23 h kaklik /Modules/Clock/CLKDIV01A/ ulozeni verze pred otocenim konektoru. Diff
/Modules/Clock/CLKDIV01A/PCB/CLKDIV.pcb
/Modules/Clock/CLKDIV01A/SCH/CLKDIV.DSN
3393 3984 d 0 h kaklik /Modules/Clock/CLKDIV01A/PCB/ zapojeni diff paru. Diff
/Modules/Clock/CLKDIV01A/PCB/CLKDIV.pcb
3392 3984 d 0 h kaklik /Modules/Clock/CLKDIV01A/PCB/ Diff
/Modules/Clock/CLKDIV01A/PCB/CLKDIV.pcb
3391 3984 d 0 h kaklik /Modules/Clock/CLKDIV01A/PCB/ prvni slusne zapojeni diferencialnich paru. Diff
/Modules/Clock/CLKDIV01A/PCB/CLKDIV.pcb
3389 3984 d 1 h kaklik /Modules/Clock/CLKDIV01A/PCB/ otoceni a srovnani konektoru Diff
/Modules/Clock/CLKDIV01A/PCB/CLKDIV.pcb
3388 3984 d 2 h kaklik /Modules/Clock/CLKDIV01A/ Diff
/Modules/Clock/CLKDIV01A/PCB/CLKDIV.pcb
/Modules/Clock/CLKDIV01A/SCH/CLKDIV.DSN
/Modules/Clock/CLKDIV01A/SCH/CLKDIV.opj
3387 3984 d 3 h kaklik /Modules/Clock/CLKDIV01A/ Diff
/Modules/Clock/CLKDIV01A/SCH/clkdiv.pdf
/Modules/Clock/CLKDIV01A/PCB/CLKDIV.pcb
/Modules/Clock/CLKDIV01A/SCH/CLKDIV.DSN
/Modules/Clock/CLKDIV01A/SCH/CLKDIV.asc
/Modules/Clock/CLKDIV01A/SCH/CLKDIV.opj
3386 3984 d 6 h kaklik /Modules/Clock/CLKDIV01A/ aktualizace podle noveho navrhu. Diff
/Modules/Clock/CLKDIV01A/pdf/NB6L239.PDF
/Modules/Clock/CLKDIV01A/pdf/sy100s834-l.pdf
/Modules/Clock/CLKDIV01A/SCH/navrh.PDF
3385 3984 d 22 h kaklik /Modules/Clock/CLKDIV01A/PCB/ zkouska zaroutovatelnosti. Diff
/Modules/Clock/CLKDIV01A/PCB/CLKDIV.pcb
3384 3984 d 22 h kaklik /Modules/Clock/CLKDIV01A/ prvni schema a plosny spoj modulu delicky. Diff
/Modules/Clock/CLKDIV01A/PCB/CLKDIV.pcb
/Modules/Clock/CLKDIV01A/SCH/CLKDIV.DSN
/Modules/Clock/CLKDIV01A/SCH/CLKDIV.asc
/Modules/Clock/CLKDIV01A/SCH/CLKDIV.opj
3383 3985 d 0 h kaklik /Modules/ zalozeni noveho modulu pro delicku hodin. Diff
/Modules/CPLD_FPGA/S6AN01A/SCH/navrh.PDF
/Modules/Clock/CLKDIV01A
/Modules/Clock/CLKDIV01A/CAM_AMA
/Modules/Clock/CLKDIV01A/CAM_DOC
/Modules/Clock/CLKDIV01A/CAM_PROFI
/Modules/Clock/CLKDIV01A/CAM_PROFI/Preview.gvp
/Modules/Clock/CLKDIV01A/DOC
/Modules/Clock/CLKDIV01A/DOC/HTML
/Modules/Clock/CLKDIV01A/DOC/SRC
/Modules/Clock/CLKDIV01A/PCB
/Modules/Clock/CLKDIV01A/PrjInfo.txt
/Modules/Clock/CLKDIV01A/SCH
/Modules/Clock/CLKDIV01A/SCH/navrh.PDF
/Modules/Clock/CLKDIV01A/SW
/Modules/Clock/CLKDIV01A/pdf
/Modules/Clock/CLKDIV01A/pdf/sy100s834-l.pdf