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Rev Age Author Path Log message Diff
1572 5206 d 19 h kaklik / poznamky problemu Diff
1555 5235 d 4 h kaklik /Modules/Clock/ pokus s ladenim delky spoju Diff
1548 5245 d 15 h kaklik /Modules/Clock/ aktualizace popisu modulů. Diff
1547 5245 d 16 h kaklik /Modules/Clock/CLKGEN01A/ Fotky LO. Diff
1546 5248 d 13 h kaklik /Modules/Clock/CLKGEN01A/ seznam chyb. Diff
1545 5248 d 14 h kaklik /Modules/Clock/CLKGEN01A/ potisk Diff
1544 5249 d 15 h kaklik / Diff
1543 5249 d 15 h kaklik /Modules/Clock/CLKGEN01A/ vymena CAM vystupu Diff
1542 5249 d 17 h kaklik /Modules/Clock/CLKGEN01A/ generovani technologickych dat. Diff
1541 5250 d 5 h kaklik /Modules/Clock/CLKGEN01A/PCB/ Diff
1540 5250 d 6 h kaklik /Modules/Clock/CLKGEN01A/PCB/ Diff
1539 5250 d 6 h kaklik /Modules/Clock/CLKGEN01A/PCB/ Diff
1531 5267 d 5 h kaklik /Modules/Clock/CLKGEN01A/ pridani chybejicich terminacnich odporu.. Diff
1530 5267 d 12 h kaklik /Modules/Clock/CLKGEN01A/ Temer konecna verze PCB pro Si570. Respektive Si5XX Diff
1529 5267 d 14 h kaklik /Modules/Clock/CLKGEN01A/ Vpodstate hotovy tistak, jeste bude pokus s otocenim konektoru. Diff
1528 5267 d 15 h kaklik /Modules/ Diff
1527 5267 d 16 h kaklik /Modules/Clock/CLKGEN01A/SCH/ pridani zapomenutych der a fidu znacek Diff
1526 5268 d 7 h kaklik /Modules/Clock/CLKGEN01A/PCB/ Diff
1525 5268 d 7 h kaklik /Modules/Clock/CLKGEN01A/PCB/ zacatek prace na plosnem spoji. Diff
1524 5268 d 12 h kaklik /Modules/Clock/CLKGEN01A/SCH/ export dat pro PADs. Diff