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Rev Age Author Path Log message Diff
1932 5031 d 6 h kaklik /Modules/Clock/CLKGEN01B/DOC/ prejmenovani podle konvence Diff
1931 5033 d 22 h kaklik /Modules/TDC/GP201A/SW/PICinterface/ testovani TDC Diff
1930 5034 d 2 h kaklik / preklad kodu Diff
1914 5044 d 6 h kaklik /Modules/CommSerial/ETH02A/ Vygenerovani potisku Diff
1913 5044 d 6 h kaklik /Modules/CommSerial/ETH02A/ prace na modulu pro ethernet Diff
1912 5044 d 7 h kaklik /Modules/CommSerial/ETH02A/ prace na modulu pro ethernet Diff
1911 5045 d 1 h kaklik /Modules/ Vyvoj tistaku pro ETHERNET. Diff
1910 5046 d 1 h kaklik /Modules/ARM/STM32F10xRxT/ nalezene chyby Diff
1908 5047 d 20 h klimma /Modules/PowerSupply/klimma/ Diff
1907 5048 d 1 h kaklik /Modules/PowerSupply/MC3406301A/pdf/ dokumentace Diff
1906 5049 d 12 h miho /Modules/CPLD_FPGA/S3AN01A/ S3AN01A doplnění obrázků Diff
1899 5050 d 4 h miho /Modules/CPLD_FPGA/S3AN01A/ S3AN01A je již zastaralá konstrukce Diff
1898 5050 d 4 h miho /Modules/CPLD_FPGA/S3AN01B/ S3AN01B revize desky S3AN01A (s opravami) Diff
1897 5050 d 4 h miho /Modules/CPLD_FPGA/S3AN01A/SCH/ S3AN01A doplněny texty Diff
1896 5054 d 2 h miho /Modules/CPLD_FPGA/S3AN01A/ S3AN01A opravy schématu (doplnění Errata) a přenesení změn do PCB. Diff
1894 5054 d 21 h kaklik /Modules/CommSerial/ETH02A/ Diff
1892 5063 d 21 h kaklik /Modules/CommSerial/ETH02A/ zacatek kresleni PCB Diff
1891 5063 d 22 h kaklik /Modules/ schema modulu s ehternet konektorem. Diff
1890 5066 d 3 h kaklik /Modules/ARM/STM32F10xRxT/ Diff
1888 5066 d 4 h kaklik / vygenerevani osazovaku Diff