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Rev Age Author Path Log message Diff
1544 5054 d 18 h kaklik / Diff
1543 5054 d 18 h kaklik /Modules/Clock/CLKGEN01A/ vymena CAM vystupu Diff
1542 5054 d 19 h kaklik /Modules/Clock/CLKGEN01A/ generovani technologickych dat. Diff
1541 5055 d 8 h kaklik /Modules/Clock/CLKGEN01A/PCB/ Diff
1540 5055 d 9 h kaklik /Modules/Clock/CLKGEN01A/PCB/ Diff
1539 5055 d 9 h kaklik /Modules/Clock/CLKGEN01A/PCB/ Diff
1538 5058 d 9 h kaklik /Modules/Clock/ Rozhodnuti pouzit pro CLKHUB jinou soucastku, protoze AD95010 nejde zapojit. Diff
1537 5058 d 15 h kaklik /Modules/Clock/CLKHUB01A/ zacatek navrhu PCB Diff
1536 5059 d 6 h kaklik /Modules/Clock/CLKHUB01A/SCH/ Temer hotove schema Diff
1535 5068 d 13 h kaklik /Modules/CommSerial/USBIO01A/DOC/SRC/ fotky k modulu USBIO01A Diff
1534 5068 d 13 h kaklik /Modules/CommSerial/USBIO01A/ fotky k modulu USBIO01A Diff
1533 5068 d 13 h kaklik /Modules/ADconverters/ADCmonoSPI01B/ fotky k modulu ADCmonoSPI01B Diff
1531 5072 d 8 h kaklik /Modules/Clock/CLKGEN01A/ pridani chybejicich terminacnich odporu.. Diff
1530 5072 d 15 h kaklik /Modules/Clock/CLKGEN01A/ Temer konecna verze PCB pro Si570. Respektive Si5XX Diff
1529 5072 d 17 h kaklik /Modules/Clock/CLKGEN01A/ Vpodstate hotovy tistak, jeste bude pokus s otocenim konektoru. Diff
1528 5072 d 18 h kaklik /Modules/ Diff
1527 5072 d 19 h kaklik /Modules/Clock/CLKGEN01A/SCH/ pridani zapomenutych der a fidu znacek Diff
1526 5073 d 9 h kaklik /Modules/Clock/CLKGEN01A/PCB/ Diff
1525 5073 d 10 h kaklik /Modules/Clock/CLKGEN01A/PCB/ zacatek prace na plosnem spoji. Diff
1524 5073 d 15 h kaklik /Modules/Clock/CLKGEN01A/SCH/ export dat pro PADs. Diff