/Designs/HAM Constructions/SDRX02A/DOC/2014-05-12KakonaDiplThesisCTU-Prague.pdf
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/Designs/HAM Constructions/SDRX02A/HDL/
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/Designs/HAM Constructions/SDRX02A/HDL/modules/
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/Designs/HAM Constructions/SDRX02A/HDL/modules/comm/
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/Designs/HAM Constructions/SDRX02A/HDL/modules/comm/spi_master_transmit.vhd
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/Designs/HAM Constructions/SDRX02A/HDL/modules/core_generator_ml605/
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/Designs/HAM Constructions/SDRX02A/HDL/modules/core_generator_ml605/clk_125MHz_to_6MHz.xco
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/Designs/HAM Constructions/SDRX02A/HDL/modules/core_generator_ml605/fifo_32x512.xco
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/Designs/HAM Constructions/SDRX02A/HDL/modules/core_generator_ml605/fifo_32x512_dualclk_fwft.xco
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/Designs/HAM Constructions/SDRX02A/HDL/modules/core_generator_ml605/fifo_32x512_walmostfull.xco
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/Designs/HAM Constructions/SDRX02A/HDL/modules/fifo_related/
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/Designs/HAM Constructions/SDRX02A/HDL/modules/fifo_related/fifo_to_enable.vhd
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/Designs/HAM Constructions/SDRX02A/HDL/modules/information/
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/Designs/HAM Constructions/SDRX02A/HDL/modules/information/information_block.vhd
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/Designs/HAM Constructions/SDRX02A/HDL/modules/sychro1/
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/Designs/HAM Constructions/SDRX02A/HDL/modules/sychro1/clock_divider.vhd
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/Designs/HAM Constructions/SDRX02A/HDL/modules/sychro1/up_counter.vhd
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/Designs/HAM Constructions/SDRX02A/HDL/modules/sychro1/up_counter_stdlv.vhd
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/Designs/HAM Constructions/SDRX02A/HDL/modules/xilly/
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/Designs/HAM Constructions/SDRX02A/HDL/modules/xilly/xilly_userlogiccmp_wrapper.vhd
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/Designs/HAM Constructions/SDRX02A/HDL/project_src/
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/Designs/HAM Constructions/SDRX02A/HDL/project_src/bitslip_compensation.vhd
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/Designs/HAM Constructions/SDRX02A/HDL/project_src/glue_data.vhd
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/Designs/HAM Constructions/SDRX02A/HDL/project_src/information_data.vhd
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/Designs/HAM Constructions/SDRX02A/HDL/project_src/iserdes_clock_generator.vhd
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/Designs/HAM Constructions/SDRX02A/HDL/project_src/kakona_package.vhd
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/Designs/HAM Constructions/SDRX02A/HDL/project_src/lo_divider_wrapper.vhd
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/Designs/HAM Constructions/SDRX02A/HDL/project_src/multiplexer_from_fifos.vhd
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/Designs/HAM Constructions/SDRX02A/HDL/project_src/myserdes_ddr.vhd
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/Designs/HAM Constructions/SDRX02A/HDL/project_src/myserdes_ddr_wrapper.vhd
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/Designs/HAM Constructions/SDRX02A/HDL/project_src/processing_block.vhd
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/Designs/HAM Constructions/SDRX02A/HDL/project_src/saw_generator_wrapper.vhd
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/Designs/HAM Constructions/SDRX02A/HDL/project_src/spi_transmitter_wrapper2.vhd
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/Designs/HAM Constructions/SDRX02A/HDL/project_src/swap_endianness.vhd
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/Designs/HAM Constructions/SDRX02A/HDL/project_src/userlogiccmp_template.vhd
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/Designs/HAM Constructions/SDRX02A/HDL/project_src/xilly/
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/Designs/HAM Constructions/SDRX02A/HDL/project_src/xilly/xilly_toplevel.userlogiccmp_kakona.vhd
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/Designs/HAM Constructions/SDRX02A/HDL/project_src/xillybus_ml605_kakona.ucf
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/Designs/HAM Constructions/SDRX02A/HDL/README.txt
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/Designs/HAM Constructions/SDRX02A/pdf/fiberoptics/
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/Designs/HAM Constructions/SDRX02A/pdf/fiberoptics/cable.txt
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/Designs/HAM Constructions/SDRX02A/PrjInfo.txt
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/Designs/HAM Constructions/SDRX02A/SCH/Coherent_UHF_SDR_receiver.dia
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/Designs/HAM Constructions/SDRX02A/SCH/Coherent_UHF_SDR_receiver_demonstrator.dia
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/Designs/HAM Constructions/SDRX02A/SCH/UHF_SDR_receiver.png
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/Designs/HAM Constructions/SDRX02A/SW/GRC/
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/Designs/HAM Constructions/SDRX02A/SW/GRC/AM_receiver.grc
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/Designs/HAM Constructions/SDRX02A/SW/GRC/FM_receiver.grc
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/Designs/HAM Constructions/SDRX02A/SW/GRC/FM_stanice.txt
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/Designs/HAM Constructions/SDRX02A/SW/GRC/Grabber.grc
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/Designs/HAM Constructions/SDRX02A/SW/GRC/Grabber_QT.grc
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/Designs/HAM Constructions/SDRX02A/SW/GRC/MLAB_ADC_Grabber.py
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/Designs/HAM Constructions/SDRX02A/SW/GRC/Player.grc
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/Designs/HAM Constructions/SDRX02A/SW/GRC/Player_balance.grc
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/Designs/HAM Constructions/SDRX02A/SW/GRC/Player_fm.grc
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/Designs/HAM Constructions/SDRX02A/SW/GRC/Records_player.py
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/Designs/HAM Constructions/SDRX02A/SW/GRC/top_block.py
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/Designs/HAM Constructions/SDRX02B/DOC/2014-05-12KakonaDiplThesisCTU-Prague.pdf
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/Designs/HAM Constructions/SDRX02B/SW/
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