Last modification
Rev 2937 – miho – 4216 d 6 h
Log message
Přidány obrázky do sekce XVC
Path Blame Diff Log
/Modules/CPLD_FPGA/XILINX_XVC/SchemaCyklu_Small.png Log
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/XVC_FT220X02A_Bot_Small.JPG Log
/Modules/CPLD_FPGA/XILINX_XVC/XVC_FT220X02A/XVC_FT220X02A_Top_Small.JPG Log