Last modification
Rev 1529 – kaklik – 5271 d 14 h
Log message
Vpodstate hotovy tistak, jeste bude pokus s otocenim konektoru.
Path Blame Diff Log
/Modules/Clock/CLKGEN01A/PCB/CLKGEN.pcb Blame Diff Log
/Modules/Clock/CLKGEN01A/SCH/CLKGEN.asc Blame Diff Log
/Modules/Clock/CLKGEN01A/SCH/CLKGEN.DSN Blame Diff Log