Last modification
Rev 0 – kaklik – 3205 d 9 h
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zapis moznych problemu k otestovani.

vylepseni layoutu differencnich spoju.
Path Blame Diff Log
/Modules/Translators/I2CDIFF01A/SCH_PCB/I2CDIFF01A.kicad_pcb Blame Diff Log
/Modules/Translators/I2CDIFF01A/SCH_PCB/I2CDIFF01A.kicad_pcb-bak Blame Diff Log
/Modules/Translators/I2CDIFF01A/TODO.txt Blame Diff Log