Last modification
Rev 0 – jacho – 3193 d 9 h
Log message
Vytvoreni noveho modulu RJ45V01A. Navrh PCB pripraven ke kontrole.
Path Blame Diff Log
/Modules/Universal/RJ45V01A/ Log
/Modules/Universal/RJ45V01A/CAM_PROFI/ Log
/Modules/Universal/RJ45V01A/DOC/ Log
/Modules/Universal/RJ45V01A/DOC/SRC/ Log
/Modules/Universal/RJ45V01A/DOC/SRC/RJ45V01A.doc Log
/Modules/Universal/RJ45V01A/pdf/ Log
/Modules/Universal/RJ45V01A/PrjInfo.txt Log
/Modules/Universal/RJ45V01A/RJ45V01A_Top_Small.jpg Log
/Modules/Universal/RJ45V01A/SCH_PCB/ Log
/Modules/Universal/RJ45V01A/SCH_PCB/RJ45V01A-cache.lib Log
/Modules/Universal/RJ45V01A/SCH_PCB/RJ45V01A.bak Log
/Modules/Universal/RJ45V01A/SCH_PCB/RJ45V01A.cmp Log
/Modules/Universal/RJ45V01A/SCH_PCB/RJ45V01A.csv Log
/Modules/Universal/RJ45V01A/SCH_PCB/RJ45V01A.kicad_pcb Log
/Modules/Universal/RJ45V01A/SCH_PCB/RJ45V01A.kicad_pcb-bak Log
/Modules/Universal/RJ45V01A/SCH_PCB/RJ45V01A.net Log
/Modules/Universal/RJ45V01A/SCH_PCB/RJ45V01A.pdf Log
/Modules/Universal/RJ45V01A/SCH_PCB/RJ45V01A.pro Log
/Modules/Universal/RJ45V01A/SCH_PCB/RJ45V01A.sch Log
/Modules/Universal/RJ45V01A/TODO.txt Log