Last modification
Rev 2133 – paro – 4826 d 16 h
Log message
Project import
Path Blame Diff Log
/Modules/Universal/UNIATMEGA8TQFP01A/ Log
/Modules/Universal/UNIATMEGA8TQFP01A/$savepcb.000 Log
/Modules/Universal/UNIATMEGA8TQFP01A/$savepcb.brd Log
/Modules/Universal/UNIATMEGA8TQFP01A/customized.py Log
/Modules/Universal/UNIATMEGA8TQFP01A/DIL8.lib Log
/Modules/Universal/UNIATMEGA8TQFP01A/DIL16.lib Log
/Modules/Universal/UNIATMEGA8TQFP01A/DIL20.lib Log
/Modules/Universal/UNIATMEGA8TQFP01A/pokus Log
/Modules/Universal/UNIATMEGA8TQFP01A/proto.mod Log
/Modules/Universal/UNIATMEGA8TQFP01A/replacer.py Log
/Modules/Universal/UNIATMEGA8TQFP01A/sed.out Log
/Modules/Universal/UNIATMEGA8TQFP01A/universal1 Log
/Modules/Universal/UNIATMEGA8TQFP01A/universal1-Back.ps Log
/Modules/Universal/UNIATMEGA8TQFP01A/universal1-cache.bak Log
/Modules/Universal/UNIATMEGA8TQFP01A/universal1-cache.lib Log
/Modules/Universal/UNIATMEGA8TQFP01A/universal1-Front.ps Log
/Modules/Universal/UNIATMEGA8TQFP01A/universal1.000 Log
/Modules/Universal/UNIATMEGA8TQFP01A/universal1.bak Log
/Modules/Universal/UNIATMEGA8TQFP01A/universal1.brd Log
/Modules/Universal/UNIATMEGA8TQFP01A/universal1.brd.backup1 Log
/Modules/Universal/UNIATMEGA8TQFP01A/universal1.brd.backup2 Log
/Modules/Universal/UNIATMEGA8TQFP01A/universal1.brd.backup3 Log
/Modules/Universal/UNIATMEGA8TQFP01A/universal1.brd.backup4 Log
/Modules/Universal/UNIATMEGA8TQFP01A/universal1.brd.backup5 Log
/Modules/Universal/UNIATMEGA8TQFP01A/universal1.cmp Log
/Modules/Universal/UNIATMEGA8TQFP01A/universal1.net Log
/Modules/Universal/UNIATMEGA8TQFP01A/universal1.pro Log
/Modules/Universal/UNIATMEGA8TQFP01A/universal1.sch Log