Rev Author Line No. Line
4918 kaklik 1 -- A bridge between the read side of a native FIFO and the Flexelerator's "enable" signal technique
2  
3  
4 library ieee;
5 use ieee.std_logic_1164.all;
6 use ieee.numeric_std.all;
7  
8  
9 entity fifo_to_enable is
10 port(
11  
12 -- Input from FIFO:
13 din : in std_logic_vector;
14 rden : out std_logic;
15 empty : in std_logic;
16  
17 -- Output with enable:
18 data : out std_logic_vector;
19 valid : out std_logic;
20 enable : in std_logic;
21  
22 clk : in std_logic;
23 reset : in std_logic
24  
25 );
26  
27 end entity;
28  
29 architecture behavioral of fifo_to_enable is
30  
31 signal s_rden : std_logic := '0';
32 signal s_rden_d : std_logic := '0';
33 signal s_valid : std_logic := '0';
34  
35 subtype t_data is std_logic_vector( din'range );
36 type t_data_buffer is array( 1 to 2 ) of t_data;
37 signal s_data_buffer : t_data_buffer := ( others => ( others => '0' ) );
38  
39 signal s_cntr : natural range 0 to 3;
40  
41 begin
42  
43  
44 s_rden <= '1' when empty = '0' and enable = '1' and reset = '0' and s_cntr < 3 else '0';
45 rden <= s_rden;
46 s_valid <= '1' when s_cntr > 0 and enable = '1' and reset = '0' else '0';
47 valid <= s_valid;
48 data <= s_data_buffer( 1 );
49  
50 -- Delayed rden:
51 delayed_rden : process( clk ) is
52 begin
53 if( rising_edge( clk ) ) then
54 s_rden_d <= s_rden;
55 end if;
56 end process;
57  
58 data_manipulation : process( clk ) is
59 begin
60 if( rising_edge( clk ) ) then
61  
62 if( s_valid = '1' ) then
63 s_data_buffer(1) <= s_data_buffer(2);
64 --s_data_buffer(2) <= s_data_buffer(3);
65 end if;
66  
67 if( reset = '1' ) then
68 s_cntr <= 0;
69 elsif( s_rden_d = '1' and s_valid = '0' ) then
70 s_cntr <= s_cntr + 1;
71 s_data_buffer( s_cntr + 1 ) <= din;
72 elsif( s_rden_d = '1' and s_valid = '1' ) then
73 s_data_buffer( s_cntr ) <= din;
74 elsif( s_rden_d = '0' and s_valid = '1' ) then
75 s_cntr <= s_cntr - 1;
76 end if;
77  
78 end if;
79 end process;
80  
81 end architecture;