Rev Author Line No. Line
4918 kaklik 1 -- file: selectio_iserdes_8bit_ddr_diffin.vhd
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47 ------------------------------------------------------------------------------
48 -- User entered comments
49 ------------------------------------------------------------------------------
50 -- None
51 ------------------------------------------------------------------------------
52 --
53 -- EDIT: Only the clock generator buffers here
54  
55  
56 library ieee;
57 use ieee.std_logic_1164.all;
58 use ieee.std_logic_unsigned.all;
59 use ieee.std_logic_arith.all;
60 use ieee.std_logic_misc.all;
61 use ieee.numeric_std.all;
62  
63 library unisim;
64 use unisim.vcomponents.all;
65  
66 entity iserdes_clock_generator is
67 port
68 (
69 -- Clock and reset signals
70 CLK_IN_P : in std_logic; -- Differential fast clock from IOB
71 CLK_IN_N : in std_logic;
72 CLK_OUT : out std_logic; -- Fast clock output (synchronous to data)
73 CLK_DIV_OUT : out std_logic; -- Slow clock output
74  
75 CLK_RESET : in std_logic); -- Reset signal for Clock circuit
76  
77 end iserdes_clock_generator;
78  
79 architecture sychro1 of iserdes_clock_generator is
80  
81 signal clk_in_int : std_logic;
82  
83 begin
84  
85 -- Create the clock logic
86 ibufds_clk_inst : IBUFGDS
87 generic map (
88 DIFF_TERM => TRUE,
89 IOSTANDARD => "LVDS_25" )
90 port map (
91 I => CLK_IN_P,
92 IB => CLK_IN_N,
93 O => clk_in_int);
94  
95 -- High Speed BUFIO clock buffer
96 bufio_inst : BUFIO
97 port map (
98 O => CLK_OUT,
99 I => clk_in_int);
100  
101 -- BUFR generates the slow clock
102 clkout_buf_inst : BUFR
103 generic map (
104 SIM_DEVICE => "VIRTEX6",
105 BUFR_DIVIDE => "4")
106 port map (
107 O => CLK_DIV_OUT,
108 CE => '1',
109 CLR => CLK_RESET,
110 I => clk_in_int );
111  
112 end sychro1;
113  
114  
115