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library

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Blame information for rev 3

Line No.	Rev	Author	Line
1	3	kaklik	`#nolist`
2			`//`
3			`// Komplete definition of all Special Feature Registers for CCS C compiler`
4			`//`
5			`// PIC16F873`
6			`// PIC16F874`
7			`// PIC16F876`
8			`// PIC16F877`
9			`//`
10			`// (c)miho 2005`
11			`//`
12			`// History:`
13			`//`
14			`// 1.00 First Version, not verified yet`
15
16
17			`// SFR Registers in Memory Bank 0`
18			`//`
19			`#byte INDF = 0x00`
20			`#byte TMR0 = 0x01`
21			`#byte PCL = 0x02`
22			`#byte STATUS = 0x03`
23			`#bit IRP = STATUS.7`
24			`#bit RP1 = STATUS.6`
25			`#bit RP0 = STATUS.5`
26			`#bit TO = STATUS.4`
27			`#bit PD = STATUS.3`
28			`#bit Z = STATUS.2`
29			`#bit DC = STATUS.1`
30			`#bit C = STATUS.0`
31			`#byte FSR = 0x04`
32			`#byte PORTA = 0x05`
33			`#byte PORTB = 0x06`
34			`#byte PORTC = 0x07`
35			`#byte PORTD = 0x08`
36			`#byte PORTE = 0x09`
37			`#byte PCLATH = 0x0A`
38			`#byte INTCON = 0x0B`
39			`#bit GIE = INTCON.7`
40			`#bit PEIE = INTCON.6`
41			`#bit T0IE = INTCON.5`
42			`#bit INTE = INTCON.4`
43			`#bit RBIE = INTCON.3`
44			`#bit T0IF = INTCON.2`
45			`#bit INTF = INTCON.1`
46			`#bit RBIF = INTCON.0`
47			`#byte PIR1 = 0x0C`
48			`#bit PSPIF = PIR1.7`
49			`#bit ADIF = PIR1.6`
50			`#bit RCIF = PIR1.5`
51			`#bit TXIF = PIR1.4`
52			`#bit SSPIF = PIR1.3`
53			`#bit CCP1IF = PIR1.2`
54			`#bit TMR2IF = PIR1.1`
55			`#bit TMR1IF = PIR1.0`
56			`#byte PIR2 = 0x0D`
57			`#bit EEIF = PIR2.4`
58			`#bit BCLIF = PIR2.3`
59			`#bit CCP2IF = PIR2.0`
60			`#byte TMR1L = 0x0E`
61			`#byte TMR1H = 0x0F`
62			`#byte T1CON = 0x10`
63			`#bit T1CKPS1 = T1CON.5`
64			`#bit T1CKPS0 = T1CON.4`
65			`#bit T1OSCEN = T1CON.3`
66			`#bit T1SYNC = T1CON.2`
67			`#bit TMR1CS = T1CON.1`
68			`#bit TMR1ON = T1CON.0`
69			`#byte TMR2 = 0x11`
70			`#byte T2CON = 0x12`
71			`#bit TOUTPS3 = T2CON.6`
72			`#bit TOUTPS2 = T2CON.5`
73			`#bit TOUTPS1 = T2CON.4`
74			`#bit TOUTPS0 = T2CON.3`
75			`#bit TMR2ON = T2CON.2`
76			`#bit T2CKPS1 = T2CON.1`
77			`#bit T2CKPS0 = T2CON.0`
78			`#byte SSPBUF = 0x13`
79			`#byte SSPCON = 0x14`
80			`#bit WCOL = SSPCON.7`
81			`#bit SSPOV = SSPCON.6`
82			`#bit SSPEN = SSPCON.5`
83			`#bit CKP = SSPCON.4`
84			`#bit SSPM3 = SSPCON.3`
85			`#bit SSPM2 = SSPCON.2`
86			`#bit SSPM1 = SSPCON.1`
87			`#bit SSPM0 = SSPCON.0`
88			`#byte CCPR1L = 0x15`
89			`#byte CCPR1H = 0x16`
90			`#byte CCP1CON = 0x17`
91			`#bit CCP1X = CCP1CON.5`
92			`#bit CCP1Y = CCP1CON.4`
93			`#bit CCP1M3 = CCP1CON.3`
94			`#bit CCP1M2 = CCP1CON.2`
95			`#bit CCP1M1 = CCP1CON.1`
96			`#bit CCP1M0 = CCP1CON.0`
97			`#byte RCSTA = 0x18`
98			`#bit SPEN = RCSTA.7`
99			`#bit RX9 = RCSTA.6`
100			`#bit SREN = RCSTA.5`
101			`#bit CREN = RCSTA.4`
102			`#bit ADDEN = RCSTA.3`
103			`#bit FERR = RCSTA.2`
104			`#bit OERR = RCSTA.1`
105			`#bit RX9D = RCSTA.0`
106			`#byte TXREG = 0x19`
107			`#byte RCREG = 0x1A`
108			`#byte CCPR2L = 0x1B`
109			`#byte CCPR2H = 0x1C`
110			`#byte CCP2CON = 0x1D`
111			`#bit CCP2X = CCP2CON.5`
112			`#bit CCP2Y = CCP2CON.4`
113			`#bit CCP2M3 = CCP2CON.3`
114			`#bit CCP2M2 = CCP2CON.2`
115			`#bit CCP2M1 = CCP2CON.1`
116			`#bit CCP2M0 = CCP2CON.0`
117			`#byte ADRESH = 0x1E`
118			`#byte ADCON0 = 0x1F`
119			`#bit ADCS1 = ADCON0.7`
120			`#bit ADCS0 = ADCON0.6`
121			`#bit CHS2 = ADCON0.5`
122			`#bit CHS1 = ADCON0.4`
123			`#bit CHS0 = ADCON0.3`
124			`#bit GO = ADCON0.2`
125			`#bit ADON = ADCON0.0`
126
127
128			`// SFR Registers in Memory Bank 1`
129			`//`
130			`#byte INDF_1 = 0x80 // miror`
131			`#byte OPTION_REG = 0x81`
132			`#bit RBPU = OPTION_REG.7`
133			`#bit INTEDG = OPTION_REG.6`
134			`#bit T0CS = OPTION_REG.5`
135			`#bit T0SE = OPTION_REG.4`
136			`#bit PSA = OPTION_REG.3`
137			`#bit PS2 = OPTION_REG.2`
138			`#bit PS1 = OPTION_REG.1`
139			`#bit PS0 = OPTION_REG.0`
140			`#byte PCL_1 = 0x82 // mirror`
141			`#byte STATUS_1 = 0x83 // mirror`
142			`#bit IRP_1 = STATUS_1.7`
143			`#bit RP1_1 = STATUS_1.6`
144			`#bit RP0_1 = STATUS_1.5`
145			`#bit TO_1 = STATUS_1.4`
146			`#bit PD_1 = STATUS_1.3`
147			`#bit Z_1 = STATUS_1.2`
148			`#bit DC_1 = STATUS_1.1`
149			`#bit C_1 = STATUS_1.0`
150			`#byte FSR_1 = 0x84 // mirror`
151			`#byte TRISA = 0x85`
152			`#byte TRISB = 0x86`
153			`#byte TRISC = 0x87`
154			`#byte TRISD = 0x88`
155			`#byte TRISE = 0x89`
156			`#bit IBF = TRISE.7`
157			`#bit OBF = TRISE.6`
158			`#bit IBOV = TRISE.5`
159			`#bit PSPMODE = TRISE.4`
160			`#byte PCLATH_1 = 0x8A // mirror`
161			`#byte INTCON_1 = 0x8B // mirror`
162			`#bit GIE_1 = INTCON_1.7`
163			`#bit PEIE_1 = INTCON_1.6`
164			`#bit TMR0IE_1 = INTCON_1.5`
165			`#bit INTE_1 = INTCON_1.4`
166			`#bit RBIE_1 = INTCON_1.3`
167			`#bit T0IF_1 = INTCON_1.2`
168			`#bit INTF_1 = INTCON_1.1`
169			`#bit RBIF_1 = INTCON_1.0`
170			`#byte PIE1 = 0x8C`
171			`#bit PSPIE = PIE1.7`
172			`#bit ADIE = PIE1.6`
173			`#bit RCIE = PIE1.5`
174			`#bit TXIE = PIE1.4`
175			`#bit SSPIE = PIE1.3`
176			`#bit CCP1IE = PIE1.2`
177			`#bit TMR2IE = PIE1.1`
178			`#bit TMR1IE = PIE1.0`
179			`#byte PIE2 = 0x8D`
180			`#bit EEIE = PIE2.4`
181			`#bit BCLIE = PIE2.3`
182			`#bit CCP2IE = PIE2.0`
183			`#byte PCON = 0x8E`
184			`#bit POR = PCON.1`
185			`#bit BOR = PCON.0`
186			`#byte SSPCON2 = 0x91`
187			`#bit GCEN = SSPCON2.7`
188			`#bit ACKSTAT = SSPCON2.6`
189			`#bit ACKDT = SSPCON2.5`
190			`#bit ACKEN = SSPCON2.4`
191			`#bit RCEN = SSPCON2.3`
192			`#bit PEN = SSPCON2.2`
193			`#bit RSEN = SSPCON2.1`
194			`#bit SEN = SSPCON2.0`
195			`#byte PR2 = 0x92`
196			`#byte SSPADD = 0x93`
197			`#byte SSPSTAT = 0x94`
198			`#bit SMP = SSPSTAT.7`
199			`#bit CKE = SSPSTAT.6`
200			`#bit DA = SSPSTAT.5`
201			`#bit P = SSPSTAT.4`
202			`#bit S = SSPSTAT.3`
203			`#bit RW = SSPSTAT.2`
204			`#bit UA = SSPSTAT.1`
205			`#bit BF = SSPSTAT.0`
206			`#byte TXSTA = 0x98`
207			`#bit CSRC = TXSTA.7`
208			`#bit TX9 = TXSTA.6`
209			`#bit TXEN = TXSTA.5`
210			`#bit SYNC = TXSTA.4`
211			`#bit BRGH = TXSTA.2`
212			`#bit TRMT = TXSTA.1`
213			`#bit TX9D = TXSTA.0`
214			`#byte SPBRG = 0x99`
215			`#byte ADRESL = 0x9E`
216			`#byte ADCON1 = 0x9F`
217			`#bit ADFM = ADCON1.7`
218			`#bit PCFG3 = ADCON1.3`
219			`#bit PCFG2 = ADCON1.2`
220			`#bit PCFG1 = ADCON1.1`
221			`#bit PCFG0 = ADCON1.0`
222
223
224			`// SFR Registers in Memory Bank 2`
225			`//`
226			`#byte INDF_2 = 0x100 // mirror`
227			`#byte TMR0_2 = 0x101 // mirror`
228			`#byte PCL_2 = 0x102 // mirror`
229			`#byte STATUS_2 = 0x103 // mirror`
230			`#bit IRP_2 = STATUS_2.7`
231			`#bit RP1_2 = STATUS_2.6`
232			`#bit RP0_2 = STATUS_2.5`
233			`#bit TO_2 = STATUS_2.4`
234			`#bit PD_2 = STATUS_2.3`
235			`#bit Z_2 = STATUS_2.2`
236			`#bit DC_2 = STATUS_2.1`
237			`#bit C_2 = STATUS_2.0`
238			`#byte FSR_2 = 0x104 // mirror`
239			`#byte PORTB_2 = 0x106 // mirror`
240			`#byte PCLATH_2 = 0x10A // mirror`
241			`#byte INTCON_2 = 0x10B // mirror`
242			`#bit GIE_2 = INTCON_2.7`
243			`#bit PEIE_2 = INTCON_2.6`
244			`#bit T0IE_2 = INTCON_2.5`
245			`#bit INTE_2 = INTCON_2.4`
246			`#bit RBIE_2 = INTCON_2.3`
247			`#bit T0IF_2 = INTCON_2.2`
248			`#bit INTF_2 = INTCON_2.1`
249			`#bit RBIF_2 = INTCON_2.0`
250			`#byte EEDATA = 0x10C`
251			`#byte EEADR = 0x10D`
252			`#byte EEDATH = 0x10E`
253			`#byte EEADRH = 0x10F`
254
255
256			`// SFR Registers in Memory Bank 3`
257			`//`
258			`#byte INDF_3 = 0x180 // mirror`
259			`#byte OPTION_REG_3 = 0x181 // mirror`
260			`#bit RBPU_3 = OPTION_REG_3.7`
261			`#bit INTEDG_3 = OPTION_REG_3.6`
262			`#bit T0CS_3 = OPTION_REG_3.5`
263			`#bit T0SE_3 = OPTION_REG_3.4`
264			`#bit PSA_3 = OPTION_REG_3.3`
265			`#bit PS2_3 = OPTION_REG_3.2`
266			`#bit PS1_3 = OPTION_REG_3.1`
267			`#bit PS0_3 = OPTION_REG_3.0`
268			`#byte PCL_3 = 0x182 // mirror`
269			`#byte STATUS_3 = 0x183 // mirror`
270			`#bit IRP_3 = STATUS_3.7`
271			`#bit RP1_3 = STATUS_3.6`
272			`#bit RP0_3 = STATUS_3.5`
273			`#bit TO_3 = STATUS_3.4`
274			`#bit PD_3 = STATUS_3.3`
275			`#bit Z_3 = STATUS_3.2`
276			`#bit DC_3 = STATUS_3.1`
277			`#bit C_3 = STATUS_3.0`
278			`#byte FSR_3 = 0x184 // mirror`
279			`#byte TRISB_3 = 0x186 // mirror`
280			`#byte PLATH_3 = 0x18A // mirror`
281			`#byte INTCON_3 = 0x18B // mirror`
282			`#bit GIE_3 = INTCON_3.7`
283			`#bit PEIE_3 = INTCON_3.6`
284			`#bit T0IE_3 = INTCON_3.5`
285			`#bit INTE_3 = INTCON_3.4`
286			`#bit RBIE_3 = INTCON_3.3`
287			`#bit T0IF_3 = INTCON_3.2`
288			`#bit INTF_3 = INTCON_3.1`
289			`#bit RBIF_3 = INTCON_3.0`
290			`#byte EECON1 = 0x18C`
291			`#bit EEPGD = EECON1.7`
292			`#bit WRERR = EECON1.3`
293			`#bit WREN = EECON1.2`
294			`#bit WR = EECON1.1`
295			`#bit RD = EECON1.0`
296			`#byte EECON2 = 0x18D`
297
298
299			`#list`