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library

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Blame information for rev 3

Line No. Rev Author Line
1 3 kaklik #nolist
2 //
3 // Komplete definition of all Special Feature Registers for CCS C compiler
4 //
5 // PIC16F87
6 // PIC16F88
7 //
8 // (c)miho 2005
9 //
10 // History:
11 //
12 // 1.00 First Version, not verified yet
13  
14  
15 // SFR Registers in Memory Bank 0
16 //
17 #byte INDF = 0x00
18 #byte TMR0 = 0x01
19 #byte PCL = 0x02
20 #byte STATUS = 0x03
21 #bit IRP = STATUS.7
22 #bit RP1 = STATUS.6
23 #bit RP0 = STATUS.5
24 #bit TO = STATUS.4
25 #bit PD = STATUS.3
26 #bit Z = STATUS.2
27 #bit DC = STATUS.1
28 #bit C = STATUS.0
29 #byte FSR = 0x04
30 #byte PORTA = 0x05
31 #byte PORTB = 0x06
32 #byte PCLATH = 0x0A
33 #byte INTCON = 0x0B
34 #bit GIE = INTCON.7
35 #bit PEIE = INTCON.6
36 #bit TMR0IE = INTCON.5
37 #bit INT0IE = INTCON.4
38 #bit RBIE = INTCON.3
39 #bit TMR0IF = INTCON.2
40 #bit INT0IF = INTCON.1
41 #bit RBIF = INTCON.0
42 #byte PIR1 = 0x0C
43 #bit ADIF = PIR1.6
44 #bit RCIF = PIR1.5
45 #bit TXIF = PIR1.4
46 #bit SSPIF = PIR1.3
47 #bit CCP1IF = PIR1.2
48 #bit TMR2IF = PIR1.1
49 #bit TMR1IF = PIR1.0
50 #byte PIR2 = 0x0D
51 #bit OSFIF = PIR2.7
52 #bit CMIF = PIR2.6
53 #bit EEIF = PIR2.4
54 #byte TMR1L = 0x0E
55 #byte TMR1H = 0x0F
56 #byte T1CON = 0x10
57 #bit T1RUN = T1CON.6
58 #bit T1CKPS1 = T1CON.5
59 #bit T1CKPS0 = T1CON.4
60 #bit T1OSCEN = T1CON.3
61 #bit T1SYNC = T1CON.2
62 #bit TMR1CS = T1CON.1
63 #bit TMR1ON = T1CON.0
64 #byte TMR2 = 0x11
65 #byte T2CON = 0x12
66 #bit TOUTPS3 = T2CON.6
67 #bit TOUTPS2 = T2CON.5
68 #bit TOUTPS1 = T2CON.4
69 #bit TOUTPS0 = T2CON.3
70 #bit TMR2ON = T2CON.2
71 #bit T2CKPS1 = T2CON.1
72 #bit T2CKPS0 = T2CON.0
73 #byte SSPBUF = 0x13
74 #byte SSPCON1 = 0x14
75 #bit WCOL = SSPCON1.7
76 #bit SSPOV = SSPCON1.6
77 #bit SSPEN = SSPCON1.5
78 #bit CKP = SSPCON1.4
79 #bit SSPM3 = SSPCON1.3
80 #bit SSPM2 = SSPCON1.2
81 #bit SSPM1 = SSPCON1.1
82 #bit SSPM0 = SSPCON1.0
83 #byte CCPR1L = 0x15
84 #byte CCPR1H = 0x16
85 #byte CCP1CON = 0x17
86 #bit CCP1X = CCP1CON.5
87 #bit CCP1Y = CCP1CON.4
88 #bit CCP1M3 = CCP1CON.3
89 #bit CCP1M2 = CCP1CON.2
90 #bit CCP1M1 = CCP1CON.1
91 #bit CCP1M0 = CCP1CON.0
92 #byte RCSTA = 0x18
93 #bit SPEN = RCSTA.7
94 #bit RX9 = RCSTA.6
95 #bit SREN = RCSTA.5
96 #bit CREN = RCSTA.4
97 #bit ADDEN = RCSTA.3
98 #bit FERR = RCSTA.2
99 #bit OERR = RCSTA.1
100 #bit RX9D = RCSTA.0
101 #byte TXREG = 0x19
102 #byte RCREG = 0x1A
103 #byte ADRESH = 0x1E // F88 only
104 #byte ADCON0 = 0x1F // F88 only
105 #bit ADCS1 = ADCON0.7
106 #bit ADCS0 = ADCON0.6
107 #bit CHS2 = ADCON0.5
108 #bit CHS1 = ADCON0.4
109 #bit CHS0 = ADCON0.3
110 #bit GO = ADCON0.2
111 #bit ADON = ADCON0.0
112  
113  
114 // SFR Registers in Memory Bank 1
115 //
116 #byte INDF_1 = 0x80 // miror
117 #byte OPTION = 0x81
118 #bit RBPU = OPTION.7
119 #bit INTEDG = OPTION.6
120 #bit T0CS = OPTION.5
121 #bit T0SE = OPTION.4
122 #bit PSA = OPTION.3
123 #bit PS2 = OPTION.2
124 #bit PS1 = OPTION.1
125 #bit PS0 = OPTION.0
126 #byte PCL = 0x82
127 #byte STATUS_1 = 0x83 // mirror
128 #bit IRP_1 = STATUS_1.7
129 #bit RP1_1 = STATUS_1.6
130 #bit RP0_1 = STATUS_1.5
131 #bit TO_1 = STATUS_1.4
132 #bit PD_1 = STATUS_1.3
133 #bit Z_1 = STATUS_1.2
134 #bit DC_1 = STATUS_1.1
135 #bit C_1 = STATUS_1.0
136 #byte FSR = 0x84
137 #byte TRISA = 0x85
138 #byte TRISB = 0x86
139 #byte PCLATH_1 = 0x8A // mirror
140 #byte INTCON_1 = 0x8B // mirror
141 #bit GIE_1 = INTCON_1.7
142 #bit PEIE_1 = INTCON_1.6
143 #bit TMR0IE_1 = INTCON_1.5
144 #bit INT0IE_1 = INTCON_1.4
145 #bit RBIE_1 = INTCON_1.3
146 #bit TMR0IF_1 = INTCON_1.2
147 #bit INT0IF_1 = INTCON_1.1
148 #bit RBIF_1 = INTCON_1.0
149 #byte PIE1 = 0x8C
150 #bit ADIE = PIE1.6
151 #bit RCIE = PIE1.5
152 #bit TXIE = PIE1.4
153 #bit SSPIE = PIE1.3
154 #bit CCP1IE = PIE1.2
155 #bit TMR2IE = PIE1.1
156 #bit TMR1IE = PIE1.0
157 #byte PIE2 = 0x8D
158 #bit OSFIE = PIE2.7
159 #bit CMIE = PIE2.6
160 #bit EEIE = PIE2.4
161 #byte PCON = 0x8E
162 #bit POR = PCON.1
163 #bit BOR = PCON.0
164 #byte OSCCON = 0x8F
165 #bit IRCF2 = OSCCON.6
166 #bit IRCF1 = OSCCON.5
167 #bit IRCF0 = OSCCON.4
168 #bit OSTS = OSCCON.3
169 #bit IOFS = OSCCON.2
170 #bit SCS1 = OSCCON.1
171 #bit SCS0 = OSCCON.0
172 #byte OSCTUNE = 0x90
173 #bit TUN5 = OSCTUNE.5
174 #bit TUN4 = OSCTUNE.4
175 #bit TUN3 = OSCTUNE.3
176 #bit TUN2 = OSCTUNE.2
177 #bit TUN1 = OSCTUNE.1
178 #bit TUN0 = OSCTUNE.0
179 #byte PR2 = 0x92
180 #byte SSPADD = 0x93
181 #byte SSPSTAT = 0x94
182 #bit SMP = SSPSTAT.7
183 #bit CKE = SSPSTAT.6
184 #bit DA = SSPSTAT.5
185 #bit P = SSPSTAT.4
186 #bit S = SSPSTAT.3
187 #bit RW = SSPSTAT.2
188 #bit UA = SSPSTAT.1
189 #bit BF = SSPSTAT.0
190 #byte TXSTA = 0x98
191 #bit CSRC = TXSTA.7
192 #bit TX9 = TXSTA.6
193 #bit TXEN = TXSTA.5
194 #bit SYNC = TXSTA.4
195 #bit BRGH = TXSTA.2
196 #bit TRMT = TXSTA.1
197 #bit TX9D = TXSTA.0
198 #byte SPBRG = 0x99
199 #byte ANSEL = 0x9B // F88 only
200 #bit ANS6 = ANSEL.6
201 #bit ANS5 = ANSEL.5
202 #bit ANS4 = ANSEL.4
203 #bit ANS3 = ANSEL.3
204 #bit ANS2 = ANSEL.2
205 #bit ANS1 = ANSEL.1
206 #bit ANS0 = ANSEL.0
207 #byte CMCON = 0x9C
208 #bit C2OUT = CMCON.7
209 #bit C1OUT = CMCON.6
210 #bit C2INV = CMCON.5
211 #bit C1INV = CMCON.4
212 #bit CIS = CMCON.3
213 #bit CM2 = CMCON.2
214 #bit CM1 = CMCON.1
215 #bit CM0 = CMCON.0
216 #byte CVRCON = 0x9D
217 #bit CVREN = CVRCON.7
218 #bit CVROE = CVRCON.6
219 #bit CVRR = CVRCON.5
220 #bit CVR3 = CVRCON.3
221 #bit CVR2 = CVRCON.2
222 #bit CVR1 = CVRCON.1
223 #bit CVR0 = CVRCON.0
224 #byte ADRESL = 0x9E // F88 only
225 #byte ADCON1 = 0x9F // F88 only
226 #bit ADFM = ADCON1.7
227 #bit ADCS2 = ADCON1.6
228 #bit VCFG1 = ADCON1.5
229 #bit VCFG0 = ADCON1.4
230  
231  
232 // SFR Registers in Memory Bank 2
233 //
234 #byte INDF_2 = 0x100 // mirror
235 #byte TMR0_2 = 0x101 // mirror
236 #byte PCL_2 = 0x102 // mirror
237 #byte STATUS_2 = 0x103 // mirror
238 #bit IRP_2 = STATUS_2.7
239 #bit RP1_2 = STATUS_2.6
240 #bit RP0_2 = STATUS_2.5
241 #bit TO_2 = STATUS_2.4
242 #bit PD_2 = STATUS_2.3
243 #bit Z_2 = STATUS_2.2
244 #bit DC_2 = STATUS_2.1
245 #bit C_2 = STATUS_2.0
246 #byte FSR_2 = 0x104 // mirror
247 #byte WDTCON = 0x105
248 #bit WDTPS3 = WDTCON.4
249 #bit WDTPS2 = WDTCON.3
250 #bit WDTPS1 = WDTCON.2
251 #bit WDTPS0 = WDTCON.1
252 #bit SWDTEN = WDTCON.0
253 #byte PORTB_2 = 0x106 // mirror
254 #byte PCLATH_2 = 0x10A // mirror
255 #byte INTCON_2 = 0x10B // mirror
256 #bit GIE_2 = INTCON_2.7
257 #bit PEIE_2 = INTCON_2.6
258 #bit TMR0IE_2 = INTCON_2.5
259 #bit INT0IE_2 = INTCON_2.4
260 #bit RBIE_2 = INTCON_2.3
261 #bit TMR0IF_2 = INTCON_2.2
262 #bit INT0IF_2 = INTCON_2.1
263 #bit RBIF_2 = INTCON_2.0
264 #byte EEDATA = 0x10C
265 #byte EEADR = 0x10D
266 #byte EEDATH = 0x10E
267 #byte EEADRH = 0x10F
268  
269  
270 // SFR Registers in Memory Bank 3
271 //
272 #byte INDF_3 = 0x180 // mirror
273 #byte OPTION_3 = 0x181 // mirror
274 #bit RBPU_3 = OPTION_3.7
275 #bit INTEDG_3 = OPTION_3.6
276 #bit T0CS_3 = OPTION_3.5
277 #bit T0SE_3 = OPTION_3.4
278 #bit PSA_3 = OPTION_3.3
279 #bit PS2_3 = OPTION_3.2
280 #bit PS1_3 = OPTION_3.1
281 #bit PS0_3 = OPTION_3.0
282 #byte PCL_3 = 0x182 // mirror
283 #byte STATUS_3 = 0x183 // mirror
284 #bit IRP_3 = STATUS_3.7
285 #bit RP1_3 = STATUS_3.6
286 #bit RP0_3 = STATUS_3.5
287 #bit TO_3 = STATUS_3.4
288 #bit PD_3 = STATUS_3.3
289 #bit Z_3 = STATUS_3.2
290 #bit DC_3 = STATUS_3.1
291 #bit C_3 = STATUS_3.0
292 #byte FSR_3 = 0x184 // mirror
293 #byte TRISB_3 = 0x186 // mirror
294 #byte PLATH_3 = 0x18A // mirror
295 #byte INTCON_3 = 0x18B // mirror
296 #bit GIE_3 = INTCON_3.7
297 #bit PEIE_3 = INTCON_3.6
298 #bit TMR0IE_3 = INTCON_3.5
299 #bit INT0IE_3 = INTCON_3.4
300 #bit RBIE_3 = INTCON_3.3
301 #bit TMR0IF_3 = INTCON_3.2
302 #bit INT0IF_3 = INTCON_3.1
303 #bit RBIF_3 = INTCON_3.0
304 #byte EECON1 = 0x18C
305 #bit EEPGD = EECON1.7
306 #bit FREE = EECON1.4
307 #bit WRERR = EECON1.3
308 #bit WREN = EECON1.2
309 #bit WR = EECON1.1
310 #bit RD = EECON1.0
311 #byte EECON2 = 0x18D
312  
313  
314 #list
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