| Line No. | Rev | Author | Line |
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| 1 | 32 | kaklik | /********************************************************************* |
| 2 | * |
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| 3 | * ENC424J600/624J600 Registers and Bits |
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| 4 | * |
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| 5 | ********************************************************************* |
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| 6 | * FileName: ENCX24J600.h |
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| 7 | * Dependencies: None |
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| 8 | * Processor: PIC18, PIC24F, PIC24H, dsPIC30F, dsPIC33F, PIC32 |
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| 9 | * Compiler: Microchip C32 v1.05 or higher |
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| 10 | * Microchip C30 v3.12 or higher |
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| 11 | * Microchip C18 v3.30 or higher |
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| 12 | * HI-TECH PICC-18 PRO 9.63PL2 or higher |
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| 13 | * Company: Microchip Technology, Inc. |
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| 14 | * |
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| 15 | * Software License Agreement |
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| 16 | * |
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| 17 | * Copyright (C) 2002-2009 Microchip Technology Inc. All rights |
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| 18 | * reserved. |
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| 19 | * |
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| 20 | * Microchip licenses to you the right to use, modify, copy, and |
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| 21 | * distribute: |
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| 22 | * (i) the Software when embedded on a Microchip microcontroller or |
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| 23 | * digital signal controller product ("Device") which is |
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| 24 | * integrated into Licensee's product; or |
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| 25 | * (ii) ONLY the Software driver source files ENC28J60.c, ENC28J60.h, |
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| 26 | * ENCX24J600.c and ENCX24J600.h ported to a non-Microchip device |
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| 27 | * used in conjunction with a Microchip ethernet controller for |
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| 28 | * the sole purpose of interfacing with the ethernet controller. |
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| 29 | * |
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| 30 | * You should refer to the license agreement accompanying this |
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| 31 | * Software for additional information regarding your rights and |
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| 32 | * obligations. |
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| 33 | * |
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| 34 | * THE SOFTWARE AND DOCUMENTATION ARE PROVIDED "AS IS" WITHOUT |
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| 35 | * WARRANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED, INCLUDING WITHOUT |
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| 36 | * LIMITATION, ANY WARRANTY OF MERCHANTABILITY, FITNESS FOR A |
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| 37 | * PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT SHALL |
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| 38 | * MICROCHIP BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR |
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| 39 | * CONSEQUENTIAL DAMAGES, LOST PROFITS OR LOST DATA, COST OF |
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| 40 | * PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS |
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| 41 | * BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE |
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| 42 | * THEREOF), ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER |
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| 43 | * SIMILAR COSTS, WHETHER ASSERTED ON THE BASIS OF CONTRACT, TORT |
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| 44 | * (INCLUDING NEGLIGENCE), BREACH OF WARRANTY, OR OTHERWISE. |
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| 45 | * |
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| 46 | * |
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| 47 | * Author Date Comment |
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| 48 | *~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 49 | * Howard Schlunder 11/30/07 Original |
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| 50 | ********************************************************************/ |
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| 51 | |||
| 52 | #ifndef __ENCX24J600_H |
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| 53 | #define __ENCX24J600_H |
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| 54 | #include "GenericTypeDefs.h" |
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| 55 | #include "HardwareProfile.h" |
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| 56 | |||
| 57 | // Define macro for 8-bit PSP SFR address translation to SPI addresses |
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| 58 | #if (ENC100_INTERFACE_MODE == 0) // SPI |
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| 59 | #define ENC100_TRANSLATE_TO_PIN_ADDR(a) ((a) & 0x00FFu) |
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| 60 | #elif !defined(ENC100_PSP_USE_INDIRECT_RAM_ADDRESSING) || (ENC100_INTERFACE_MODE == 9) || (ENC100_INTERFACE_MODE == 10) // Direct addressing modes and 16-bit multiplexed modes require no address translation (all 14 or 15 address bits must be connected) |
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| 61 | #undef ENC100_TRANSLATE_TO_PIN_ADDR |
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| 62 | #define ENC100_TRANSLATE_TO_PIN_ADDR(a) (a) |
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| 63 | #elif !defined(ENC100_TRANSLATE_TO_PIN_ADDR) |
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| 64 | #error HardwareProfile.h must define ENC100_TRANSLATE_TO_PIN_ADDR macro when using indirect PSP addressing |
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| 65 | #endif |
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| 66 | |||
| 67 | #define ENC100_RAM_SIZE (24*1024u) |
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| 68 | |||
| 69 | // Crypto memory addresses. These are accessible by the DMA only and therefore |
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| 70 | // have the same addresses no matter what MCU interface is being used (SPI, |
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| 71 | // 8-bit PSP, or 16-bit PSP) |
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| 72 | #define ENC100_MODEX_Y (0x7880u) |
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| 73 | #define ENC100_MODEX_E (0x7800u) |
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| 74 | #define ENC100_MODEX_X (0x7880u) |
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| 75 | #define ENC100_MODEX_M (0x7900u) |
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| 76 | #define ENC100_HASH_DATA_IN (0x7A00u) |
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| 77 | #define ENC100_HASH_IV_IN (0x7A40u) |
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| 78 | #define ENC100_HASH_LEN_IN (0x7A54u) |
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| 79 | #define ENC100_HASH_DIGEST_OUT (0x7A70u) |
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| 80 | #define ENC100_HASH_LEN_OUT (0x7A84u) |
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| 81 | #define ENC100_HASH_BASE_ADDR (0x7A00u) |
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| 82 | #define ENC100_AES_KEY (0x7C00u) |
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| 83 | #define ENC100_AES_TEXTA (0x7C20u) |
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| 84 | #define ENC100_AES_TEXTB (0x7C30u) |
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| 85 | #define ENC100_AES_XOROUT (0x7C40u) |
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| 86 | |||
| 87 | |||
| 88 | // Receive Status Vector bit fields |
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| 89 | typedef union __attribute__((aligned(2), packed)) { |
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| 90 | BYTE v[6]; |
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| 91 | struct { |
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| 92 | WORD ByteCount; |
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| 93 | |||
| 94 | unsigned char PreviouslyIgnored:1; |
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| 95 | unsigned char RXDCPreviouslySeen:1; |
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| 96 | unsigned char CarrierPreviouslySeen:1; |
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| 97 | unsigned char CodeViolation:1; |
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| 98 | unsigned char CRCError:1; |
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| 99 | unsigned char LengthCheckError:1; |
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| 100 | unsigned char LengthOutOfRange:1; |
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| 101 | unsigned char ReceiveOk:1; |
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| 102 | unsigned char Multicast:1; |
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| 103 | unsigned char Broadcast:1; |
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| 104 | unsigned char DribbleNibble:1; |
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| 105 | unsigned char ControlFrame:1; |
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| 106 | unsigned char PauseControlFrame:1; |
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| 107 | unsigned char UnsupportedOpcode:1; |
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| 108 | unsigned char VLANType:1; |
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| 109 | unsigned char RuntMatch:1; |
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| 110 | |||
| 111 | unsigned char filler:1; |
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| 112 | unsigned char HashMatch:1; |
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| 113 | unsigned char MagicPacketMatch:1; |
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| 114 | unsigned char PatternMatch:1; |
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| 115 | unsigned char UnicastMatch:1; |
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| 116 | unsigned char BroadcastMatch:1; |
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| 117 | unsigned char MulticastMatch:1; |
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| 118 | unsigned char ZeroH:1; |
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| 119 | unsigned char Zero:8; |
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| 120 | } bits; |
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| 121 | } RXSTATUS; |
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| 122 | |||
| 123 | |||
| 124 | #if (ENC100_INTERFACE_MODE >= 1) // Parallel mode |
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| 125 | #define SET_OFFSET ENC100_TRANSLATE_TO_PIN_ADDR(0x0100u) |
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| 126 | #define CLR_OFFSET ENC100_TRANSLATE_TO_PIN_ADDR(0x0180u) |
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| 127 | |||
| 128 | #else // SPI mode |
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| 129 | //////////////////////////////////////////////////// |
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| 130 | // ENC424J600/624J600 SPI Opcodes // |
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| 131 | //////////////////////////////////////////////////// |
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| 132 | #define RCR (0x0u<<5)// Read Control Register |
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| 133 | #define WCR (0x2u<<5)// Write Control Register |
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| 134 | #define RCRU (0x20u) // Read Control Register Unbanked |
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| 135 | #define WCRU (0x22u) // Write Control Register Unbanked |
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| 136 | #define BFS (0x4u<<5)// Bit Field Set |
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| 137 | #define BFSU (0x24u) // Bit Field Set Unbanked |
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| 138 | #define BFC (0x5u<<5)// Bit Field Clear |
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| 139 | #define BFCU (0x26u) // Bit Field Clear Unbanked |
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| 140 | #define RBMGP (0x28u) // Read Buffer Memory General Purpose |
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| 141 | #define WBMGP (0x2Au) // Write Buffer Memory General Purpose |
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| 142 | #define RBMRX (0x2Cu) // Read Buffer Memory RX |
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| 143 | #define WBMRX (0x2Eu) // Write Buffer Memory RX |
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| 144 | #define RBMUDA (0x30u) // Read Buffer Memory User Defined Area |
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| 145 | #define WBMUDA (0x32u) // Write Buffer Memory User Defined Area |
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| 146 | #define WGPRDPT (0x60u) // Write General Purpose Read Pointer |
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| 147 | #define RGPRDPT (0x62u) // Read General Purpose Read Pointer |
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| 148 | #define WRXRDPT (0x64u) // Write RX Read Pointer |
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| 149 | #define RRXRDPT (0x66u) // Read RX Read Pointer |
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| 150 | #define WUDARDPT (0x68u) // Write User Defined Area Read Pointer |
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| 151 | #define RUDARDPT (0x6Au) // Read User Defined Area Read Pointer |
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| 152 | #define WGPWRPT (0x6Cu) // Write General Purpose Write Pointer |
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| 153 | #define RGPWRPT (0x6Eu) // Read General Purpose Write Pointer |
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| 154 | #define WRXWRPT (0x70u) // Write RX Write Pointer |
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| 155 | #define RRXWRPT (0x72u) // Read RX Write Pointer |
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| 156 | #define WUDAWRPT (0x74u) // Write User Defined Area Write Pointer |
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| 157 | #define RUDAWRPT (0x76u) // Read User Defined Area Write Pointer |
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| 158 | #define B0SEL (0xC0u) // Bank 0 Select |
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| 159 | #define B1SEL (0xC2u) // Bank 1 Select |
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| 160 | #define B2SEL (0xC4u) // Bank 2 Select |
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| 161 | #define B3SEL (0xC6u) // Bank 3 Select |
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| 162 | #define RBSEL (0xC8u) // Read Bank Select |
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| 163 | #define SETETHRST (0xCAu) // Set ETHRST bit (perform system reset) |
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| 164 | #define FCDIS (0xE0u) // Flow Control Disable |
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| 165 | #define FCSINGLE (0xE2u) // Flow Control Single |
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| 166 | #define FCMULTIPLE (0xE4u) // Flow Control Multiple |
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| 167 | #define FCCLEAR (0xE6u) // Flow Control Clear |
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| 168 | #define SETPKTDEC (0xCCu) // Set PKTDEC bit (decrement RX packet pending counter) |
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| 169 | #define DMASTOP (0xD0u) // DMA Stop |
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| 170 | #define DMACKSUM (0xD8u) // DMA Start Checksum |
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| 171 | #define DMACKSUMS (0xDAu) // DMA Start Checksum with Seed |
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| 172 | #define DMACOPY (0xDCu) // DMA Start Copy |
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| 173 | #define DMACOPYS (0xDEu) // DMA Start Copy and Checksum with Seed |
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| 174 | #define SETTXRTS (0xD4u) // Set TXRTS bit (transmit a packet) |
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| 175 | #define ENABLERX (0xE8u) // Enable RX |
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| 176 | #define DISABLERX (0xEAu) // Disable RX |
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| 177 | #define SETEIE (0xECu) // Set Ethernet Interrupt Enable (EIE) |
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| 178 | #define CLREIE (0xEEu) // Clear Ethernet Interrupt Enable (EIE) |
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| 179 | #endif |
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| 180 | |||
| 181 | //////////////////////////////////////////////////// |
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| 182 | // ENC424J600/624J600 register addresses // |
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| 183 | //////////////////////////////////////////////////// |
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| 184 | // SPI Bank 0 registers -------- |
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| 185 | #define ETXST ENC100_TRANSLATE_TO_PIN_ADDR(0x7E00u) |
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| 186 | #define ETXSTL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E00u) |
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| 187 | #define ETXSTH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E01u) |
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| 188 | #define ETXLEN ENC100_TRANSLATE_TO_PIN_ADDR(0x7E02u) |
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| 189 | #define ETXLENL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E02u) |
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| 190 | #define ETXLENH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E03u) |
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| 191 | #define ERXST ENC100_TRANSLATE_TO_PIN_ADDR(0x7E04u) |
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| 192 | #define ERXSTL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E04u) |
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| 193 | #define ERXSTH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E05u) |
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| 194 | #define ERXTAIL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E06u) |
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| 195 | #define ERXTAILL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E06u) |
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| 196 | #define ERXTAILH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E07u) |
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| 197 | #define ERXHEAD ENC100_TRANSLATE_TO_PIN_ADDR(0x7E08u) |
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| 198 | #define ERXHEADL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E08u) |
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| 199 | #define ERXHEADH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E09u) |
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| 200 | #define EDMAST ENC100_TRANSLATE_TO_PIN_ADDR(0x7E0Au) |
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| 201 | #define EDMASTL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E0Au) |
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| 202 | #define EDMASTH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E0Bu) |
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| 203 | #define EDMALEN ENC100_TRANSLATE_TO_PIN_ADDR(0x7E0Cu) |
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| 204 | #define EDMALENL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E0Cu) |
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| 205 | #define EDMALENH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E0Du) |
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| 206 | #define EDMADST ENC100_TRANSLATE_TO_PIN_ADDR(0x7E0Eu) |
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| 207 | #define EDMADSTL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E0Eu) |
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| 208 | #define EDMADSTH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E0Fu) |
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| 209 | #define EDMACS ENC100_TRANSLATE_TO_PIN_ADDR(0x7E10u) |
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| 210 | #define EDMACSL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E10u) |
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| 211 | #define EDMACSH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E11u) |
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| 212 | #define ETXSTAT ENC100_TRANSLATE_TO_PIN_ADDR(0x7E12u) |
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| 213 | #define ETXSTATL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E12u) |
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| 214 | #define ETXSTATH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E13u) |
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| 215 | #define ETXWIRE ENC100_TRANSLATE_TO_PIN_ADDR(0x7E14u) |
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| 216 | #define ETXWIREL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E14u) |
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| 217 | #define ETXWIREH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E15u) |
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| 218 | |||
| 219 | // SPI all bank registers |
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| 220 | #define EUDAST ENC100_TRANSLATE_TO_PIN_ADDR(0x7E16u) |
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| 221 | #define EUDASTL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E16u) |
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| 222 | #define EUDASTH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E17u) |
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| 223 | #define EUDAND ENC100_TRANSLATE_TO_PIN_ADDR(0x7E18u) |
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| 224 | #define EUDANDL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E18u) |
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| 225 | #define EUDANDH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E19u) |
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| 226 | #define ESTAT ENC100_TRANSLATE_TO_PIN_ADDR(0x7E1Au) |
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| 227 | #define ESTATL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E1Au) |
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| 228 | #define ESTATH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E1Bu) |
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| 229 | #define EIR ENC100_TRANSLATE_TO_PIN_ADDR(0x7E1Cu) |
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| 230 | #define EIRL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E1Cu) |
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| 231 | #define EIRH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E1Du) |
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| 232 | #define ECON1 ENC100_TRANSLATE_TO_PIN_ADDR(0x7E1Eu) |
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| 233 | #define ECON1L ENC100_TRANSLATE_TO_PIN_ADDR(0x7E1Eu) |
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| 234 | #define ECON1H ENC100_TRANSLATE_TO_PIN_ADDR(0x7E1Fu) |
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| 235 | |||
| 236 | |||
| 237 | // SPI Bank 1 registers ----- |
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| 238 | #define EHT1 ENC100_TRANSLATE_TO_PIN_ADDR(0x7E20u) |
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| 239 | #define EHT1L ENC100_TRANSLATE_TO_PIN_ADDR(0x7E20u) |
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| 240 | #define EHT1H ENC100_TRANSLATE_TO_PIN_ADDR(0x7E21u) |
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| 241 | #define EHT2 ENC100_TRANSLATE_TO_PIN_ADDR(0x7E22u) |
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| 242 | #define EHT2L ENC100_TRANSLATE_TO_PIN_ADDR(0x7E22u) |
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| 243 | #define EHT2H ENC100_TRANSLATE_TO_PIN_ADDR(0x7E23u) |
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| 244 | #define EHT3 ENC100_TRANSLATE_TO_PIN_ADDR(0x7E24u) |
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| 245 | #define EHT3L ENC100_TRANSLATE_TO_PIN_ADDR(0x7E24u) |
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| 246 | #define EHT3H ENC100_TRANSLATE_TO_PIN_ADDR(0x7E25u) |
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| 247 | #define EHT4 ENC100_TRANSLATE_TO_PIN_ADDR(0x7E26u) |
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| 248 | #define EHT4L ENC100_TRANSLATE_TO_PIN_ADDR(0x7E26u) |
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| 249 | #define EHT4H ENC100_TRANSLATE_TO_PIN_ADDR(0x7E27u) |
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| 250 | #define EPMM1 ENC100_TRANSLATE_TO_PIN_ADDR(0x7E28u) |
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| 251 | #define EPMM1L ENC100_TRANSLATE_TO_PIN_ADDR(0x7E28u) |
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| 252 | #define EPMM1H ENC100_TRANSLATE_TO_PIN_ADDR(0x7E29u) |
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| 253 | #define EPMM2 ENC100_TRANSLATE_TO_PIN_ADDR(0x7E2Au) |
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| 254 | #define EPMM2L ENC100_TRANSLATE_TO_PIN_ADDR(0x7E2Au) |
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| 255 | #define EPMM2H ENC100_TRANSLATE_TO_PIN_ADDR(0x7E2Bu) |
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| 256 | #define EPMM3 ENC100_TRANSLATE_TO_PIN_ADDR(0x7E2Cu) |
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| 257 | #define EPMM3L ENC100_TRANSLATE_TO_PIN_ADDR(0x7E2Cu) |
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| 258 | #define EPMM3H ENC100_TRANSLATE_TO_PIN_ADDR(0x7E2Du) |
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| 259 | #define EPMM4 ENC100_TRANSLATE_TO_PIN_ADDR(0x7E2Eu) |
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| 260 | #define EPMM4L ENC100_TRANSLATE_TO_PIN_ADDR(0x7E2Eu) |
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| 261 | #define EPMM4H ENC100_TRANSLATE_TO_PIN_ADDR(0x7E2Fu) |
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| 262 | #define EPMCS ENC100_TRANSLATE_TO_PIN_ADDR(0x7E30u) |
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| 263 | #define EPMCSL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E30u) |
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| 264 | #define EPMCSH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E31u) |
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| 265 | #define EPMO ENC100_TRANSLATE_TO_PIN_ADDR(0x7E32u) |
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| 266 | #define EPMOL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E32u) |
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| 267 | #define EPMOH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E33u) |
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| 268 | #define ERXFCON ENC100_TRANSLATE_TO_PIN_ADDR(0x7E34u) |
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| 269 | #define ERXFCONL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E34u) |
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| 270 | #define ERXFCONH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E35u) |
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| 271 | |||
| 272 | // SPI all bank registers from 0x36 to 0x3F |
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| 273 | |||
| 274 | |||
| 275 | // SPI Bank 2 registers ----- |
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| 276 | #define MACON1 ENC100_TRANSLATE_TO_PIN_ADDR(0x7E40u) |
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| 277 | #define MACON1L ENC100_TRANSLATE_TO_PIN_ADDR(0x7E40u) |
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| 278 | #define MACON1H ENC100_TRANSLATE_TO_PIN_ADDR(0x7E41u) |
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| 279 | #define MACON2 ENC100_TRANSLATE_TO_PIN_ADDR(0x7E42u) |
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| 280 | #define MACON2L ENC100_TRANSLATE_TO_PIN_ADDR(0x7E42u) |
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| 281 | #define MACON2H ENC100_TRANSLATE_TO_PIN_ADDR(0x7E43u) |
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| 282 | #define MABBIPG ENC100_TRANSLATE_TO_PIN_ADDR(0x7E44u) |
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| 283 | #define MABBIPGL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E44u) |
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| 284 | #define MABBIPGH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E45u) |
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| 285 | #define MAIPG ENC100_TRANSLATE_TO_PIN_ADDR(0x7E46u) |
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| 286 | #define MAIPGL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E46u) |
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| 287 | #define MAIPGH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E47u) |
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| 288 | #define MACLCON ENC100_TRANSLATE_TO_PIN_ADDR(0x7E48u) |
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| 289 | #define MACLCONL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E48u) |
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| 290 | #define MACLCONH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E49u) |
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| 291 | #define MAMXFL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E4Au) |
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| 292 | #define MAMXFLL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E4Au) |
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| 293 | #define MAMXFLH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E4Bu) |
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| 294 | //#define r ENC100_TRANSLATE_TO_PIN_ADDR(0x7E4Cu) |
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| 295 | //#define r ENC100_TRANSLATE_TO_PIN_ADDR(0x7E4Du) |
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| 296 | //#define r ENC100_TRANSLATE_TO_PIN_ADDR(0x7E4Eu) |
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| 297 | //#define r ENC100_TRANSLATE_TO_PIN_ADDR(0x7E4Fu) |
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| 298 | //#define r ENC100_TRANSLATE_TO_PIN_ADDR(0x7E50u) |
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| 299 | //#define r ENC100_TRANSLATE_TO_PIN_ADDR(0x7E51u) |
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| 300 | #define MICMD ENC100_TRANSLATE_TO_PIN_ADDR(0x7E52u) |
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| 301 | #define MICMDL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E52u) |
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| 302 | #define MICMDH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E53u) |
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| 303 | #define MIREGADR ENC100_TRANSLATE_TO_PIN_ADDR(0x7E54u) |
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| 304 | #define MIREGADRL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E54u) |
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| 305 | #define MIREGADRH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E55u) |
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| 306 | |||
| 307 | // SPI all bank registers from 0x56 to 0x5F |
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| 308 | |||
| 309 | |||
| 310 | // SPI Bank 3 registers ----- |
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| 311 | #define MAADR3 ENC100_TRANSLATE_TO_PIN_ADDR(0x7E60u) |
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| 312 | #define MAADR3L ENC100_TRANSLATE_TO_PIN_ADDR(0x7E60u) |
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| 313 | #define MAADR3H ENC100_TRANSLATE_TO_PIN_ADDR(0x7E61u) |
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| 314 | #define MAADR2 ENC100_TRANSLATE_TO_PIN_ADDR(0x7E62u) |
||
| 315 | #define MAADR2L ENC100_TRANSLATE_TO_PIN_ADDR(0x7E62u) |
||
| 316 | #define MAADR2H ENC100_TRANSLATE_TO_PIN_ADDR(0x7E63u) |
||
| 317 | #define MAADR1 ENC100_TRANSLATE_TO_PIN_ADDR(0x7E64u) |
||
| 318 | #define MAADR1L ENC100_TRANSLATE_TO_PIN_ADDR(0x7E64u) |
||
| 319 | #define MAADR1H ENC100_TRANSLATE_TO_PIN_ADDR(0x7E65u) |
||
| 320 | #define MIWR ENC100_TRANSLATE_TO_PIN_ADDR(0x7E66u) |
||
| 321 | #define MIWRL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E66u) |
||
| 322 | #define MIWRH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E67u) |
||
| 323 | #define MIRD ENC100_TRANSLATE_TO_PIN_ADDR(0x7E68u) |
||
| 324 | #define MIRDL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E68u) |
||
| 325 | #define MIRDH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E69u) |
||
| 326 | #define MISTAT ENC100_TRANSLATE_TO_PIN_ADDR(0x7E6Au) |
||
| 327 | #define MISTATL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E6Au) |
||
| 328 | #define MISTATH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E6Bu) |
||
| 329 | #define EPAUS ENC100_TRANSLATE_TO_PIN_ADDR(0x7E6Cu) |
||
| 330 | #define EPAUSL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E6Cu) |
||
| 331 | #define EPAUSH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E6Du) |
||
| 332 | #define ECON2 ENC100_TRANSLATE_TO_PIN_ADDR(0x7E6Eu) |
||
| 333 | #define ECON2L ENC100_TRANSLATE_TO_PIN_ADDR(0x7E6Eu) |
||
| 334 | #define ECON2H ENC100_TRANSLATE_TO_PIN_ADDR(0x7E6Fu) |
||
| 335 | #define ERXWM ENC100_TRANSLATE_TO_PIN_ADDR(0x7E70u) |
||
| 336 | #define ERXWML ENC100_TRANSLATE_TO_PIN_ADDR(0x7E70u) |
||
| 337 | #define ERXWMH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E71u) |
||
| 338 | #define EIE ENC100_TRANSLATE_TO_PIN_ADDR(0x7E72u) |
||
| 339 | #define EIEL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E72u) |
||
| 340 | #define EIEH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E73u) |
||
| 341 | #define EIDLED ENC100_TRANSLATE_TO_PIN_ADDR(0x7E74u) |
||
| 342 | #define EIDLEDL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E74u) |
||
| 343 | #define EIDLEDH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E75u) |
||
| 344 | |||
| 345 | // SPI all bank registers from 0x66 to 0x6F |
||
| 346 | |||
| 347 | |||
| 348 | // SPI Non-banked Special Function Registers |
||
| 349 | #define EGPDATA ENC100_TRANSLATE_TO_PIN_ADDR(0x7E80u) |
||
| 350 | #define EGPDATAL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E80u) |
||
| 351 | //#define r ENC100_TRANSLATE_TO_PIN_ADDR(0x7E81u) |
||
| 352 | #define ERXDATA ENC100_TRANSLATE_TO_PIN_ADDR(0x7E82u) |
||
| 353 | #define ERXDATAL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E82u) |
||
| 354 | //#define r ENC100_TRANSLATE_TO_PIN_ADDR(0x7E83u) |
||
| 355 | #define EUDADATA ENC100_TRANSLATE_TO_PIN_ADDR(0x7E84u) |
||
| 356 | #define EUDADATAL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E84u) |
||
| 357 | //#define r ENC100_TRANSLATE_TO_PIN_ADDR(0x7E85u) |
||
| 358 | #define EGPRDPT ENC100_TRANSLATE_TO_PIN_ADDR(0x7E86u) |
||
| 359 | #define EGPRDPTL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E86u) |
||
| 360 | #define EGPRDPTH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E87u) |
||
| 361 | #define EGPWRPT ENC100_TRANSLATE_TO_PIN_ADDR(0x7E88u) |
||
| 362 | #define EGPWRPTL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E88u) |
||
| 363 | #define EGPWRPTH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E89u) |
||
| 364 | #define ERXRDPT ENC100_TRANSLATE_TO_PIN_ADDR(0x7E8Au) |
||
| 365 | #define ERXRDPTL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E8Au) |
||
| 366 | #define ERXRDPTH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E8Bu) |
||
| 367 | #define ERXWRPT ENC100_TRANSLATE_TO_PIN_ADDR(0x7E8Cu) |
||
| 368 | #define ERXWRPTL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E8Cu) |
||
| 369 | #define ERXWRPTH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E8Du) |
||
| 370 | #define EUDARDPT ENC100_TRANSLATE_TO_PIN_ADDR(0x7E8Eu) |
||
| 371 | #define EUDARDPTL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E8Eu) |
||
| 372 | #define EUDARDPTH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E8Fu) |
||
| 373 | #define EUDAWRPT ENC100_TRANSLATE_TO_PIN_ADDR(0x7E90u) |
||
| 374 | #define EUDAWRPTL ENC100_TRANSLATE_TO_PIN_ADDR(0x7E90u) |
||
| 375 | #define EUDAWRPTH ENC100_TRANSLATE_TO_PIN_ADDR(0x7E91u) |
||
| 376 | |||
| 377 | |||
| 378 | |||
| 379 | //////////////////////////////////////////////////// |
||
| 380 | // ENC424J600/624J600 PHY Register Addresses // |
||
| 381 | //////////////////////////////////////////////////// |
||
| 382 | #define PHCON1 0x00u |
||
| 383 | #define PHSTAT1 0x01u |
||
| 384 | #define PHANA 0x04u |
||
| 385 | #define PHANLPA 0x05u |
||
| 386 | #define PHANE 0x06u |
||
| 387 | #define PHCON2 0x11u |
||
| 388 | #define PHSTAT2 0x1Bu |
||
| 389 | #define PHSTAT3 0x1Fu |
||
| 390 | |||
| 391 | |||
| 392 | |||
| 393 | //////////////////////////////////////////////////// |
||
| 394 | // ENC424J600/624J600 register bits // |
||
| 395 | //////////////////////////////////////////////////// |
||
| 396 | // ESTAT bits ---------- |
||
| 397 | #define ESTAT_INT ((WORD)1<<15) |
||
| 398 | #define ESTAT_FCIDLE ((WORD)1<<14) |
||
| 399 | #define ESTAT_RXBUSY ((WORD)1<<13) |
||
| 400 | #define ESTAT_CLKRDY ((WORD)1<<12) |
||
| 401 | #define ESTAT_RSTDONE ((WORD)1<<11) |
||
| 402 | #define ESTAT_PHYDPX ((WORD)1<<10) |
||
| 403 | #define ESTAT_PHYRDY ((WORD)1<<9) |
||
| 404 | #define ESTAT_PHYLNK ((WORD)1<<8) |
||
| 405 | #define ESTAT_PKTCNT7 (1<<7) |
||
| 406 | #define ESTAT_PKTCNT6 (1<<6) |
||
| 407 | #define ESTAT_PKTCNT5 (1<<5) |
||
| 408 | #define ESTAT_PKTCNT4 (1<<4) |
||
| 409 | #define ESTAT_PKTCNT3 (1<<3) |
||
| 410 | #define ESTAT_PKTCNT2 (1<<2) |
||
| 411 | #define ESTAT_PKTCNT1 (1<<1) |
||
| 412 | #define ESTAT_PKTCNT0 (1) |
||
| 413 | |||
| 414 | // EIR bits ------------ |
||
| 415 | #define EIR_CRYPTEN ((WORD)1<<15) |
||
| 416 | #define EIR_MODEXIF ((WORD)1<<14) |
||
| 417 | #define EIR_HASHIF ((WORD)1<<13) |
||
| 418 | #define EIR_AESIF ((WORD)1<<12) |
||
| 419 | #define EIR_LINKIF ((WORD)1<<11) |
||
| 420 | #define EIR_PRDYIF ((WORD)1<<10) |
||
| 421 | #define EIR_r9 ((WORD)1<<9) |
||
| 422 | #define EIR_r8 ((WORD)1<<8) |
||
| 423 | #define EIR_r7 (1<<7) |
||
| 424 | #define EIR_PKTIF (1<<6) |
||
| 425 | #define EIR_DMAIF (1<<5) |
||
| 426 | #define EIR_r4 (1<<4) |
||
| 427 | #define EIR_TXIF (1<<3) |
||
| 428 | #define EIR_TXABTIF (1<<2) |
||
| 429 | #define EIR_RXABTIF (1<<1) |
||
| 430 | #define EIR_PCFULIF (1) |
||
| 431 | |||
| 432 | // ECON1 bits ---------- |
||
| 433 | #define ECON1_MODEXST ((WORD)1<<15) |
||
| 434 | #define ECON1_HASHEN ((WORD)1<<14) |
||
| 435 | #define ECON1_HASHOP ((WORD)1<<13) |
||
| 436 | #define ECON1_HASHLST ((WORD)1<<12) |
||
| 437 | #define ECON1_AESST ((WORD)1<<11) |
||
| 438 | #define ECON1_AESOP1 ((WORD)1<<10) |
||
| 439 | #define ECON1_AESOP0 ((WORD)1<<9) |
||
| 440 | #define ECON1_PKTDEC ((WORD)1<<8) |
||
| 441 | #define ECON1_FCOP1 (1<<7) |
||
| 442 | #define ECON1_FCOP0 (1<<6) |
||
| 443 | #define ECON1_DMAST (1<<5) |
||
| 444 | #define ECON1_DMACPY (1<<4) |
||
| 445 | #define ECON1_DMACSSD (1<<3) |
||
| 446 | #define ECON1_DMANOCS (1<<2) |
||
| 447 | #define ECON1_TXRTS (1<<1) |
||
| 448 | #define ECON1_RXEN (1) |
||
| 449 | |||
| 450 | // ETXSTAT bits -------- |
||
| 451 | #define ETXSTAT_r12 ((WORD)1<<12) |
||
| 452 | #define ETXSTAT_r11 ((WORD)1<<11) |
||
| 453 | #define ETXSTAT_LATECOL ((WORD)1<<10) |
||
| 454 | #define ETXSTAT_MAXCOL ((WORD)1<<9) |
||
| 455 | #define ETXSTAT_EXDEFER ((WORD)1<<8) |
||
| 456 | #define ETXSTAT_DEFER (1<<7) |
||
| 457 | #define ETXSTAT_r6 (1<<6) |
||
| 458 | #define ETXSTAT_r5 (1<<5) |
||
| 459 | #define ETXSTAT_CRCBAD (1<<4) |
||
| 460 | #define ETXSTAT_COLCNT3 (1<<3) |
||
| 461 | #define ETXSTAT_COLCNT2 (1<<2) |
||
| 462 | #define ETXSTAT_COLCNT1 (1<<1) |
||
| 463 | #define ETXSTAT_COLCNT0 (1) |
||
| 464 | |||
| 465 | // ERXFCON bits -------- |
||
| 466 | #define ERXFCON_HTEN ((WORD)1<<15) |
||
| 467 | #define ERXFCON_MPEN ((WORD)1<<14) |
||
| 468 | #define ERXFCON_NOTPM ((WORD)1<<12) |
||
| 469 | #define ERXFCON_PMEN3 ((WORD)1<<11) |
||
| 470 | #define ERXFCON_PMEN2 ((WORD)1<<10) |
||
| 471 | #define ERXFCON_PMEN1 ((WORD)1<<9) |
||
| 472 | #define ERXFCON_PMEN0 ((WORD)1<<8) |
||
| 473 | #define ERXFCON_CRCEEN (1<<7) |
||
| 474 | #define ERXFCON_CRCEN (1<<6) |
||
| 475 | #define ERXFCON_RUNTEEN (1<<5) |
||
| 476 | #define ERXFCON_RUNTEN (1<<4) |
||
| 477 | #define ERXFCON_UCEN (1<<3) |
||
| 478 | #define ERXFCON_NOTMEEN (1<<2) |
||
| 479 | #define ERXFCON_MCEN (1<<1) |
||
| 480 | #define ERXFCON_BCEN (1) |
||
| 481 | |||
| 482 | // MACON1 bits --------- |
||
| 483 | #define MACON1_r15 ((WORD)1<<15) |
||
| 484 | #define MACON1_r14 ((WORD)1<<14) |
||
| 485 | #define MACON1_r11 ((WORD)1<<11) |
||
| 486 | #define MACON1_r10 ((WORD)1<<10) |
||
| 487 | #define MACON1_r9 ((WORD)1<<9) |
||
| 488 | #define MACON1_r8 ((WORD)1<<8) |
||
| 489 | #define MACON1_LOOPBK (1<<4) |
||
| 490 | #define MACON1_r3 (1<<3) |
||
| 491 | #define MACON1_RXPAUS (1<<2) |
||
| 492 | #define MACON1_PASSALL (1<<1) |
||
| 493 | #define MACON1_r0 (1) |
||
| 494 | |||
| 495 | // MACON2 bits --------- |
||
| 496 | #define MACON2_DEFER ((WORD)1<<14) |
||
| 497 | #define MACON2_BPEN ((WORD)1<<13) |
||
| 498 | #define MACON2_NOBKOFF ((WORD)1<<12) |
||
| 499 | #define MACON2_r9 ((WORD)1<<9) |
||
| 500 | #define MACON2_r8 ((WORD)1<<8) |
||
| 501 | #define MACON2_PADCFG2 (1<<7) |
||
| 502 | #define MACON2_PADCFG1 (1<<6) |
||
| 503 | #define MACON2_PADCFG0 (1<<5) |
||
| 504 | #define MACON2_TXCRCEN (1<<4) |
||
| 505 | #define MACON2_PHDREN (1<<3) |
||
| 506 | #define MACON2_HFRMEN (1<<2) |
||
| 507 | #define MACON2_r1 (1<<1) |
||
| 508 | #define MACON2_FULDPX (1) |
||
| 509 | |||
| 510 | // MABBIPG bits -------- |
||
| 511 | #define MABBIPG_BBIPG6 (1<<6) |
||
| 512 | #define MABBIPG_BBIPG5 (1<<5) |
||
| 513 | #define MABBIPG_BBIPG4 (1<<4) |
||
| 514 | #define MABBIPG_BBIPG3 (1<<3) |
||
| 515 | #define MABBIPG_BBIPG2 (1<<2) |
||
| 516 | #define MABBIPG_BBIPG1 (1<<1) |
||
| 517 | #define MABBIPG_BBIPG0 (1) |
||
| 518 | |||
| 519 | // MAIPG bits ---------- |
||
| 520 | #define MAIPG_r14 ((WORD)1<<14) |
||
| 521 | #define MAIPG_r13 ((WORD)1<<13) |
||
| 522 | #define MAIPG_r12 ((WORD)1<<12) |
||
| 523 | #define MAIPG_r11 ((WORD)1<<11) |
||
| 524 | #define MAIPG_r10 ((WORD)1<<10) |
||
| 525 | #define MAIPG_r9 ((WORD)1<<9) |
||
| 526 | #define MAIPG_r8 ((WORD)1<<8) |
||
| 527 | #define MAIPG_IPG6 (1<<6) |
||
| 528 | #define MAIPG_IPG5 (1<<5) |
||
| 529 | #define MAIPG_IPG4 (1<<4) |
||
| 530 | #define MAIPG_IPG3 (1<<3) |
||
| 531 | #define MAIPG_IPG2 (1<<2) |
||
| 532 | #define MAIPG_IPG1 (1<<1) |
||
| 533 | #define MAIPG_IPG0 (1) |
||
| 534 | |||
| 535 | // MACLCON bits -------- |
||
| 536 | #define MACLCON_r13 ((WORD)1<<13) |
||
| 537 | #define MACLCON_r12 ((WORD)1<<12) |
||
| 538 | #define MACLCON_r11 ((WORD)1<<11) |
||
| 539 | #define MACLCON_r10 ((WORD)1<<10) |
||
| 540 | #define MACLCON_r9 ((WORD)1<<9) |
||
| 541 | #define MACLCON_r8 ((WORD)1<<8) |
||
| 542 | #define MACLCON_MAXRET3 (1<<3) |
||
| 543 | #define MACLCON_MAXRET2 (1<<2) |
||
| 544 | #define MACLCON_MAXRET1 (1<<1) |
||
| 545 | #define MACLCON_MAXRET0 (1) |
||
| 546 | |||
| 547 | // MICMD bits ---------- |
||
| 548 | #define MICMD_MIISCAN (1<<1) |
||
| 549 | #define MICMD_MIIRD (1) |
||
| 550 | |||
| 551 | // MIREGADR bits ------- |
||
| 552 | #define MIREGADR_r12 ((WORD)1<<12) |
||
| 553 | #define MIREGADR_r11 ((WORD)1<<11) |
||
| 554 | #define MIREGADR_r10 ((WORD)1<<10) |
||
| 555 | #define MIREGADR_r9 ((WORD)1<<9) |
||
| 556 | #define MIREGADR_r8 ((WORD)1<<8) |
||
| 557 | #define MIREGADR_PHREG4 (1<<4) |
||
| 558 | #define MIREGADR_PHREG3 (1<<3) |
||
| 559 | #define MIREGADR_PHREG2 (1<<2) |
||
| 560 | #define MIREGADR_PHREG1 (1<<1) |
||
| 561 | #define MIREGADR_PHREG0 (1) |
||
| 562 | |||
| 563 | // MISTAT bits --------- |
||
| 564 | #define MISTAT_r3 (1<<3) |
||
| 565 | #define MISTAT_NVALID (1<<2) |
||
| 566 | #define MISTAT_SCAN (1<<1) |
||
| 567 | #define MISTAT_BUSY (1) |
||
| 568 | |||
| 569 | // ECON2 bits ---------- |
||
| 570 | #define ECON2_ETHEN ((WORD)1<<15) |
||
| 571 | #define ECON2_STRCH ((WORD)1<<14) |
||
| 572 | #define ECON2_TXMAC ((WORD)1<<13) |
||
| 573 | #define ECON2_SHA1MD5 ((WORD)1<<12) |
||
| 574 | #define ECON2_COCON3 ((WORD)1<<11) |
||
| 575 | #define ECON2_COCON2 ((WORD)1<<10) |
||
| 576 | #define ECON2_COCON1 ((WORD)1<<9) |
||
| 577 | #define ECON2_COCON0 ((WORD)1<<8) |
||
| 578 | #define ECON2_AUTOFC (1<<7) |
||
| 579 | #define ECON2_TXRST (1<<6) |
||
| 580 | #define ECON2_RXRST (1<<5) |
||
| 581 | #define ECON2_ETHRST (1<<4) |
||
| 582 | #define ECON2_MODLEN1 (1<<3) |
||
| 583 | #define ECON2_MODLEN0 (1<<2) |
||
| 584 | #define ECON2_AESLEN1 (1<<1) |
||
| 585 | #define ECON2_AESLEN0 (1) |
||
| 586 | |||
| 587 | // ERXWM bits ---------- |
||
| 588 | #define ERXWM_RXFWM7 ((WORD)1<<15) |
||
| 589 | #define ERXWM_RXFWM6 ((WORD)1<<14) |
||
| 590 | #define ERXWM_RXFWM5 ((WORD)1<<13) |
||
| 591 | #define ERXWM_RXFWM4 ((WORD)1<<12) |
||
| 592 | #define ERXWM_RXFWM3 ((WORD)1<<11) |
||
| 593 | #define ERXWM_RXFWM2 ((WORD)1<<10) |
||
| 594 | #define ERXWM_RXFWM1 ((WORD)1<<9) |
||
| 595 | #define ERXWM_RXFWM0 ((WORD)1<<8) |
||
| 596 | #define ERXWM_RXEWM7 (1<<7) |
||
| 597 | #define ERXWM_RXEWM6 (1<<6) |
||
| 598 | #define ERXWM_RXEWM5 (1<<5) |
||
| 599 | #define ERXWM_RXEWM4 (1<<4) |
||
| 600 | #define ERXWM_RXEWM3 (1<<3) |
||
| 601 | #define ERXWM_RXEWM2 (1<<2) |
||
| 602 | #define ERXWM_RXEWM1 (1<<1) |
||
| 603 | #define ERXWM_RXEWM0 (1) |
||
| 604 | |||
| 605 | // EIE bits ------------ |
||
| 606 | #define EIE_INTIE ((WORD)1<<15) |
||
| 607 | #define EIE_MODEXIE ((WORD)1<<14) |
||
| 608 | #define EIE_HASHIE ((WORD)1<<13) |
||
| 609 | #define EIE_AESIE ((WORD)1<<12) |
||
| 610 | #define EIE_LINKIE ((WORD)1<<11) |
||
| 611 | #define EIE_PRDYIE ((WORD)1<<10) |
||
| 612 | #define EIE_r9 ((WORD)1<<9) |
||
| 613 | #define EIE_r8 ((WORD)1<<8) |
||
| 614 | #define EIE_r7 (1<<7) |
||
| 615 | #define EIE_PKTIE (1<<6) |
||
| 616 | #define EIE_DMAIE (1<<5) |
||
| 617 | #define EIE_r4 (1<<4) |
||
| 618 | #define EIE_TXIE (1<<3) |
||
| 619 | #define EIE_TXABTIE (1<<2) |
||
| 620 | #define EIE_RXABTIE (1<<1) |
||
| 621 | #define EIE_PCFULIE (1) |
||
| 622 | |||
| 623 | // EIDLED bits --------- |
||
| 624 | #define EIDLED_LACFG3 ((WORD)1<<15) |
||
| 625 | #define EIDLED_LACFG2 ((WORD)1<<14) |
||
| 626 | #define EIDLED_LACFG1 ((WORD)1<<13) |
||
| 627 | #define EIDLED_LACFG0 ((WORD)1<<12) |
||
| 628 | #define EIDLED_LBCFG3 ((WORD)1<<11) |
||
| 629 | #define EIDLED_LBCFG2 ((WORD)1<<10) |
||
| 630 | #define EIDLED_LBCFG1 ((WORD)1<<9) |
||
| 631 | #define EIDLED_LBCFG0 ((WORD)1<<8) |
||
| 632 | #define EIDLED_DEVID2 (1<<7) |
||
| 633 | #define EIDLED_DEVID1 (1<<6) |
||
| 634 | #define EIDLED_DEVID0 (1<<5) |
||
| 635 | #define EIDLED_REVID4 (1<<4) |
||
| 636 | #define EIDLED_REVID3 (1<<3) |
||
| 637 | #define EIDLED_REVID2 (1<<2) |
||
| 638 | #define EIDLED_REVID1 (1<<1) |
||
| 639 | #define EIDLED_REVID0 (1) |
||
| 640 | |||
| 641 | // PHCON1 bits --------- |
||
| 642 | #define PHCON1_PRST ((WORD)1<<15) |
||
| 643 | #define PHCON1_PLOOPBK ((WORD)1<<14) |
||
| 644 | #define PHCON1_SPD100 ((WORD)1<<13) |
||
| 645 | #define PHCON1_ANEN ((WORD)1<<12) |
||
| 646 | #define PHCON1_PSLEEP ((WORD)1<<11) |
||
| 647 | #define PHCON1_r10 ((WORD)1<<10) |
||
| 648 | #define PHCON1_RENEG ((WORD)1<<9) |
||
| 649 | #define PHCON1_PFULDPX ((WORD)1<<8) |
||
| 650 | #define PHCON1_r7 (1<<7) |
||
| 651 | #define PHCON1_r6 (1<<6) |
||
| 652 | #define PHCON1_r5 (1<<5) |
||
| 653 | #define PHCON1_r4 (1<<4) |
||
| 654 | #define PHCON1_r3 (1<<3) |
||
| 655 | #define PHCON1_r2 (1<<2) |
||
| 656 | #define PHCON1_r1 (1<<1) |
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| 657 | #define PHCON1_r0 (1) |
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| 658 | |||
| 659 | // PHSTAT1 bits -------- |
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| 660 | #define PHSTAT1_r15 ((WORD)1<<15) |
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| 661 | #define PHSTAT1_FULL100 ((WORD)1<<14) |
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| 662 | #define PHSTAT1_HALF100 ((WORD)1<<13) |
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| 663 | #define PHSTAT1_FULL10 ((WORD)1<<12) |
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| 664 | #define PHSTAT1_HALF10 ((WORD)1<<11) |
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| 665 | #define PHSTAT1_r10 ((WORD)1<<10) |
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| 666 | #define PHSTAT1_r9 ((WORD)1<<9) |
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| 667 | #define PHSTAT1_r8 ((WORD)1<<8) |
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| 668 | #define PHSTAT1_r7 (1<<7) |
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| 669 | #define PHSTAT1_r6 (1<<6) |
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| 670 | #define PHSTAT1_ANDONE (1<<5) |
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| 671 | #define PHSTAT1_LRFAULT (1<<4) |
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| 672 | #define PHSTAT1_ANABLE (1<<3) |
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| 673 | #define PHSTAT1_LLSTAT (1<<2) |
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| 674 | #define PHSTAT1_r1 (1<<1) |
||
| 675 | #define PHSTAT1_EXTREGS (1) |
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| 676 | |||
| 677 | // PHANA bits ---------- |
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| 678 | #define PHANA_ADNP ((WORD)1<<15) |
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| 679 | #define PHANA_r14 ((WORD)1<<14) |
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| 680 | #define PHANA_ADFAULT ((WORD)1<<13) |
||
| 681 | #define PHANA_r12 ((WORD)1<<12) |
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| 682 | #define PHANA_ADPAUS1 ((WORD)1<<11) |
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| 683 | #define PHANA_ADPAUS0 ((WORD)1<<10) |
||
| 684 | #define PHANA_r9 ((WORD)1<<9) |
||
| 685 | #define PHANA_AD100FD ((WORD)1<<8) |
||
| 686 | #define PHANA_AD100 (1<<7) |
||
| 687 | #define PHANA_AD10FD (1<<6) |
||
| 688 | #define PHANA_AD10 (1<<5) |
||
| 689 | #define PHANA_ADIEEE4 (1<<4) |
||
| 690 | #define PHANA_ADIEEE3 (1<<3) |
||
| 691 | #define PHANA_ADIEEE2 (1<<2) |
||
| 692 | #define PHANA_ADIEEE1 (1<<1) |
||
| 693 | #define PHANA_ADIEEE0 (1) |
||
| 694 | |||
| 695 | // PHANLPA bits -------- |
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| 696 | #define PHANLPA_LPNP ((WORD)1<<15) |
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| 697 | #define PHANLPA_LPACK ((WORD)1<<14) |
||
| 698 | #define PHANLPA_LPFAULT ((WORD)1<<13) |
||
| 699 | #define PHANLPA_r12 ((WORD)1<<12) |
||
| 700 | #define PHANLPA_LPPAUS1 ((WORD)1<<11) |
||
| 701 | #define PHANLPA_LPPAUS0 ((WORD)1<<10) |
||
| 702 | #define PHANLPA_LP100T4 ((WORD)1<<9) |
||
| 703 | #define PHANLPA_LP100FD ((WORD)1<<8) |
||
| 704 | #define PHANLPA_LP100 (1<<7) |
||
| 705 | #define PHANLPA_LP10FD (1<<6) |
||
| 706 | #define PHANLPA_LP10 (1<<5) |
||
| 707 | #define PHANLPA_LPIEEE4 (1<<4) |
||
| 708 | #define PHANLPA_LPIEEE3 (1<<3) |
||
| 709 | #define PHANLPA_LPIEEE2 (1<<2) |
||
| 710 | #define PHANLPA_LPIEEE1 (1<<1) |
||
| 711 | #define PHANLPA_LPIEEE0 (1) |
||
| 712 | |||
| 713 | // PHANE bits ---------- |
||
| 714 | #define PHANE_r15 ((WORD)1<<15) |
||
| 715 | #define PHANE_r14 ((WORD)1<<14) |
||
| 716 | #define PHANE_r13 ((WORD)1<<13) |
||
| 717 | #define PHANE_r12 ((WORD)1<<12) |
||
| 718 | #define PHANE_r11 ((WORD)1<<11) |
||
| 719 | #define PHANE_r10 ((WORD)1<<10) |
||
| 720 | #define PHANE_r9 ((WORD)1<<9) |
||
| 721 | #define PHANE_r8 ((WORD)1<<8) |
||
| 722 | #define PHANE_r7 (1<<7) |
||
| 723 | #define PHANE_r6 (1<<6) |
||
| 724 | #define PHANE_r5 (1<<5) |
||
| 725 | #define PHANE_PDFLT (1<<4) |
||
| 726 | #define PHANE_r3 (1<<3) |
||
| 727 | #define PHANE_r2 (1<<2) |
||
| 728 | #define PHANE_LPARCD (1<<1) |
||
| 729 | #define PHANA_LPANABL (1) |
||
| 730 | |||
| 731 | // PHCON2 bits --------- |
||
| 732 | #define PHCON2_r15 ((WORD)1<<15) |
||
| 733 | #define PHCON2_r14 ((WORD)1<<14) |
||
| 734 | #define PHCON2_EDPWRDN ((WORD)1<<13) |
||
| 735 | #define PHCON2_r12 ((WORD)1<<12) |
||
| 736 | #define PHCON2_EDTHRES ((WORD)1<<11) |
||
| 737 | #define PHCON2_r10 ((WORD)1<<10) |
||
| 738 | #define PHCON2_r9 ((WORD)1<<9) |
||
| 739 | #define PHCON2_r8 ((WORD)1<<8) |
||
| 740 | #define PHCON2_r7 (1<<7) |
||
| 741 | #define PHCON2_r6 (1<<6) |
||
| 742 | #define PHCON2_r5 (1<<5) |
||
| 743 | #define PHCON2_r4 (1<<4) |
||
| 744 | #define PHCON2_r3 (1<<3) |
||
| 745 | #define PHCON2_FRCLNK (1<<2) |
||
| 746 | #define PHCON2_EDSTAT (1<<1) |
||
| 747 | #define PHCON2_r0 (1) |
||
| 748 | |||
| 749 | // PHSTAT2 bits --------- |
||
| 750 | #define PHSTAT2_r15 ((WORD)1<<15) |
||
| 751 | #define PHSTAT2_r14 ((WORD)1<<14) |
||
| 752 | #define PHSTAT2_r13 ((WORD)1<<13) |
||
| 753 | #define PHSTAT2_r12 ((WORD)1<<12) |
||
| 754 | #define PHSTAT2_r11 ((WORD)1<<11) |
||
| 755 | #define PHSTAT2_r10 ((WORD)1<<10) |
||
| 756 | #define PHSTAT2_r9 ((WORD)1<<9) |
||
| 757 | #define PHSTAT2_r8 ((WORD)1<<8) |
||
| 758 | #define PHSTAT2_r7 (1<<7) |
||
| 759 | #define PHSTAT2_r6 (1<<6) |
||
| 760 | #define PHSTAT2_r5 (1<<5) |
||
| 761 | #define PHSTAT2_PLRITY (1<<4) |
||
| 762 | #define PHSTAT2_r3 (1<<3) |
||
| 763 | #define PHSTAT2_r2 (1<<2) |
||
| 764 | #define PHSTAT2_r1 (1<<1) |
||
| 765 | #define PHSTAT2_r0 (1) |
||
| 766 | |||
| 767 | // PHSTAT3 bits -------- |
||
| 768 | #define PHSTAT3_r15 ((WORD)1<<15) |
||
| 769 | #define PHSTAT3_r14 ((WORD)1<<14) |
||
| 770 | #define PHSTAT3_r13 ((WORD)1<<13) |
||
| 771 | #define PHSTAT3_r12 ((WORD)1<<12) |
||
| 772 | #define PHSTAT3_r11 ((WORD)1<<11) |
||
| 773 | #define PHSTAT3_r10 ((WORD)1<<10) |
||
| 774 | #define PHSTAT3_r9 ((WORD)1<<9) |
||
| 775 | #define PHSTAT3_r8 ((WORD)1<<8) |
||
| 776 | #define PHSTAT3_r7 (1<<7) |
||
| 777 | #define PHSTAT3_r6 (1<<6) |
||
| 778 | #define PHSTAT3_r5 (1<<5) |
||
| 779 | #define PHSTAT3_SPDDPX2 (1<<4) |
||
| 780 | #define PHSTAT3_SPDDPX1 (1<<3) |
||
| 781 | #define PHSTAT3_SPDDPX0 (1<<2) |
||
| 782 | #define PHSTAT3_r1 (1<<1) |
||
| 783 | #define PHSTAT3_r0 (1) |
||
| 784 | |||
| 785 | |||
| 786 | #endif |
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