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1 32 kaklik /*********************************************************************
2 *
3 * National 83640 definitions
4 *
5 *********************************************************************
6 * FileName: ETHPIC32ExtPhyDP83640.h
7 * Dependencies:
8 * Processor: PIC32
9 *
10 * Complier: MPLAB C32
11 * MPLAB IDE
12 * Company: Microchip Technology, Inc.
13 *
14 * Software License Agreement
15 * Microchip Audio Library – PIC32 Software.
16 * Copyright © 2008 Microchip Technology Inc. All rights reserved.
17 *
18 * Microchip licenses the Software for your use with Microchip microcontrollers
19 * and Microchip digital signal controllers pursuant to the terms of the
20 * Non-Exclusive Software License Agreement accompanying this Software.
21 *
22 * SOFTWARE AND DOCUMENTATION ARE PROVIDED “AS IS” WITHOUT WARRANTY
23 * OF ANY KIND, EITHER EXPRESS OR IMPLIED, INCLUDING WITHOUT LIMITATION,
24 * ANY WARRANTY OF MERCHANTABILITY, TITLE, NON-INFRINGEMENT AND FITNESS
25 * FOR A PARTICULAR PURPOSE.
26 * MICROCHIP AND ITS LICENSORS ASSUME NO RESPONSIBILITY FOR THE ACCURACY,
27 * RELIABILITY OR APPLICATION OF THE SOFTWARE AND DOCUMENTATION.
28 * IN NO EVENT SHALL MICROCHIP OR ITS LICENSORS BE LIABLE OR OBLIGATED
29 * UNDER CONTRACT, NEGLIGENCE, STRICT LIABILITY, CONTRIBUTION, BREACH
30 * OF WARRANTY, OR OTHER LEGAL EQUITABLE THEORY ANY DIRECT OR INDIRECT
31 * DAMAGES OR EXPENSES INCLUDING BUT NOT LIMITED TO ANY INCIDENTAL,
32 * SPECIAL, INDIRECT, PUNITIVE OR CONSEQUENTIAL DAMAGES, LOST PROFITS
33 * OR LOST DATA, COST OF PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY,
34 * SERVICES, OR ANY CLAIMS BY THIRD PARTIES (INCLUDING BUT NOT LIMITED
35 * TO ANY DEFENSE THEREOF), OR OTHER SIMILAR COSTS.
36 *
37 *$Id: $
38 ********************************************************************/
39 #ifndef _NAT_DP83640_H_
40  
41 #define _NAT_DP83640_H_
42  
43 typedef enum
44 {
45 /*
46 // basic registers, accross all registers: 0-1
47 PHY_REG_BMCON = 0,
48 PHY_REG_BMSTAT = 1,
49 // extended registers: 2-15
50 PHY_REG_PHYID1 = 2,
51 PHY_REG_PHYID2 = 3,
52 PHY_REG_ANAD = 4,
53 PHY_REG_ANLPAD = 5,
54 PHY_REG_ANLPADNP = 5,
55 PHY_REG_ANEXP = 6,
56 PHY_REG_ANNPTR = 7,
57 // PHY_REG_ANLPRNP = 8, not on 83640
58 */
59  
60 // specific vendor registers: 16-31
61 PHY_REG_STS = 0x10,
62 PHY_REG_MII_INT_CTRL = 0x11,
63 PHY_REG_MII_INT_STAT = 0x12,
64 PHY_REG_PAGESEL = 0x13, // extended register accessed by page selection register
65  
66 // extended registers - page 0
67 PHY_REG_FALSE_CS_COUNT = 0x14,
68 PHY_REG_RXERR_COUNT = 0x15,
69 PHY_REG_PCS_CONFIG = 0x16,
70 PHY_REG_RMII_BYPASS = 0x17,
71 PHY_REG_LED_CTRL = 0x18,
72 PHY_REG_PHY_CTRL = 0x19,
73 PHY_REG_10BT_CTRL = 0x1a,
74 PHY_REG_TEST_CTRL = 0x1b,
75 PHY_REG_ENERGY_CTRL = 0x1d,
76 PHY_REG_PCFCR = 0x1F,
77  
78 // test registers - page 1
79 PHY_REG_TEST_SD_CNFG = 0x1E,
80  
81 // link diagnostics registers - page 2
82 PHY_REG_LEN100_DET = 0x14,
83 PHY_REG_FREQ100 = 0x15,
84 PHY_REG_TDR_CTRL = 0x16,
85 PHY_REG_TDR_WIN = 0x17,
86 PHY_REG_TDR_PEAK = 0x18,
87 PHY_REG_TDR_THR = 0x19,
88 PHY_REG_VAR_CTRL = 0x1A,
89 PHY_REG_VAR_DAT = 0x1B,
90 PHY_REG_LQMR = 0x1D,
91 PHY_REG_LQDR = 0x1E,
92 PHY_REG_LQMR2 = 0x1F,
93  
94 // PTP 1588 base registers - page 4
95 PHY_REG_PTP_DTL = 0x14,
96 PHY_REG_PTP_TDR = 0x15,
97 PHY_REG_PTP_STS = 0x16,
98 PHY_REG_PTP_TSTS = 0x17,
99 PHY_REG_PTP_RATEL = 0x18,
100 PHY_REG_PTP_RATEH = 0x19,
101 PHY_REG_PTP_RDCKSUM = 0x1A,
102 PHY_REG_PTP_WRCKSUM = 0x1B,
103 PHY_REG_PTP_TXTS = 0x1C,
104 PHY_REG_PTP_RXTS = 0x1D,
105 PHY_REG_PTP_ESTS = 0x1E,
106 PHY_REG_PTP_EDATA = 0x1F,
107  
108 // PTP 1588 Configuration registers - Page 5
109 PHY_REG_PTP_TRIG = 0x14,
110 PHY_REG_PTP_EVNT = 0x15,
111 PHY_REG_PTP_TXCFG0 = 0x16,
112 PHY_REG_PTP_TXCFG1 = 0x17,
113 PHY_REG_PSF_CFG0 = 0x18,
114 PHY_REG_PTP_RXCFG0 = 0x19,
115 PHY_REG_PTP_RXCFG1 = 0x1A,
116 PHY_REG_PTP_RXCFG2 = 0x1B,
117 PHY_REG_PTP_RXCFG3 = 0x1C,
118 PHY_REG_PTP_RXCFG4 = 0x1D,
119 PHY_REG_PTP_TRDL = 0x1E,
120 PHY_REG_PTP_TRDH = 0x1F,
121  
122 // PTP 1588 Configuration Registers - Page 6
123 PHY_REG_PTP_COC = 0x14,
124 PHY_REG_PSF_CFG1 = 0x15,
125 PHY_REG_PSF_CFG2 = 0x16,
126 PHY_REG_PSF_CFG3 = 0x17,
127 PHY_REG_PSF_CFG4 = 0x18,
128 PHY_REG_PTP_SFDCFG = 0x19,
129 PHY_REG_PTP_INTCTL = 0x1A,
130 PHY_REG_PTP_CLKSRC = 0x1B,
131 PHY_REG_PTP_ETR = 0x1C,
132 PHY_REG_PTP_OFF = 0x1D,
133 PHY_REG_PTP_GPIOMON = 0x1E,
134 PHY_REG_PTP_RXHASH = 0x1F,
135  
136 //
137 //PHY_REGISTERS = 32 // total number of registers
138 }ePHY_VENDOR_REG;
139 // updated version of ePHY_REG
140  
141  
142 // vendor registers
143 //
144 typedef union {
145 struct {
146 unsigned ELAST_BUF:2;
147 unsigned RX_UNF_STS:1;
148 unsigned RX_OVF_STS:1;
149 unsigned RMII_REV1_0:1;
150 unsigned RMII_MODE:1;
151 unsigned SCMII_TX : 1;
152 unsigned SCMII_RX : 1;
153 unsigned PMD_LOOP : 1;
154 unsigned : 4;
155 unsigned DIS_TX_OPT : 1;
156 unsigned RMII_MASTER : 1;
157 unsigned :1;
158 };
159 struct {
160 unsigned short w:16;
161 };
162 } __RMIIBYPASSbits_t; // reg 0x17: PHY_REG_RMII_BYPASS
163 #define _RMIIBYPASS_RMII_MODE_MASK 0x0020
164 #define _RMIIBYPASS_RMII_REV1_0_MASK 0x0010
165 #define _RMIIBYPASS_RX_OVF_STS_MASK 0x0008
166 #define _RMIIBYPASS_RX_UNF_STS_MASK 0x0004
167 #define _RMIIBYPASS_ELAST_BUF_MASK 0x0003
168  
169  
170  
171  
172 typedef union {
173 struct {
174 unsigned PHYADDR:5;
175 unsigned LED_CFG:2;
176 unsigned BP_STRETCH:1;
177 unsigned BIST_START:1;
178 unsigned BIST_STATUS:1;
179 unsigned PSR_15:1;
180 unsigned BIST_FE:1;
181 unsigned PAUSE_TX:1;
182 unsigned PAUSE_RX:1;
183 unsigned FORCE_MDIX:1;
184 unsigned MDIX_EN:1;
185 };
186 struct {
187 unsigned short w:16;
188 };
189 } __PHYCTRLbits_t; // reg 0x19: PHY_REG_PHY_CTRL
190 #define _PHYCTRL_PHYADDR_MASK 0x001f
191 #define _PHYCTRL_LED_CFG_MASK 0x0060
192 #define _PHYCTRL_BP_STRETCH_MASK 0x0080
193 #define _PHYCTRL_BIST_START_MASK 0x0100
194 #define _PHYCTRL_BIST_STATUS_MASK 0x0200
195 #define _PHYCTRL_PSR_15_MASK 0x0400
196 #define _PHYCTRL_BIST_FE_MASK 0x0800
197 #define _PHYCTRL_PAUSE_TX_MASK 0x1000
198 #define _PHYCTRL_PAUSE_RX_MASK 0x2000
199 #define _PHYCTRL_FORCE_MDIX_MASK 0x4000
200 #define _PHYCTRL_MDIX_EN_MASK 0x8000
201  
202  
203  
204  
205  
206  
207 #endif // _NAT_DP83640C_H_
208  
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