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1 32 kaklik /*********************************************************************
2 *
3 * National DP83848 PHY definitions
4 *
5 *********************************************************************
6 * FileName: ETHPIC32ExtPhyDP83848.h
7 * Dependencies:
8 * Processor: PIC32
9 *
10 * Complier: MPLAB C32
11 * MPLAB IDE
12 * Company: Microchip Technology, Inc.
13 *
14 * Software License Agreement
15 * Microchip Audio Library – PIC32 Software.
16 * Copyright © 2008 Microchip Technology Inc. All rights reserved.
17 *
18 * Microchip licenses the Software for your use with Microchip microcontrollers
19 * and Microchip digital signal controllers pursuant to the terms of the
20 * Non-Exclusive Software License Agreement accompanying this Software.
21 *
22 * SOFTWARE AND DOCUMENTATION ARE PROVIDED “AS IS” WITHOUT WARRANTY
23 * OF ANY KIND, EITHER EXPRESS OR IMPLIED, INCLUDING WITHOUT LIMITATION,
24 * ANY WARRANTY OF MERCHANTABILITY, TITLE, NON-INFRINGEMENT AND FITNESS
25 * FOR A PARTICULAR PURPOSE.
26 * MICROCHIP AND ITS LICENSORS ASSUME NO RESPONSIBILITY FOR THE ACCURACY,
27 * RELIABILITY OR APPLICATION OF THE SOFTWARE AND DOCUMENTATION.
28 * IN NO EVENT SHALL MICROCHIP OR ITS LICENSORS BE LIABLE OR OBLIGATED
29 * UNDER CONTRACT, NEGLIGENCE, STRICT LIABILITY, CONTRIBUTION, BREACH
30 * OF WARRANTY, OR OTHER LEGAL EQUITABLE THEORY ANY DIRECT OR INDIRECT
31 * DAMAGES OR EXPENSES INCLUDING BUT NOT LIMITED TO ANY INCIDENTAL,
32 * SPECIAL, INDIRECT, PUNITIVE OR CONSEQUENTIAL DAMAGES, LOST PROFITS
33 * OR LOST DATA, COST OF PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY,
34 * SERVICES, OR ANY CLAIMS BY THIRD PARTIES (INCLUDING BUT NOT LIMITED
35 * TO ANY DEFENSE THEREOF), OR OTHER SIMILAR COSTS.
36 *
37 *$Id: $
38 ********************************************************************/
39 #ifndef _NAT_DP83848C_H_
40  
41 #define _NAT_DP83848C_H_
42  
43 typedef enum
44 {
45 /*
46 // basic registers, accross all registers: 0-1
47 PHY_REG_BMCON = 0,
48 PHY_REG_BMSTAT = 1,
49 // extended registers: 2-15
50 PHY_REG_PHYID1 = 2,
51 PHY_REG_PHYID2 = 3,
52 PHY_REG_ANAD = 4,
53 PHY_REG_ANLPAD = 5,
54 PHY_REG_ANLPADNP = 5,
55 PHY_REG_ANEXP = 6,
56 PHY_REG_ANNPTR = 7,
57 PHY_REG_ANLPRNP = 8,
58 */
59 // specific vendor registers: 16-31
60 PHY_REG_STAT = 0x10,
61 PHY_REG_MII_INT_CTRL = 0x11,
62 PHY_REG_MII_INT_STAT = 0x12,
63 PHY_REG_FALSE_CS_COUNT = 0x14,
64 PHY_REG_RXERR_COUNT = 0x15,
65 PHY_REG_PCS_CONFIG = 0x16,
66 PHY_REG_RMII_BYPASS = 0x17,
67 PHY_REG_LED_CTRL = 0x18,
68 PHY_REG_PHY_CTRL = 0x19,
69 PHY_REG_10BT_CTRL = 0x1a,
70 PHY_REG_TEST_CTRL = 0x1b,
71 PHY_REG_ENERGY_CTRL = 0x1d,
72  
73 //
74 //PHY_REGISTERS = 32 // total number of registers
75 }ePHY_VENDOR_REG;
76 // updated version of ePHY_REG
77  
78  
79 // vendor registers
80 //
81 typedef union {
82 struct {
83 unsigned ELAST_BUF:2;
84 unsigned RX_UNF_STS:1;
85 unsigned RX_OVF_STS:1;
86 unsigned RMII_REV1_0:1;
87 unsigned RMII_MODE:1;
88 unsigned :10;
89 };
90 struct {
91 unsigned short w:16;
92 };
93 } __RMIIBYPASSbits_t; // reg 0x17: PHY_REG_RMII_BYPASS
94 #define _RMIIBYPASS_RMII_MODE_MASK 0x0020
95 #define _RMIIBYPASS_RMII_REV1_0_MASK 0x0010
96 #define _RMIIBYPASS_RX_OVF_STS_MASK 0x0008
97 #define _RMIIBYPASS_RX_UNF_STS_MASK 0x0004
98 #define _RMIIBYPASS_ELAST_BUF_MASK 0x0003
99  
100  
101  
102  
103 typedef union {
104 struct {
105 unsigned PHYADDR:5;
106 unsigned LED_CFG:2;
107 unsigned BP_STRETCH:1;
108 unsigned BIST_START:1;
109 unsigned BIST_STATUS:1;
110 unsigned PSR_15:1;
111 unsigned BIST_FE:1;
112 unsigned PAUSE_TX:1;
113 unsigned PAUSE_RX:1;
114 unsigned FORCE_MDIX:1;
115 unsigned MDIX_EN:1;
116 };
117 struct {
118 unsigned short w:16;
119 };
120 } __PHYCTRLbits_t; // reg 0x19: PHY_REG_PHY_CTRL
121 #define _PHYCTRL_PHYADDR_MASK 0x001f
122 #define _PHYCTRL_LED_CFG_MASK 0x0060
123 #define _PHYCTRL_BP_STRETCH_MASK 0x0080
124 #define _PHYCTRL_BIST_START_MASK 0x0100
125 #define _PHYCTRL_BIST_STATUS_MASK 0x0200
126 #define _PHYCTRL_PSR_15_MASK 0x0400
127 #define _PHYCTRL_BIST_FE_MASK 0x0800
128 #define _PHYCTRL_PAUSE_TX_MASK 0x1000
129 #define _PHYCTRL_PAUSE_RX_MASK 0x2000
130 #define _PHYCTRL_FORCE_MDIX_MASK 0x4000
131 #define _PHYCTRL_MDIX_EN_MASK 0x8000
132  
133  
134  
135  
136  
137  
138 #endif // _NAT_DP83848C_H_
139  
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