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1 32 kaklik /*********************************************************************
2 *
3 * External Phy register definition file
4 *
5 *********************************************************************
6 * FileName: ETHPIC32ExtPhyRegs.h
7 * Dependencies:
8 * Processor: PIC32
9 *
10 * Complier: MPLAB C32
11 * MPLAB IDE
12 * Company: Microchip Technology, Inc.
13 *
14 * Software License Agreement
15 * Microchip Audio Library – PIC32 Software.
16 * Copyright © 2008 Microchip Technology Inc. All rights reserved.
17 *
18 * Microchip licenses the Software for your use with Microchip microcontrollers
19 * and Microchip digital signal controllers pursuant to the terms of the
20 * Non-Exclusive Software License Agreement accompanying this Software.
21 *
22 * SOFTWARE AND DOCUMENTATION ARE PROVIDED “AS IS” WITHOUT WARRANTY
23 * OF ANY KIND, EITHER EXPRESS OR IMPLIED, INCLUDING WITHOUT LIMITATION,
24 * ANY WARRANTY OF MERCHANTABILITY, TITLE, NON-INFRINGEMENT AND FITNESS
25 * FOR A PARTICULAR PURPOSE.
26 * MICROCHIP AND ITS LICENSORS ASSUME NO RESPONSIBILITY FOR THE ACCURACY,
27 * RELIABILITY OR APPLICATION OF THE SOFTWARE AND DOCUMENTATION.
28 * IN NO EVENT SHALL MICROCHIP OR ITS LICENSORS BE LIABLE OR OBLIGATED
29 * UNDER CONTRACT, NEGLIGENCE, STRICT LIABILITY, CONTRIBUTION, BREACH
30 * OF WARRANTY, OR OTHER LEGAL EQUITABLE THEORY ANY DIRECT OR INDIRECT
31 * DAMAGES OR EXPENSES INCLUDING BUT NOT LIMITED TO ANY INCIDENTAL,
32 * SPECIAL, INDIRECT, PUNITIVE OR CONSEQUENTIAL DAMAGES, LOST PROFITS
33 * OR LOST DATA, COST OF PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY,
34 * SERVICES, OR ANY CLAIMS BY THIRD PARTIES (INCLUDING BUT NOT LIMITED
35 * TO ANY DEFENSE THEREOF), OR OTHER SIMILAR COSTS.
36 *
37 *$Id: $
38 ********************************************************************/
39  
40  
41 #ifndef _ETH_PHY_REGS_H_
42 #define _ETH_PHY_REGS_H_
43  
44 // This file contains common definitions (accross all PHY's)
45 //
46  
47  
48 // MIIM registers access
49 //
50  
51 typedef enum
52 {
53 // basic registers, accross all registers: 0-1
54 PHY_REG_BMCON = 0,
55 PHY_REG_BMSTAT = 1,
56 // extended registers: 2-15
57 PHY_REG_PHYID1 = 2,
58 PHY_REG_PHYID2 = 3,
59 PHY_REG_ANAD = 4,
60 PHY_REG_ANLPAD = 5,
61 PHY_REG_ANLPADNP = 5,
62 PHY_REG_ANEXP = 6,
63 PHY_REG_ANNPTR = 7,
64 PHY_REG_ANLPRNP = 8,
65 /* ... */
66  
67 // specific vendor registers: 16-31
68 PHY_REG_VENDOR = 16, // this is updated by each specific PHY
69 //
70 //
71 //
72 PHY_REGISTERS = 32 // total number of registers
73 }ePHY_BASIC_REG;
74  
75 // MIIM registers definitions
76 //
77  
78 // basic registers
79 //
80  
81 typedef union {
82 struct {
83 unsigned :7;
84 unsigned COLTEST:1;
85 unsigned DUPLEX:1;
86 unsigned AN_RESTART:1;
87 unsigned ISOLATE:1;
88 unsigned PDWN:1;
89 unsigned AN_ENABLE:1;
90 unsigned SPEED:1;
91 unsigned LOOPBACK:1;
92 unsigned RESET:1;
93 };
94 struct {
95 unsigned short w:16;
96 };
97 } __BMCONbits_t; // reg 0: PHY_REG_BMCON
98 #define _BMCON_COLTEST_MASK 0x0080
99 #define _BMCON_DUPLEX_MASK 0x0100
100 #define _BMCON_AN_RESTART_MASK 0x0200
101 #define _BMCON_ISOLATE_MASK 0x0400
102 #define _BMCON_PDWN_MASK 0x0800
103 #define _BMCON_AN_ENABLE_MASK 0x1000
104 #define _BMCON_SPEED_MASK 0x2000
105 #define _BMCON_LOOPBACK_MASK 0x4000
106 #define _BMCON_RESET_MASK 0x8000
107  
108  
109  
110 typedef union {
111 struct {
112 unsigned EXTEND_ABLE:1;
113 unsigned JABBER_DET:1;
114 unsigned LINK_STAT:1;
115 unsigned AN_ABLE:1;
116 unsigned REM_FAULT:1;
117 unsigned AN_COMPLETE:1;
118 unsigned PREAMBLE_SUPPRESS:1;
119 unsigned :4;
120 unsigned BASE10T_HDX:1;
121 unsigned BASE10T_FDX:1;
122 unsigned BASE100TX_HDX:1;
123 unsigned BASE100TX_FDX:1;
124 unsigned BASE100T4:1;
125 };
126 struct {
127 unsigned short w:16;
128 };
129 } __BMSTATbits_t; // reg 1: PHY_REG_BMSTAT
130 #define _BMSTAT_EXTEND_ABLE_MASK 0x0001
131 #define _BMSTAT_JABBER_DET_MASK 0x0002
132 #define _BMSTAT_LINK_STAT_MASK 0x0004
133 #define _BMSTAT_AN_ABLE_MASK 0x0008
134 #define _BMSTAT_REM_FAULT_MASK 0x0010
135 #define _BMSTAT_AN_COMPLETE_MASK 0x0020
136 #define _BMSTAT_PREAMBLE_SUPPRESS_MASK 0x0040
137 #define _BMSTAT_BASE10T_HDX_MASK 0x0800
138 #define _BMSTAT_BASE10T_FDX_MASK 0x1000
139 #define _BMSTAT_BASE100TX_HDX_MASK 0x2000
140 #define _BMSTAT_BASE100TX_FDX_MASK 0x4000
141 #define _BMSTAT_BASE100T4_MASK 0x8000
142  
143  
144 #define _BMSTAT_NEGOTIATION_MASK (_BMSTAT_BASE10T_HDX_MASK|_BMSTAT_BASE10T_FDX_MASK| \
145 _BMSTAT_BASE100TX_HDX_MASK|_BMSTAT_BASE100TX_FDX_MASK|_BMSTAT_BASE100T4_MASK) // negotiation field mask
146 #define _BMSTAT_NEGOTIATION_POS 11 // negotiation field position
147 #define _BMSTAT_NEGOTIATION_LENGTH 5 // negotiation field length
148  
149  
150 // extended registers
151 //
152  
153 typedef union {
154 struct {
155 unsigned OUI_MSB:16;
156 };
157 struct {
158 unsigned short w:16;
159 };
160 } __PHYID1bits_t; // reg 2: PHY_REG_PHYID1
161  
162  
163  
164 typedef union {
165 struct {
166 unsigned MNF_REV:4;
167 unsigned MNF_MODEL:6;
168 unsigned OUI_LSB:6;
169 };
170 struct {
171 unsigned short w:16;
172 };
173 } __PHYID2bits_t; // reg 3: PHY_REG_PHYID2
174 #define _PHYID2_MNF_REV_MASK 0x000f
175 #define _PHYID2_MNF_MODEL_MASK 0x03f0
176 #define _PHYID2_OUI_LSB_MASK 0xfc00
177  
178  
179  
180 typedef union {
181 struct {
182 unsigned PROT_SEL:5;
183 unsigned BASE10T:1;
184 unsigned BASE10T_FDX:1;
185 unsigned BASE100TX:1;
186 unsigned BASE100TX_FDX:1;
187 unsigned BASE100T4:1;
188 unsigned PAUSE:1; // NOTE: the PAUSE fields coding for SMSC is reversed!
189 unsigned ASM_DIR:1; // typo in the data sheet?
190 unsigned :1;
191 unsigned REM_FAULT:1;
192 unsigned :1;
193 unsigned NP_ABLE:1;
194 };
195 struct {
196 unsigned short w:16;
197 };
198 } __ANADbits_t; // reg 4: PHY_REG_ANAD
199 #define _ANAD_PROT_SEL_MASK 0x001f
200 #define _ANAD_BASE10T_MASK 0x0020
201 #define _ANAD_BASE10T_FDX_MASK 0x0040
202 #define _ANAD_BASE100TX_MASK 0x0080
203 #define _ANAD_BASE100TX_FDX_MASK 0x0100
204 #define _ANAD_BASE100T4_MASK 0x0200
205 #define _ANAD_PAUSE_MASK 0x0400
206 #define _ANAD_ASM_DIR_MASK 0x0800
207 #define _ANAD_REM_FAULT_MASK 0x2000
208 #define _ANAD_NP_ABLE_MASK 0x8000
209  
210 #define _ANAD_NEGOTIATION_MASK (_ANAD_BASE10T_MASK|_ANAD_BASE10T_FDX_MASK|_ANAD_BASE100TX_MASK|_ANAD_BASE100TX_FDX_MASK| \
211 _ANAD_BASE100T4_MASK) // negotiation field mask
212 #define _ANAD_NEGOTIATION_POS 5 // negotiation field position
213 #define _ANAD_NEGOTIATION_LENGTH 5 // negotiation field length
214  
215  
216 typedef union {
217 struct {
218 unsigned PROT_SEL:5;
219 unsigned BASE10T:1;
220 unsigned BASE10T_FDX:1;
221 unsigned BASE100TX:1;
222 unsigned BASE100TX_FDX:1;
223 unsigned BASE100T4:1;
224 unsigned PAUSE:1;
225 unsigned ASM_DIR:1;
226 unsigned :1;
227 unsigned REM_FAULT:1;
228 unsigned ACK:1;
229 unsigned NP_ABLE:1;
230 };
231 struct {
232 unsigned short w:16;
233 };
234 } __ANLPADbits_t; // reg 5: PHY_REG_ANLPAD
235 #define _ANLPAD_PROT_SEL_MASK 0x001f
236 #define _ANLPAD_BASE10T_MASK 0x0020
237 #define _ANLPAD_BASE10T_FDX_MASK 0x0040
238 #define _ANLPAD_BASE100TX_MASK 0x0080
239 #define _ANLPAD_BASE100TX_FDX_MASK 0x0100
240 #define _ANLPAD_BASE100T4_MASK 0x0200
241 #define _ANLPAD_PAUSE_MASK 0x0400
242 #define _ANLPAD_ASM_DIR_MASK 0x0800
243 #define _ANLPAD_REM_FAULT_MASK 0x2000
244 #define _ANLPAD_ACK_MASK 0x4000
245 #define _ANLPAD_NP_ABLE_MASK 0x8000
246  
247 typedef union {
248 struct {
249 unsigned MESSAGE:11;
250 unsigned TOGGLE:1;
251 unsigned ACK2:1;
252 unsigned MSGP:1;
253 unsigned ACK:1;
254 unsigned NP:1;
255 };
256 struct {
257 unsigned short w:16;
258 };
259 } __ANLPADNPbits_t; // reg 5: PHY_REG_ANLPADNP: next page
260  
261 #define _ANLPADNP_MESSAGE_MASK 0x7ff
262 #define _ANLPADNP_TOGGLE_MASK 0x0800
263 #define _ANLPADNP_ACK2_MASK 0x1000
264 #define _ANLPADNP_MSGP_MASK 0x2000
265 #define _ANLPADNP_ACK_MASK 0x4000
266 #define _ANLPADNP_NP_MASK 0x8000
267  
268  
269  
270  
271 typedef union {
272 struct {
273 unsigned LP_AN_ABLE:1;
274 unsigned PAGE_RX:1;
275 unsigned NP_ABLE:1;
276 unsigned LP_NP_ABLE:1;
277 unsigned PDF:1;
278 unsigned :11;
279 };
280 struct {
281 unsigned short w:16;
282 };
283 } __ANEXPbits_t; // reg 6: PHY_REG_ANEXP
284 #define _ANEXP_LP_AN_ABLE_MASK 0x0001
285 #define _ANEXP_PAGE_RX_MASK 0x0002
286 #define _ANEXP_NP_ABLE_MASK 0x0004
287 #define _ANEXP_LP_NP_ABLE_MASK 0x0008
288 #define _ANEXP_PDF_MASK 0x0010
289  
290  
291  
292  
293 typedef union {
294 struct {
295 unsigned MESSAGE:11;
296 unsigned TOGGLE:1;
297 unsigned ACK2:1;
298 unsigned MSGP:1;
299 unsigned :1;
300 unsigned NP:1;
301 };
302 struct {
303 unsigned short w:16;
304 };
305 } __ANNPTRbits_t; // reg 7: PHY_REG_ANNPTR
306 #define _ANNPTR_MESSAGE_MASK 0x7ff
307 #define _ANNPTR_TOGGLE_MASK 0x0800
308 #define _ANNPTR_ACK2_MASK 0x1000
309 #define _ANNPTR_MSGP_MASK 0x2000
310 #define _ANNPTR_NP_MASK 0x8000
311  
312 typedef union {
313 struct {
314 unsigned MESSAGE:11;
315 unsigned TOGGLE:1;
316 unsigned ACK2:1;
317 unsigned MSGP:1;
318 unsigned ACK:1;
319 unsigned NP:1;
320 };
321 struct {
322 unsigned short w:16;
323 };
324 } __ANLPRNPbits_t; // reg 8: PHY_REG_ANLPRNP
325 #define _ANLPRNP_MESSAGE_MASK 0x7ff
326 #define _ANLPRNP_TOGGLE_MASK 0x0800
327 #define _ANLPRNP_ACK2_MASK 0x1000
328 #define _ANLPRNP_MSGP_MASK 0x2000
329 #define _ANLPRNP_ACK_MASK 0x4000
330 #define _ANLPRNP_NP_MASK 0x8000
331  
332  
333  
334  
335 #endif // _ETH_PHY_REGS_H_
336  
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