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1 32 kaklik /*********************************************************************
2 *
3 * SMSC LAN8700 definitions
4 *
5 *********************************************************************
6 * FileName: ETHPIC32ExtPhySMSC8700.h
7 * Dependencies:
8 * Processor: PIC32
9 *
10 * Complier: MPLAB C32
11 * MPLAB IDE
12 * Company: Microchip Technology, Inc.
13 *
14 * Software License Agreement
15 * Microchip Audio Library – PIC32 Software.
16 * Copyright © 2008 Microchip Technology Inc. All rights reserved.
17 *
18 * Microchip licenses the Software for your use with Microchip microcontrollers
19 * and Microchip digital signal controllers pursuant to the terms of the
20 * Non-Exclusive Software License Agreement accompanying this Software.
21 *
22 * SOFTWARE AND DOCUMENTATION ARE PROVIDED “AS IS” WITHOUT WARRANTY
23 * OF ANY KIND, EITHER EXPRESS OR IMPLIED, INCLUDING WITHOUT LIMITATION,
24 * ANY WARRANTY OF MERCHANTABILITY, TITLE, NON-INFRINGEMENT AND FITNESS
25 * FOR A PARTICULAR PURPOSE.
26 * MICROCHIP AND ITS LICENSORS ASSUME NO RESPONSIBILITY FOR THE ACCURACY,
27 * RELIABILITY OR APPLICATION OF THE SOFTWARE AND DOCUMENTATION.
28 * IN NO EVENT SHALL MICROCHIP OR ITS LICENSORS BE LIABLE OR OBLIGATED
29 * UNDER CONTRACT, NEGLIGENCE, STRICT LIABILITY, CONTRIBUTION, BREACH
30 * OF WARRANTY, OR OTHER LEGAL EQUITABLE THEORY ANY DIRECT OR INDIRECT
31 * DAMAGES OR EXPENSES INCLUDING BUT NOT LIMITED TO ANY INCIDENTAL,
32 * SPECIAL, INDIRECT, PUNITIVE OR CONSEQUENTIAL DAMAGES, LOST PROFITS
33 * OR LOST DATA, COST OF PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY,
34 * SERVICES, OR ANY CLAIMS BY THIRD PARTIES (INCLUDING BUT NOT LIMITED
35 * TO ANY DEFENSE THEREOF), OR OTHER SIMILAR COSTS.
36 *
37 ********************************************************************/
38 #ifndef _SMSC_8700_H_
39  
40 #define _SMSC_8700_H_
41  
42 typedef enum
43 {
44 /*
45 // basic registers, accross all registers: 0-1
46 PHY_REG_BMCON = 0,
47 PHY_REG_BMSTAT = 1,
48 // extended registers: 2-15
49 PHY_REG_PHYID1 = 2,
50 PHY_REG_PHYID2 = 3,
51 PHY_REG_ANAD = 4,
52 PHY_REG_ANLPAD = 5,
53 PHY_REG_ANLPADNP = 5,
54 PHY_REG_ANEXP = 6,
55 PHY_REG_ANNPTR = 7,
56 PHY_REG_ANLPRNP = 8,
57 */
58 // specific vendor registers: 16-31
59 PHY_REG_SILICON_REV = 16,
60 PHY_REG_MODE_CTRL = 17,
61 PHY_REG_SPECIAL_MODE = 18,
62 PHY_REG_SYMBOL_ERR_CNT = 26,
63 PHY_REG_SPECIAL_CTRL = 27,
64 PHY_REG_INT_SOURCE = 29,
65 PHY_REG_INT_MASK = 30,
66 PHY_REG_PHY_CTRL = 31,
67 //
68 //PHY_REGISTERS = 32 // total number of registers
69 }ePHY_VENDOR_REG;
70 // updated version of ePHY_REG
71  
72  
73 // vendor registers
74 //
75 typedef union {
76 struct {
77 unsigned :6;
78 unsigned SILICON_REV:4;
79 unsigned :6;
80 };
81 struct {
82 unsigned short w:16;
83 };
84 } __SILICONREVbits_t; // reg 16: PHY_REG_SILICON_REV
85 #define _SILICONREV_SILICON_REV_MASK 0x03c0
86  
87  
88 typedef union {
89 struct {
90 unsigned :1;
91 unsigned ENERGYON:1;
92 unsigned FORCE_GOOD_LINK:1;
93 unsigned PHYADPB:1;
94 unsigned :2;
95 unsigned ALTINT:1;
96 unsigned :2;
97 unsigned FAR_LOOPBACK:1;
98 unsigned MDPREPB:1;
99 unsigned LOWSQEN:1;
100 unsigned :1;
101 unsigned EDPWRDOWN:1;
102 unsigned :2;
103 };
104 struct {
105 unsigned short w:16;
106 };
107 } __MODECTRLbits_t; // reg 17: PHY_REG_MODE_CTRL
108 #define _MODECTRL_ENERGYON_MASK 0x0002
109 #define _MODECTRL_FORCE_GOOD_LINK_MASK 0x0004
110 #define _MODECTRL_PHYADPB_MASK 0x0008
111 #define _MODECTRL_ALTINT_MASK 0x0040
112 #define _MODECTRL_FAR_LOOPBACK_MASK 0x0200
113 #define _MODECTRL_MDPREPB_MASK 0x0400
114 #define _MODECTRL_LOWSQEN_MASK 0x0800
115 #define _MODECTRL_EDPWRDOWN_MASK 0x2000
116  
117  
118 typedef union {
119 struct {
120 unsigned PHYAD:5;
121 unsigned MODE:3;
122 unsigned :6;
123 unsigned MIIMODE:1;
124 unsigned :1;
125 };
126 struct {
127 unsigned short w:16;
128 };
129 } __SPECIALMODEbits_t; // reg 18: PHY_REG_SPECIAL_MODE
130 #define _SPECIALMODE_PHYAD_MASK 0x001f
131 #define _SPECIALMODE_MODE_MASK 0x00e0
132 #define _SPECIALMODE_MIIMODE_MASK 0x4000
133  
134  
135  
136  
137 typedef union {
138 struct {
139 unsigned Sym_Err_Cnt:16;
140 };
141 struct {
142 unsigned short w:16;
143 };
144 } __SYMBOLERRCNTbits_t; // reg 26: PHY_REG_SYMBOL_ERR_CNT
145  
146  
147 typedef union {
148 struct {
149 unsigned :4;
150 unsigned XPOL:1;
151 unsigned :6;
152 unsigned SQEOFF:1;
153 unsigned :1;
154 unsigned CH_SELECT:1;
155 unsigned :1;
156 unsigned AMDIXCTRL:1;
157 };
158 struct {
159 unsigned short w:16;
160 };
161 } __SPECIALCTRLbits_t; // reg 27: PHY_REG_SPECIAL_CTRL
162 #define _SPECIALCTRL_XPOL_MASK 0x0010
163 #define _SPECIALCTRL_SQEOFF_MASK 0x0800
164 #define _SPECIALCTRL_CH_SELECT_MASK 0x2000
165 #define _SPECIALCTRL_AMDIXCTRL_MASK 0x8000
166  
167  
168  
169  
170 typedef union {
171 struct {
172 unsigned :1;
173 unsigned INT1:1;
174 unsigned INT2:1;
175 unsigned INT3:1;
176 unsigned INT4:1;
177 unsigned INT5:1;
178 unsigned INT6:1;
179 unsigned INT7:1;
180 unsigned :8;
181 };
182 struct {
183 unsigned short w:16;
184 };
185 } __INTSOURCEbits_t; // reg 29: PHY_REG_INT_SOURCE
186  
187 typedef union {
188 struct {
189 unsigned :1;
190 unsigned INT1:1;
191 unsigned INT2:1;
192 unsigned INT3:1;
193 unsigned INT4:1;
194 unsigned INT5:1;
195 unsigned INT6:1;
196 unsigned INT7:1;
197 unsigned :8;
198 };
199 struct {
200 unsigned short w:16;
201 };
202 } __INTMASKbits_t; // reg 30: PHY_REG_INT_MASK
203  
204  
205 typedef union {
206 struct {
207 unsigned SCRMBL_DISBL:1;
208 unsigned :1;
209 unsigned SPEED:3; // 1: 10MbpsHD; 5:10MbpsFD; 2: 100MbpsHD; 6: 100MbpsFD;
210 unsigned :1;
211 unsigned ENABLE_4B5B:1;
212 unsigned GPO:3;
213 unsigned :2;
214 unsigned AUTODONE:1;
215 unsigned :3;
216 };
217 struct {
218 unsigned short w:16;
219 };
220 } __PHYCTRLbits_t; // reg 31: PHY_REG_PHY_CTRL
221 #define _PHYCTRL_SCRMBL_DISBL_MASK 0x0001
222 #define _PHYCTRL_SPEED_MASK 0x001c
223 #define _PHYCTRL_SPEED_FDUPLX_MASK 0x0010
224 #define _PHYCTRL_SPEED_100_10_MASK 0x000c
225 #define _PHYCTRL_SPEED_100_MASK 0x0008
226 #define _PHYCTRL_ENABLE_4B5B_MASK 0x0040
227 #define _PHYCTRL_GPO_MASK 0x0380
228 #define _PHYCTRL_AUTODONE_MASK 0x1000
229  
230  
231  
232 #endif // _SMSC_8700_H_
233  
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