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1 32 kaklik /*********************************************************************
2 *
3 * SMSC LAN8720 definitions
4 *
5 *********************************************************************
6 * FileName: ETHPIC32ExtPhySMSC8720.h
7 * Dependencies:
8 * Processor: PIC32
9 *
10 * Complier: MPLAB C32
11 * MPLAB IDE
12 * Company: Microchip Technology, Inc.
13 *
14 * Software License Agreement
15 * Microchip Audio Library – PIC32 Software.
16 * Copyright © 2008 Microchip Technology Inc. All rights reserved.
17 *
18 * Microchip licenses the Software for your use with Microchip microcontrollers
19 * and Microchip digital signal controllers pursuant to the terms of the
20 * Non-Exclusive Software License Agreement accompanying this Software.
21 *
22 * SOFTWARE AND DOCUMENTATION ARE PROVIDED “AS IS” WITHOUT WARRANTY
23 * OF ANY KIND, EITHER EXPRESS OR IMPLIED, INCLUDING WITHOUT LIMITATION,
24 * ANY WARRANTY OF MERCHANTABILITY, TITLE, NON-INFRINGEMENT AND FITNESS
25 * FOR A PARTICULAR PURPOSE.
26 * MICROCHIP AND ITS LICENSORS ASSUME NO RESPONSIBILITY FOR THE ACCURACY,
27 * RELIABILITY OR APPLICATION OF THE SOFTWARE AND DOCUMENTATION.
28 * IN NO EVENT SHALL MICROCHIP OR ITS LICENSORS BE LIABLE OR OBLIGATED
29 * UNDER CONTRACT, NEGLIGENCE, STRICT LIABILITY, CONTRIBUTION, BREACH
30 * OF WARRANTY, OR OTHER LEGAL EQUITABLE THEORY ANY DIRECT OR INDIRECT
31 * DAMAGES OR EXPENSES INCLUDING BUT NOT LIMITED TO ANY INCIDENTAL,
32 * SPECIAL, INDIRECT, PUNITIVE OR CONSEQUENTIAL DAMAGES, LOST PROFITS
33 * OR LOST DATA, COST OF PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY,
34 * SERVICES, OR ANY CLAIMS BY THIRD PARTIES (INCLUDING BUT NOT LIMITED
35 * TO ANY DEFENSE THEREOF), OR OTHER SIMILAR COSTS.
36 *
37 ********************************************************************/
38 #ifndef _SMSC_8720_H_
39  
40 #define _SMSC_8720_H_
41  
42 typedef enum
43 {
44 /*
45 // basic registers, accross all registers: 0-1
46 PHY_REG_BMCON = 0,
47 PHY_REG_BMSTAT = 1,
48 // extended registers: 2-15
49 PHY_REG_PHYID1 = 2,
50 PHY_REG_PHYID2 = 3,
51 PHY_REG_ANAD = 4,
52 PHY_REG_ANLPAD = 5,
53 PHY_REG_ANLPADNP = 5,
54 PHY_REG_ANEXP = 6,
55 // PHY_REG_ANNPTR = 7, not defined for SMSC 8720
56 // PHY_REG_ANLPRNP = 8, not defined for SMSC 8720
57 */
58 // specific vendor registers: 16-31
59 PHY_REG_MODE_CTRL = 17,
60 PHY_REG_SPECIAL_MODE = 18,
61 PHY_REG_SYMBOL_ERR_CNT = 26,
62 PHY_REG_SPECIAL_CTRL = 27,
63 PHY_REG_INT_SOURCE = 29,
64 PHY_REG_INT_MASK = 30,
65 PHY_REG_PHY_CTRL = 31,
66 //
67 //PHY_REGISTERS = 32 // total number of registers
68 }ePHY_VENDOR_REG;
69 // updated version of ePHY_REG
70  
71  
72 // vendor registers
73 //
74  
75 typedef union {
76 struct {
77 unsigned :1;
78 unsigned ENERGYON:1;
79 unsigned :4;
80 unsigned ALTINT:1;
81 unsigned :2;
82 unsigned FAR_LOOPBACK:1;
83 unsigned :3;
84 unsigned EDPWRDOWN:1;
85 unsigned :2;
86 };
87 struct {
88 unsigned short w:16;
89 };
90 } __MODECTRLbits_t; // reg 17: PHY_REG_MODE_CTRL
91 #define _MODECTRL_ENERGYON_MASK 0x0002
92 #define _MODECTRL_ALTINT_MASK 0x0040
93 #define _MODECTRL_FAR_LOOPBACK_MASK 0x0200
94 #define _MODECTRL_EDPWRDOWN_MASK 0x2000
95  
96  
97 typedef union {
98 struct {
99 unsigned PHYAD:5;
100 unsigned MODE:3;
101 unsigned :6;
102 unsigned :1;
103 unsigned :1;
104 };
105 struct {
106 unsigned short w:16;
107 };
108 } __SPECIALMODEbits_t; // reg 18: PHY_REG_SPECIAL_MODE
109 #define _SPECIALMODE_PHYAD_MASK 0x001f
110 #define _SPECIALMODE_MODE_MASK 0x00e0
111  
112  
113  
114  
115 typedef union {
116 struct {
117 unsigned Sym_Err_Cnt:16;
118 };
119 struct {
120 unsigned short w:16;
121 };
122 } __SYMBOLERRCNTbits_t; // reg 26: PHY_REG_SYMBOL_ERR_CNT
123  
124  
125 typedef union {
126 struct {
127 unsigned :4;
128 unsigned XPOL:1;
129 unsigned :6;
130 unsigned :2;
131 unsigned CH_SELECT:1;
132 unsigned :1;
133 unsigned AMDIXCTRL:1;
134 };
135 struct {
136 unsigned short w:16;
137 };
138 } __SPECIALCTRLbits_t; // reg 27: PHY_REG_SPECIAL_CTRL
139 #define _SPECIALCTRL_XPOL_MASK 0x0010
140 #define _SPECIALCTRL_CH_SELECT_MASK 0x2000
141 #define _SPECIALCTRL_AMDIXCTRL_MASK 0x8000
142  
143  
144  
145  
146 typedef union {
147 struct {
148 unsigned :1;
149 unsigned INT1:1;
150 unsigned INT2:1;
151 unsigned INT3:1;
152 unsigned INT4:1;
153 unsigned INT5:1;
154 unsigned INT6:1;
155 unsigned INT7:1;
156 unsigned :8;
157 };
158 struct {
159 unsigned short w:16;
160 };
161 } __INTSOURCEbits_t; // reg 29: PHY_REG_INT_SOURCE
162  
163 typedef union {
164 struct {
165 unsigned :1;
166 unsigned INT1:1;
167 unsigned INT2:1;
168 unsigned INT3:1;
169 unsigned INT4:1;
170 unsigned INT5:1;
171 unsigned INT6:1;
172 unsigned INT7:1;
173 unsigned :8;
174 };
175 struct {
176 unsigned short w:16;
177 };
178 } __INTMASKbits_t; // reg 30: PHY_REG_INT_MASK
179  
180  
181 typedef union {
182 struct {
183 unsigned :2;
184 unsigned SPEED:3; // 1: 10MbpsHD; 5:10MbpsFD; 2: 100MbpsHD; 6: 100MbpsFD;
185 unsigned :1;
186 unsigned :1; // ENABLE_4B5B: should be always set
187 unsigned :3; // GPO: N/A
188 unsigned :2;
189 unsigned AUTODONE:1;
190 unsigned :3;
191 };
192 struct {
193 unsigned short w:16;
194 };
195 } __PHYCTRLbits_t; // reg 31: PHY_REG_PHY_CTRL
196 #define _PHYCTRL_SPEED_MASK 0x001c
197 #define _PHYCTRL_SPEED_FDUPLX_MASK 0x0010
198 #define _PHYCTRL_SPEED_100_10_MASK 0x000c
199 #define _PHYCTRL_SPEED_100_MASK 0x0008
200 #define _PHYCTRL_AUTODONE_MASK 0x1000
201  
202  
203  
204 #endif // _SMSC_8720_H_
205  
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