| Line No. | Rev | Author | Line |
|---|---|---|---|
| 1 | 32 | kaklik | /********************************************************************* |
| 2 | * |
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| 3 | * Hardware specific definitions |
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| 4 | * |
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| 5 | ********************************************************************* |
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| 6 | * FileName: HardwareProfile.h |
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| 7 | * Dependencies: None |
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| 8 | * Processor: PIC18, PIC24F, PIC24H, dsPIC30F, dsPIC33F, PIC32 |
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| 9 | * Compiler: Microchip C32 v1.10 or higher |
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| 10 | * Microchip C30 v3.12 or higher |
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| 11 | * Microchip C18 v3.34 or higher |
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| 12 | * HI-TECH PICC-18 PRO 9.63PL2 or higher |
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| 13 | * Company: Microchip Technology, Inc. |
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| 14 | * |
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| 15 | * Software License Agreement |
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| 16 | * |
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| 17 | * Copyright (C) 2002-2010 Microchip Technology Inc. All rights |
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| 18 | * reserved. |
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| 19 | * |
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| 20 | * Microchip licenses to you the right to use, modify, copy, and |
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| 21 | * distribute: |
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| 22 | * (i) the Software when embedded on a Microchip microcontroller or |
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| 23 | * digital signal controller product ("Device") which is |
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| 24 | * integrated into Licensee's product; or |
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| 25 | * (ii) ONLY the Software driver source files ENC28J60.c, ENC28J60.h, |
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| 26 | * ENCX24J600.c and ENCX24J600.h ported to a non-Microchip device |
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| 27 | * used in conjunction with a Microchip ethernet controller for |
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| 28 | * the sole purpose of interfacing with the ethernet controller. |
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| 29 | * |
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| 30 | * You should refer to the license agreement accompanying this |
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| 31 | * Software for additional information regarding your rights and |
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| 32 | * obligations. |
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| 33 | * |
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| 34 | * THE SOFTWARE AND DOCUMENTATION ARE PROVIDED "AS IS" WITHOUT |
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| 35 | * WARRANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED, INCLUDING WITHOUT |
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| 36 | * LIMITATION, ANY WARRANTY OF MERCHANTABILITY, FITNESS FOR A |
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| 37 | * PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT SHALL |
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| 38 | * MICROCHIP BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR |
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| 39 | * CONSEQUENTIAL DAMAGES, LOST PROFITS OR LOST DATA, COST OF |
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| 40 | * PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS |
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| 41 | * BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE |
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| 42 | * THEREOF), ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER |
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| 43 | * SIMILAR COSTS, WHETHER ASSERTED ON THE BASIS OF CONTRACT, TORT |
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| 44 | * (INCLUDING NEGLIGENCE), BREACH OF WARRANTY, OR OTHERWISE. |
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| 45 | * |
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| 46 | * |
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| 47 | * Author Date Comment |
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| 48 | *~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 49 | * Howard Schlunder 10/03/06 Original, copied from Compiler.h |
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| 50 | * Ken Hesky 01/xx/10 Added MRF24WB0M-specific features |
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| 51 | ********************************************************************/ |
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| 52 | #ifndef __HARDWARE_PROFILE_H |
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| 53 | #define __HARDWARE_PROFILE_H |
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| 54 | |||
| 55 | #include "GenericTypeDefs.h" |
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| 56 | #include "Compiler.h" |
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| 57 | |||
| 58 | // Choose which hardware profile to compile for here. See |
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| 59 | // the hardware profiles below for meaning of various options. |
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| 60 | //#define PICDEMNET2 |
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| 61 | //#define PIC18_EXPLORER |
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| 62 | //#define HPC_EXPLORER |
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| 63 | //#define PIC24FJ64GA004_PIM // Explorer 16, but with the PIC24FJ64GA004 PIM module, which has significantly differnt pin mappings |
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| 64 | //#define EXPLORER_16 // PIC24FJ128GA010, PIC24HJ256GP610, dsPIC33FJ256GP710, PIC32MX360F512L, PIC32MX460F512L, PIC32MX795F512L, etc. PIMs |
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| 65 | //#define DSPICDEM11 |
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| 66 | %PIC32_GP_SK_DM320001%#define PIC32_GP_SK_DM320001 // PIC32MX360F512L General Purpose Starter Kit (for purposes of TCP/IP, defining this macro is the same as defining PIC32_USB_DM320003_1 or PIC32_USB_SK_DM320003_2) |
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| 67 | %PIC32_USB_DM320003_1%#define PIC32_USB_DM320003_1 // PIC32MX460F512L USB Starter Board (for purposes of TCP/IP, defining this macro is the same as defining PIC32_GP_SK_DM320001 or PIC32_USB_SK_DM320003_2) |
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| 68 | %PIC32_USB_SK_DM320003_2%#define PIC32_USB_SK_DM320003_2 // PIC32MX795F512L USB Starter Kit II (for purposes of TCP/IP, defining this macro is the same as defining PIC32_GP_SK_DM320001 or PIC32_USB_DM320003_1) |
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| 69 | %PIC32_ENET_SK_DM320004%#define PIC32_ENET_SK_DM320004 // PIC32MX795F512L Ethernet Starter Kit board with embedded Ethernet controller |
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| 70 | //#define PIC24FJ256DA210_DEV_BOARD // PIC24FJ256DA210 Development Board (Graphics) |
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| 71 | //#define YOUR_BOARD |
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| 72 | |||
| 73 | // If no hardware profiles are defined, assume that we are using |
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| 74 | // a Microchip demo board and try to auto-select the correct profile |
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| 75 | // based on processor selected in MPLAB |
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| 76 | #if !defined(PICDEMNET2) && !defined(PIC18_EXPLORER) && !defined(HPC_EXPLORER) && !defined(EXPLORER_16) && !defined(PIC24FJ64GA004_PIM) && !defined(DSPICDEM11) && !defined(PICDEMNET2) && !defined(INTERNET_RADIO) && !defined(YOUR_BOARD) && !defined(__PIC24FJ128GA006__) && !defined(PIC32_GP_SK_DM320001) && !defined(PIC32_USB_DM320003_1) && !defined(PIC32_USB_SK_DM320003_2) && !defined(PIC32_ENET_SK_DM320004) && !defined(PIC24FJ256DA210_DEV_BOARD) |
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| 77 | #if defined(__18F97J60) || defined(_18F97J60) |
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| 78 | #define PICDEMNET2 |
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| 79 | #elif defined(__18F67J60) || defined(_18F67J60) |
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| 80 | #define INTERNET_RADIO |
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| 81 | #elif defined(__18F8722) || defined(__18F87J10) || defined(_18F8722) || defined(_18F87J10) || defined(__18F87J11) || defined(_18F87J11)|| defined(__18F87J50) || defined(_18F87J50) |
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| 82 | #define PIC18_EXPLORER |
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| 83 | //#define HPC_EXPLORER |
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| 84 | #elif defined(__PIC24FJ64GA004__) |
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| 85 | #define PIC24FJ64GA004_PIM |
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| 86 | #elif defined(__PIC24FJ256DA210__) |
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| 87 | #define PIC24FJ256DA210_DEV_BOARD |
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| 88 | #elif defined(__PIC24F__) || defined(__PIC24H__) || defined(__dsPIC33F__) || defined(__PIC32MX__) |
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| 89 | #define EXPLORER_16 |
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| 90 | #elif defined(__dsPIC30F__) |
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| 91 | #define DSPICDEM11 |
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| 92 | #endif |
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| 93 | #endif |
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| 94 | |||
| 95 | // Set configuration fuses (but only once) |
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| 96 | #if defined(THIS_IS_STACK_APPLICATION) |
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| 97 | #if defined(__18CXX) |
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| 98 | #if defined(__EXTENDED18__) |
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| 99 | #pragma config XINST=ON |
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| 100 | #elif !defined(HI_TECH_C) |
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| 101 | #pragma config XINST=OFF |
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| 102 | #endif |
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| 103 | |||
| 104 | #if defined(__18F8722) && !defined(HI_TECH_C) |
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| 105 | // PICDEM HPC Explorer or PIC18 Explorer board |
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| 106 | #pragma config OSC=HSPLL, FCMEN=OFF, IESO=OFF, PWRT=OFF, WDT=OFF, LVP=OFF |
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| 107 | #elif defined(_18F8722) // HI-TECH PICC-18 compiler |
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| 108 | // PICDEM HPC Explorer or PIC18 Explorer board with HI-TECH PICC-18 compiler |
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| 109 | __CONFIG(1, HSPLL); |
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| 110 | __CONFIG(2, WDTDIS); |
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| 111 | __CONFIG(3, MCLREN); |
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| 112 | __CONFIG(4, XINSTDIS & LVPDIS); |
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| 113 | #elif defined(__18F87J10) && !defined(HI_TECH_C) |
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| 114 | // PICDEM HPC Explorer or PIC18 Explorer board |
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| 115 | #pragma config WDTEN=OFF, FOSC2=ON, FOSC=HSPLL |
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| 116 | #elif defined(__18F87J11) && !defined(HI_TECH_C) |
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| 117 | // PICDEM HPC Explorer or PIC18 Explorer board |
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| 118 | #pragma config WDTEN=OFF, FOSC=HSPLL |
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| 119 | #elif defined(__18F87J50) && !defined(HI_TECH_C) |
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| 120 | // PICDEM HPC Explorer or PIC18 Explorer board |
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| 121 | #pragma config WDTEN=OFF, FOSC=HSPLL, PLLDIV=3, CPUDIV=OSC1 |
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| 122 | #elif (defined(__18F97J60) || defined(__18F96J65) || defined(__18F96J60) || defined(__18F87J60) || defined(__18F86J65) || defined(__18F86J60) || defined(__18F67J60) || defined(__18F66J65) || defined(__18F66J60)) && !defined(HI_TECH_C) |
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| 123 | // PICDEM.net 2 or any other PIC18F97J60 family device |
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| 124 | #pragma config WDT=OFF, FOSC2=ON, FOSC=HSPLL, ETHLED=ON |
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| 125 | #elif defined(_18F97J60) || defined(_18F96J65) || defined(_18F96J60) || defined(_18F87J60) || defined(_18F86J65) || defined(_18F86J60) || defined(_18F67J60) || defined(_18F66J65) || defined(_18F66J60) |
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| 126 | // PICDEM.net 2 board with HI-TECH PICC-18 compiler |
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| 127 | __CONFIG(1, WDTDIS & XINSTDIS); |
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| 128 | __CONFIG(2, HSPLL); |
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| 129 | __CONFIG(3, ETHLEDEN); |
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| 130 | #elif defined(__18F4620) && !defined(HI_TECH_C) |
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| 131 | #pragma config OSC=HSPLL, WDT=OFF, MCLRE=ON, PBADEN=OFF, LVP=OFF |
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| 132 | #endif |
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| 133 | #elif defined(__PIC24FJ256DA210__) || defined(__PIC24FJ256GB210__) |
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| 134 | // PIC24FJ256DA210 Development Board (Graphics) or PIC24FJ256GB210 PIM on Explorer 16 |
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| 135 | _CONFIG3(ALTPMP_ALPMPDIS & SOSCSEL_EC); // PMP in default location, disable Timer1 oscillator so that RC13 can be used as a GPIO |
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| 136 | _CONFIG2(FNOSC_PRIPLL & POSCMOD_XT & IOL1WAY_OFF & PLL96MHZ_ON & PLLDIV_DIV2); // Primary XT OSC with 96MHz PLL (8MHz crystal input), IOLOCK can be set and cleared |
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| 137 | _CONFIG1(FWDTEN_OFF & ICS_PGx2 & JTAGEN_OFF & ALTVREF_ALTVREDIS); // Watchdog timer off, ICD debugging on PGEC2/PGED2 pins, JTAG off, AVREF and CVREF in default locations |
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| 138 | #elif defined(__PIC24FJ256GB110__) |
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| 139 | // PIC24FJ256GB110 PIM on Explorer 16 |
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| 140 | _CONFIG2(PLLDIV_DIV2 & PLL_96MHZ_ON & FNOSC_PRIPLL & IOL1WAY_OFF & POSCMOD_XT); // Primary XT OSC with 96MHz PLL (8MHz crystal input), IOLOCK can be set and cleared |
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| 141 | _CONFIG1(JTAGEN_OFF & ICS_PGx2 & FWDTEN_OFF); // Watchdog timer off, ICD debugging on PGEC2/PGED2 pins, JTAG off |
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| 142 | #elif defined(__PIC24FJ256GA110__) |
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| 143 | // PIC24FJ256GA110 PIM on Explorer 16 |
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| 144 | _CONFIG2(FNOSC_PRIPLL & IOL1WAY_OFF & POSCMOD_XT); // Primary XT OSC with PLL, IOLOCK can be set and cleared |
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| 145 | _CONFIG1(JTAGEN_OFF & ICS_PGx2 & FWDTEN_OFF); // Watchdog timer off, ICD debugging on PGEC2/PGED2 pins, JTAG off |
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| 146 | #elif defined(__PIC24F__) |
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| 147 | // Explorer 16 board |
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| 148 | _CONFIG2(FNOSC_PRIPLL & POSCMOD_XT) // Primary XT OSC with 4x PLL |
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| 149 | _CONFIG1(JTAGEN_OFF & FWDTEN_OFF) // JTAG off, watchdog timer off |
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| 150 | #elif defined(__dsPIC33F__) || defined(__PIC24H__) |
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| 151 | // Explorer 16 board |
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| 152 | _FOSCSEL(FNOSC_PRIPLL) // PLL enabled |
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| 153 | _FOSC(OSCIOFNC_OFF & POSCMD_XT) // XT Osc |
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| 154 | _FWDT(FWDTEN_OFF) // Disable Watchdog timer |
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| 155 | // JTAG should be disabled as well |
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| 156 | #elif defined(__dsPIC30F__) |
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| 157 | // dsPICDEM 1.1 board |
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| 158 | _FOSC(XT_PLL16) // XT Osc + 16X PLL |
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| 159 | _FWDT(WDT_OFF) // Disable Watchdog timer |
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| 160 | _FBORPOR(MCLR_EN & PBOR_OFF & PWRT_OFF) |
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| 161 | #elif defined(__PIC32MX__) |
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| 162 | #pragma config FPLLODIV = DIV_1, FPLLMUL = MUL_20, FPLLIDIV = DIV_2, FWDTEN = OFF, FPBDIV = DIV_1, POSCMOD = XT, FNOSC = PRIPLL, CP = OFF |
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| 163 | #if defined(PIC32_ENET_SK_DM320004) |
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| 164 | #pragma config FMIIEN = OFF, FETHIO = OFF // external PHY in RMII/alternate configuration |
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| 165 | #endif |
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| 166 | #endif |
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| 167 | #endif // Prevent more than one set of config fuse definitions |
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| 168 | |||
| 169 | // Clock frequency value. |
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| 170 | // This value is used to calculate Tick Counter value |
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| 171 | #if defined(__18CXX) |
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| 172 | // All PIC18 processors |
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| 173 | #if defined(PICDEMNET2) || defined(INTERNET_RADIO) |
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| 174 | #define GetSystemClock() (41666667ul) // Hz |
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| 175 | #define GetInstructionClock() (GetSystemClock()/4) |
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| 176 | #define GetPeripheralClock() GetInstructionClock() |
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| 177 | #elif defined(__18F87J50) || defined(_18F87J50) |
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| 178 | #define GetSystemClock() (48000000ul) // Hz |
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| 179 | #define GetInstructionClock() (GetSystemClock()/4) |
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| 180 | #define GetPeripheralClock() GetInstructionClock() |
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| 181 | #else |
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| 182 | #define GetSystemClock() (40000000ul) // Hz |
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| 183 | #define GetInstructionClock() (GetSystemClock()/4) |
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| 184 | #define GetPeripheralClock() GetInstructionClock() |
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| 185 | #endif |
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| 186 | #elif defined(__PIC24F__) || defined(__PIC24FK__) |
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| 187 | // PIC24F processor |
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| 188 | #define GetSystemClock() (32000000ul) // Hz |
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| 189 | #define GetInstructionClock() (GetSystemClock()/2) |
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| 190 | #define GetPeripheralClock() GetInstructionClock() |
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| 191 | #elif defined(__PIC24H__) |
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| 192 | // PIC24H processor |
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| 193 | #define GetSystemClock() (80000000ul) // Hz |
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| 194 | #define GetInstructionClock() (GetSystemClock()/2) |
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| 195 | #define GetPeripheralClock() GetInstructionClock() |
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| 196 | #elif defined(__dsPIC33F__) |
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| 197 | // dsPIC33F processor |
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| 198 | #define GetSystemClock() (80000000ul) // Hz |
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| 199 | #define GetInstructionClock() (GetSystemClock()/2) |
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| 200 | #define GetPeripheralClock() GetInstructionClock() |
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| 201 | #elif defined(__dsPIC30F__) |
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| 202 | // dsPIC30F processor |
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| 203 | #define GetSystemClock() (117920000ul) // Hz |
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| 204 | #define GetInstructionClock() (GetSystemClock()/4) |
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| 205 | #define GetPeripheralClock() GetInstructionClock() |
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| 206 | #elif defined(__PIC32MX__) |
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| 207 | // PIC32MX processor |
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| 208 | #define GetSystemClock() (80000000ul) // Hz |
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| 209 | #define GetInstructionClock() (GetSystemClock()/1) |
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| 210 | #define GetPeripheralClock() (GetInstructionClock()/1) // Set your divider according to your Peripheral Bus Frequency configuration fuse setting |
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| 211 | #endif |
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| 212 | |||
| 213 | // Hardware mappings |
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| 214 | #if defined(PIC18_EXPLORER) && !defined(HI_TECH_C) |
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| 215 | // PIC18 Explorer + Fast 100Mbps Ethernet PICtail Plus or Ethernet PICtail |
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| 216 | // I/O pins |
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| 217 | #define LED0_TRIS (TRISDbits.TRISD0) |
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| 218 | #define LED0_IO (LATDbits.LATD0) |
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| 219 | #define LED1_TRIS (TRISDbits.TRISD1) |
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| 220 | #define LED1_IO (LATDbits.LATD1) |
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| 221 | #define LED2_TRIS (TRISDbits.TRISD2) |
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| 222 | #define LED2_IO (LATDbits.LATD2) |
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| 223 | #define LED3_TRIS (TRISDbits.TRISD3) |
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| 224 | #define LED3_IO (LATDbits.LATD3) |
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| 225 | #define LED4_TRIS (TRISDbits.TRISD4) |
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| 226 | #define LED4_IO (LATDbits.LATD4) |
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| 227 | #define LED5_TRIS (TRISDbits.TRISD5) |
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| 228 | #define LED5_IO (LATDbits.LATD5) |
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| 229 | #define LED6_TRIS (TRISDbits.TRISD6) |
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| 230 | #define LED6_IO (LATDbits.LATD6) |
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| 231 | #define LED7_TRIS (TRISDbits.TRISD7) |
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| 232 | #define LED7_IO (LATDbits.LATD7) |
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| 233 | #define LED_GET() (LATD) |
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| 234 | #define LED_PUT(a) (LATD = (a)) |
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| 235 | |||
| 236 | #define BUTTON0_TRIS (TRISAbits.TRISA5) |
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| 237 | #define BUTTON0_IO (PORTAbits.RA5) |
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| 238 | #define BUTTON1_TRIS (TRISBbits.TRISB0) |
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| 239 | #define BUTTON1_IO (PORTBbits.RB0) |
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| 240 | #define BUTTON2_TRIS (PRODL) // No Button2 on this board |
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| 241 | #define BUTTON2_IO (1u) |
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| 242 | #define BUTTON3_TRIS (PRODL) // No Button3 on this board |
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| 243 | #define BUTTON3_IO (1u) |
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| 244 | |||
| 245 | |||
| 246 | %ENC100_COMMENTS% // ENC424J600/624J600 Fast 100Mbps Ethernet PICtail Plus defines |
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| 247 | %ENC100_COMMENTS% #define ENC100_INTERFACE_MODE 0 // Uncomment this line to use the ENC424J600/624J600 Ethernet controller (SPI mode) or comment it out to use some other network controller |
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| 248 | %ENC100_COMMENTS% |
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| 249 | %ENC100_COMMENTS% // ENC100_MDIX, ENC100_POR, and ENC100_INT are all optional. Simply leave |
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| 250 | %ENC100_COMMENTS% // them commented out if you don't have such a hardware feature on your |
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| 251 | %ENC100_COMMENTS% // board. |
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| 252 | %ENC100_COMMENTS% #define ENC100_MDIX_TRIS (TRISBbits.TRISB4) |
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| 253 | %ENC100_COMMENTS% #define ENC100_MDIX_IO (LATBbits.LATB4) |
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| 254 | %ENC100_COMMENTS%// #define ENC100_POR_TRIS (TRISBbits.TRISB5) |
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| 255 | %ENC100_COMMENTS%// #define ENC100_POR_IO (LATBbits.LATB5) |
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| 256 | %ENC100_COMMENTS%// #define ENC100_INT_TRIS (TRISBbits.TRISB2) |
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| 257 | %ENC100_COMMENTS%// #define ENC100_INT_IO (PORTBbits.RB2) |
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| 258 | %ENC100_COMMENTS% |
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| 259 | %ENC100_COMMENTS% // ENC424J600/624J600 SPI pinout |
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| 260 | %ENC100_COMMENTS% #define ENC100_CS_TRIS (TRISBbits.TRISB3) |
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| 261 | %ENC100_COMMENTS% #define ENC100_CS_IO (LATBbits.LATB3) |
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| 262 | %ENC100_COMMENTS% #define ENC100_SO_WR_B0SEL_EN_TRIS (TRISCbits.TRISC4) // NOTE: SO is ENC624J600 Serial Out, which needs to connect to the PIC SDI pin for SPI mode |
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| 263 | %ENC100_COMMENTS% #define ENC100_SO_WR_B0SEL_EN_IO (PORTCbits.RC4) |
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| 264 | %ENC100_COMMENTS% #define ENC100_SI_RD_RW_TRIS (TRISCbits.TRISC5) // NOTE: SI is ENC624J600 Serial In, which needs to connect to the PIC SDO pin for SPI mode |
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| 265 | %ENC100_COMMENTS% #define ENC100_SI_RD_RW_IO (LATCbits.LATC5) |
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| 266 | %ENC100_COMMENTS% #define ENC100_SCK_AL_TRIS (TRISCbits.TRISC3) |
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| 267 | %ENC100_COMMENTS% #define ENC100_SCK_AL_IO (PORTCbits.RC3) // NOTE: This must be the PORT, not the LATch like it is for the PSP interface. |
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| 268 | %ENC100_COMMENTS% |
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| 269 | %ENC100_COMMENTS% // ENC424J600/624J600 SPI SFR register selection (controls which SPI |
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| 270 | %ENC100_COMMENTS% // peripheral to use on PICs with multiple SPI peripherals). |
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| 271 | %ENC100_COMMENTS%// #define ENC100_ISR_ENABLE (INTCON3bits.INT2IE) |
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| 272 | %ENC100_COMMENTS%// #define ENC100_ISR_FLAG (INTCON3bits.INT2IF) |
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| 273 | %ENC100_COMMENTS%// #define ENC100_ISR_POLARITY (INTCON2bits.INTEDG2) |
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| 274 | %ENC100_COMMENTS%// #define ENC100_ISR_PRIORITY (INTCON3bits.INT2IP) |
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| 275 | %ENC100_COMMENTS% #define ENC100_SPI_ENABLE (ENC100_SPISTATbits.SPIEN) |
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| 276 | %ENC100_COMMENTS% #define ENC100_SPI_IF (PIR1bits.SSPIF) |
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| 277 | %ENC100_COMMENTS% #define ENC100_SSPBUF (SSP1BUF) |
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| 278 | %ENC100_COMMENTS% #define ENC100_SPISTAT (SSP1STAT) |
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| 279 | %ENC100_COMMENTS% #define ENC100_SPISTATbits (SSP1STATbits) |
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| 280 | %ENC100_COMMENTS% #define ENC100_SPICON1 (SSP1CON1) |
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| 281 | %ENC100_COMMENTS% #define ENC100_SPICON1bits (SSP1CON1bits) |
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| 282 | %ENC100_COMMENTS% #define ENC100_SPICON2 (SSP1CON2) |
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| 283 | |||
| 284 | %ENC28J60_COMMENTS% // ENC28J60 I/O pins |
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| 285 | %ENC28J60_COMMENTS% #define ENC_RST_TRIS (TRISBbits.TRISB5) |
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| 286 | %ENC28J60_COMMENTS% #define ENC_RST_IO (LATBbits.LATB5) |
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| 287 | %ENC28J60_COMMENTS% #define ENC_CS_TRIS (TRISBbits.TRISB3) // Uncomment this line to use the ENC28J60 Ethernet controller or comment it out to use some other network controller |
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| 288 | %ENC28J60_COMMENTS% #define ENC_CS_IO (LATBbits.LATB3) |
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| 289 | %ENC28J60_COMMENTS% #define ENC_SCK_TRIS (TRISCbits.TRISC3) |
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| 290 | %ENC28J60_COMMENTS% #define ENC_SDI_TRIS (TRISCbits.TRISC4) |
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| 291 | %ENC28J60_COMMENTS% #define ENC_SDO_TRIS (TRISCbits.TRISC5) |
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| 292 | %ENC28J60_COMMENTS% #define ENC_SPI_IF (PIR1bits.SSPIF) |
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| 293 | %ENC28J60_COMMENTS% #define ENC_SSPBUF (SSP1BUF) |
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| 294 | %ENC28J60_COMMENTS% #define ENC_SPISTAT (SSP1STAT) |
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| 295 | %ENC28J60_COMMENTS% #define ENC_SPISTATbits (SSP1STATbits) |
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| 296 | %ENC28J60_COMMENTS% #define ENC_SPICON1 (SSP1CON1) |
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| 297 | %ENC28J60_COMMENTS% #define ENC_SPICON1bits (SSP1CON1bits) |
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| 298 | %ENC28J60_COMMENTS% #define ENC_SPICON2 (SSP1CON2) |
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| 299 | |||
| 300 | %MRF24WB0M_COMMENTS% //---------------- |
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| 301 | %MRF24WB0M_COMMENTS% // MRF24WB0M I/O pins |
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| 302 | %MRF24WB0M_COMMENTS% //---------------- |
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| 303 | %MRF24WB0M_COMMENTS% #define WF_CS_TRIS (TRISCbits.TRISC2) // Uncomment this line if you wish to use the MRF24WB0M on the PICDEM.net 2 board instead of the internal PIC18F97J60 Ethernet module |
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| 304 | %MRF24WB0M_COMMENTS% #define WF_SDI_TRIS (TRISCbits.TRISC4) |
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| 305 | %MRF24WB0M_COMMENTS% #define WF_SCK_TRIS (TRISCbits.TRISC3) |
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| 306 | %MRF24WB0M_COMMENTS% #define WF_SDO_TRIS (TRISCbits.TRISC5) |
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| 307 | %MRF24WB0M_COMMENTS% #define WF_RESET_TRIS (TRISBbits.TRISB1) |
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| 308 | %MRF24WB0M_COMMENTS% #define WF_RESET_IO (LATBbits.LATB1) |
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| 309 | %MRF24WB0M_COMMENTS% #define WF_INT_TRIS (TRISBbits.TRISB0) |
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| 310 | %MRF24WB0M_COMMENTS% #define WF_INT_IO (PORTBbits.RB0) |
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| 311 | %MRF24WB0M_COMMENTS% #define WF_CS_IO (LATCbits.LATC2) |
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| 312 | %MRF24WB0M_COMMENTS% #define WF_HIBERNATE_TRIS (TRISBbits.TRISB2) |
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| 313 | %MRF24WB0M_COMMENTS% #define WF_HIBERNATE_IO (PORTBbits.RB2) |
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| 314 | %MRF24WB0M_COMMENTS% #define WF_INT_EDGE (INTCON2bits.INTEDG0) |
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| 315 | %MRF24WB0M_COMMENTS% #define WF_INT_IE (INTCONbits.INT0IE) |
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| 316 | %MRF24WB0M_COMMENTS% #define WF_INT_IF (INTCONbits.INT0IF) |
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| 317 | %MRF24WB0M_COMMENTS% #define WF_SPI_IF (PIR1bits.SSPIF) |
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| 318 | %MRF24WB0M_COMMENTS% #define WF_SSPBUF (SSP1BUF) |
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| 319 | %MRF24WB0M_COMMENTS% #define WF_SPISTAT (SSP1STAT) |
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| 320 | %MRF24WB0M_COMMENTS% #define WF_SPISTATbits (SSP1STATbits) |
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| 321 | %MRF24WB0M_COMMENTS% #define WF_SPICON1 (SSP1CON1) |
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| 322 | %MRF24WB0M_COMMENTS% #define WF_SPICON1bits (SSP1CON1bits) |
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| 323 | %MRF24WB0M_COMMENTS% #define WF_SPICON2 (SSP1CON2) |
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| 324 | %MRF24WB0M_COMMENTS% #define WF_SPI_IE (PIE1bits.SSPIE) |
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| 325 | %MRF24WB0M_COMMENTS% #define WF_SPI_IP (IPR1bits.SSPIP) |
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| 326 | |||
| 327 | %EEPROM_COMMENTS% // 25LC256 I/O pins |
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| 328 | %EEPROM_COMMENTS% #define EEPROM_CS_TRIS (TRISAbits.TRISA3) |
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| 329 | %EEPROM_COMMENTS% #define EEPROM_CS_IO (LATAbits.LATA3) |
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| 330 | %EEPROM_COMMENTS% #define EEPROM_SCK_TRIS (TRISCbits.TRISC3) |
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| 331 | %EEPROM_COMMENTS% #define EEPROM_SDI_TRIS (TRISCbits.TRISC4) |
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| 332 | %EEPROM_COMMENTS% #define EEPROM_SDO_TRIS (TRISCbits.TRISC5) |
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| 333 | %EEPROM_COMMENTS% #define EEPROM_SPI_IF (PIR1bits.SSPIF) |
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| 334 | %EEPROM_COMMENTS% #define EEPROM_SSPBUF (SSP1BUF) |
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| 335 | %EEPROM_COMMENTS% #define EEPROM_SPICON1 (SSP1CON1) |
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| 336 | %EEPROM_COMMENTS% #define EEPROM_SPICON1bits (SSP1CON1bits) |
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| 337 | %EEPROM_COMMENTS% #define EEPROM_SPICON2 (SSP1CON2) |
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| 338 | %EEPROM_COMMENTS% #define EEPROM_SPISTAT (SSP1STAT) |
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| 339 | %EEPROM_COMMENTS% #define EEPROM_SPISTATbits (SSP1STATbits) |
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| 340 | |||
| 341 | // LCD I/O pins |
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| 342 | // TODO: Need to add support for LCD behind MCP23S17 I/O expander. This |
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| 343 | // requires code that isn't in the TCP/IP stack, not just a hardware |
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| 344 | // profile change. |
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| 345 | |||
| 346 | // Serial Flash/SRAM/UART PICtail |
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| 347 | // #define SPIRAM_CS_TRIS (TRISBbits.TRISB5) |
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| 348 | // #define SPIRAM_CS_IO (LATBbits.LATB5) |
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| 349 | // #define SPIRAM_SCK_TRIS (TRISCbits.TRISC3) |
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| 350 | // #define SPIRAM_SDI_TRIS (TRISCbits.TRISC4) |
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| 351 | // #define SPIRAM_SDO_TRIS (TRISCbits.TRISC5) |
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| 352 | // #define SPIRAM_SPI_IF (PIR1bits.SSPIF) |
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| 353 | // #define SPIRAM_SSPBUF (SSP1BUF) |
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| 354 | // #define SPIRAM_SPICON1 (SSP1CON1) |
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| 355 | // #define SPIRAM_SPICON1bits (SSP1CON1bits) |
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| 356 | // #define SPIRAM_SPICON2 (SSP1CON2) |
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| 357 | // #define SPIRAM_SPISTAT (SSP1STAT) |
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| 358 | // #define SPIRAM_SPISTATbits (SSP1STATbits) |
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| 359 | // |
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| 360 | // // NOTE: You must also set the SPI_FLASH_SST/SPI_FLASH_SPANSION, |
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| 361 | // // SPI_FLASH_SECTOR_SIZE, and SPI_FLASH_PAGE_SIZE macros in |
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| 362 | // // SPIFlash.h to match your particular Flash memory chip!!! |
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| 363 | // #define SPIFLASH_CS_TRIS (TRISBbits.TRISB4) |
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| 364 | // #define SPIFLASH_CS_IO (LATBbits.LATB4) |
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| 365 | // #define SPIFLASH_SCK_TRIS (TRISCbits.TRISC3) |
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| 366 | // #define SPIFLASH_SDI_TRIS (TRISCbits.TRISC4) |
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| 367 | // #define SPIFLASH_SDI_IO (PORTCbits.RC4) |
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| 368 | // #define SPIFLASH_SDO_TRIS (TRISCbits.TRISC5) |
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| 369 | // #define SPIFLASH_SPI_IF (PIR1bits.SSPIF) |
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| 370 | // #define SPIFLASH_SSPBUF (SSP1BUF) |
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| 371 | // #define SPIFLASH_SPICON1 (SSP1CON1) |
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| 372 | // #define SPIFLASH_SPICON1bits (SSP1CON1bits) |
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| 373 | // #define SPIFLASH_SPICON2 (SSP1CON2) |
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| 374 | // #define SPIFLASH_SPISTAT (SSP1STAT) |
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| 375 | // #define SPIFLASH_SPISTATbits (SSP1STATbits) |
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| 376 | |||
| 377 | // Register name fix up for certain processors |
||
| 378 | #define SPBRGH SPBRGH1 |
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| 379 | #if defined(__18F87J50) || defined(_18F87J50) || defined(__18F87J11) || defined(_18F87J11) |
||
| 380 | #define ADCON2 ADCON1 |
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| 381 | #endif |
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| 382 | |||
| 383 | #elif defined(PIC18_EXPLORER) && defined(HI_TECH_C) |
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| 384 | // PIC18 Explorer + Fast 100Mbps Ethernet PICtail Plus or Ethernet PICtail + HI-TECH PICC-18 compiler |
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| 385 | // I/O pins |
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| 386 | #define LED0_TRIS (TRISD0) |
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| 387 | #define LED0_IO (LATD0) |
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| 388 | #define LED1_TRIS (TRISD1) |
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| 389 | #define LED1_IO (LATD1) |
||
| 390 | #define LED2_TRIS (TRISD2) |
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| 391 | #define LED2_IO (LATD2) |
||
| 392 | #define LED3_TRIS (TRISD3) |
||
| 393 | #define LED3_IO (LATD3) |
||
| 394 | #define LED4_TRIS (TRISD4) |
||
| 395 | #define LED4_IO (LATD4) |
||
| 396 | #define LED5_TRIS (TRISD5) |
||
| 397 | #define LED5_IO (LATD5) |
||
| 398 | #define LED6_TRIS (TRISD6) |
||
| 399 | #define LED6_IO (LATD6) |
||
| 400 | #define LED7_TRIS (TRISD7) |
||
| 401 | #define LED7_IO (LATD7) |
||
| 402 | #define LED_GET() (LATD) |
||
| 403 | #define LED_PUT(a) (LATD = (a)) |
||
| 404 | |||
| 405 | #define BUTTON0_TRIS (TRISA5) |
||
| 406 | #define BUTTON0_IO (RA5) |
||
| 407 | #define BUTTON1_TRIS (TRISB0) |
||
| 408 | #define BUTTON1_IO (RB0) |
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| 409 | #define BUTTON2_TRIS (PRODL) // No Button2 on this board |
||
| 410 | #define BUTTON2_IO (1u) |
||
| 411 | #define BUTTON3_TRIS (PRODL) // No Button3 on this board |
||
| 412 | #define BUTTON3_IO (1u) |
||
| 413 | |||
| 414 | %ENC100_COMMENTS% // ENC424J600/624J600 Fast 100Mbps Ethernet PICtail Plus defines |
||
| 415 | %ENC100_COMMENTS% #define ENC100_INTERFACE_MODE 0 // Uncomment this line to use the ENC424J600/624J600 Ethernet controller (SPI mode) or comment it out to use some other network controller |
||
| 416 | %ENC100_COMMENTS% |
||
| 417 | %ENC100_COMMENTS% // ENC100_MDIX, ENC100_POR, and ENC100_INT are all optional. Simply leave |
||
| 418 | %ENC100_COMMENTS% // them commented out if you don't have such a hardware feature on your |
||
| 419 | %ENC100_COMMENTS% // hardware. |
||
| 420 | %ENC100_COMMENTS% #define ENC100_MDIX_TRIS (TRISB4) |
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| 421 | %ENC100_COMMENTS% #define ENC100_MDIX_IO (LATB4) |
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| 422 | %ENC100_COMMENTS%// #define ENC100_POR_TRIS (TRISB5) |
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| 423 | %ENC100_COMMENTS%// #define ENC100_POR_IO (LATB5) |
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| 424 | %ENC100_COMMENTS%// #define ENC100_INT_TRIS (TRISB2) |
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| 425 | %ENC100_COMMENTS%// #define ENC100_INT_IO (RB2) |
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| 426 | %ENC100_COMMENTS% |
||
| 427 | %ENC100_COMMENTS% // ENC424J600/624J600 SPI pinout |
||
| 428 | %ENC100_COMMENTS% #define ENC100_CS_TRIS (TRISB3) |
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| 429 | %ENC100_COMMENTS% #define ENC100_CS_IO (LATB3) |
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| 430 | %ENC100_COMMENTS% #define ENC100_SO_WR_B0SEL_EN_TRIS (TRISC4) // NOTE: SO is ENC624J600 Serial Out, which needs to connect to the PIC SDI pin for SPI mode |
||
| 431 | %ENC100_COMMENTS% #define ENC100_SO_WR_B0SEL_EN_IO (RC4) |
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| 432 | %ENC100_COMMENTS% #define ENC100_SI_RD_RW_TRIS (TRISC5) // NOTE: SI is ENC624J600 Serial In, which needs to connect to the PIC SDO pin for SPI mode |
||
| 433 | %ENC100_COMMENTS% #define ENC100_SI_RD_RW_IO (LATC5) |
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| 434 | %ENC100_COMMENTS% #define ENC100_SCK_AL_TRIS (TRISC3) |
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| 435 | %ENC100_COMMENTS% #define ENC100_SCK_AL_IO (RC3) // NOTE: This must be the PORT, not the LATch like it is for the PSP interface. |
||
| 436 | %ENC100_COMMENTS% |
||
| 437 | %ENC100_COMMENTS% // ENC424J600/624J600 SPI SFR register selection (controls which SPI |
||
| 438 | %ENC100_COMMENTS% // peripheral to use on PICs with multiple SPI peripherals). |
||
| 439 | %ENC100_COMMENTS%// #define ENC100_ISR_ENABLE (INT2IE) |
||
| 440 | %ENC100_COMMENTS%// #define ENC100_ISR_FLAG (INT2IF) |
||
| 441 | %ENC100_COMMENTS%// #define ENC100_ISR_POLARITY (INTEDG2) |
||
| 442 | %ENC100_COMMENTS%// #define ENC100_ISR_PRIORITY (INT2IP) |
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| 443 | %ENC100_COMMENTS% #define ENC100_SPI_ENABLE (ENC100_SPISTATbits.SPIEN) |
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| 444 | %ENC100_COMMENTS% #define ENC100_SPI_IF (SSP1IF) |
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| 445 | %ENC100_COMMENTS% #define ENC100_SSPBUF (SSP1BUF) |
||
| 446 | %ENC100_COMMENTS% #define ENC100_SPISTAT (SSP1STAT) |
||
| 447 | %ENC100_COMMENTS% #define ENC100_SPISTATbits (SSP1STATbits) |
||
| 448 | %ENC100_COMMENTS% #define ENC100_SPICON1 (SSP1CON1) |
||
| 449 | %ENC100_COMMENTS% #define ENC100_SPICON1bits (SSP1CON1bits) |
||
| 450 | %ENC100_COMMENTS% #define ENC100_SPICON2 (SSP1CON2) |
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| 451 | |||
| 452 | %ENC28J60_COMMENTS% // ENC28J60 I/O pins |
||
| 453 | %ENC28J60_COMMENTS% #define ENC_RST_TRIS (TRISB5) |
||
| 454 | %ENC28J60_COMMENTS% #define ENC_RST_IO (LATB5) |
||
| 455 | %ENC28J60_COMMENTS% #define ENC_CS_TRIS (TRISB3) // Uncomment this line to use the ENC28J60 Ethernet controller or comment it out to use some other network controller |
||
| 456 | %ENC28J60_COMMENTS% #define ENC_CS_IO (LATB3) |
||
| 457 | %ENC28J60_COMMENTS% #define ENC_SCK_TRIS (TRISC3) |
||
| 458 | %ENC28J60_COMMENTS% #define ENC_SDI_TRIS (TRISC4) |
||
| 459 | %ENC28J60_COMMENTS% #define ENC_SDO_TRIS (TRISC5) |
||
| 460 | %ENC28J60_COMMENTS% #define ENC_SPI_IF (SSP1IF) |
||
| 461 | %ENC28J60_COMMENTS% #define ENC_SSPBUF (SSP1BUF) |
||
| 462 | %ENC28J60_COMMENTS% #define ENC_SPISTAT (SSP1STAT) |
||
| 463 | %ENC28J60_COMMENTS% #define ENC_SPISTATbits (SSP1STATbits) |
||
| 464 | %ENC28J60_COMMENTS% #define ENC_SPICON1 (SSP1CON1) |
||
| 465 | %ENC28J60_COMMENTS% #define ENC_SPICON1bits (SSP1CON1bits) |
||
| 466 | %ENC28J60_COMMENTS% #define ENC_SPICON2 (SSP1CON2) |
||
| 467 | |||
| 468 | %MRF24WB0M_COMMENTS% //---------------- |
||
| 469 | %MRF24WB0M_COMMENTS% // MRF24WB0M I/O pins |
||
| 470 | %MRF24WB0M_COMMENTS% //---------------- |
||
| 471 | %MRF24WB0M_COMMENTS% #define WF_CS_TRIS (TRISCbits.TRISC2) // Uncomment this line if you wish to use the MRF24WB0M on the PICDEM.net 2 board instead of the internal PIC18F97J60 Ethernet module |
||
| 472 | %MRF24WB0M_COMMENTS% #define WF_SDI_TRIS (TRISCbits.TRISC4) |
||
| 473 | %MRF24WB0M_COMMENTS% #define WF_SCK_TRIS (TRISCbits.TRISC3) |
||
| 474 | %MRF24WB0M_COMMENTS% #define WF_SDO_TRIS (TRISCbits.TRISC5) |
||
| 475 | %MRF24WB0M_COMMENTS% #define WF_RESET_TRIS (TRISBbits.TRISB1) |
||
| 476 | %MRF24WB0M_COMMENTS% #define WF_RESET_IO (LATBbits.LATB1) |
||
| 477 | %MRF24WB0M_COMMENTS% #define WF_INT_TRIS (TRISBbits.TRISB0) |
||
| 478 | %MRF24WB0M_COMMENTS% #define WF_INT_IO (PORTBbits.RB0) |
||
| 479 | %MRF24WB0M_COMMENTS% #define WF_CS_IO (LATCbits.LATC2) |
||
| 480 | %MRF24WB0M_COMMENTS% #define WF_HIBERNATE_TRIS (TRISBbits.TRISB2) |
||
| 481 | %MRF24WB0M_COMMENTS% #define WF_HIBERNATE_IO (PORTBbits.RB2) |
||
| 482 | %MRF24WB0M_COMMENTS% #define WF_INT_EDGE (INTCON2bits.INTEDG0) |
||
| 483 | %MRF24WB0M_COMMENTS% #define WF_INT_IE (INTCONbits.INT0IE) |
||
| 484 | %MRF24WB0M_COMMENTS% #define WF_INT_IF (INTCONbits.INT0IF) |
||
| 485 | %MRF24WB0M_COMMENTS% #define WF_SPI_IF (PIR1bits.SSPIF) |
||
| 486 | %MRF24WB0M_COMMENTS% #define WF_SSPBUF (SSP1BUF) |
||
| 487 | %MRF24WB0M_COMMENTS% #define WF_SPISTAT (SSP1STAT) |
||
| 488 | %MRF24WB0M_COMMENTS% #define WF_SPISTATbits (SSP1STATbits) |
||
| 489 | %MRF24WB0M_COMMENTS% #define WF_SPICON1 (SSP1CON1) |
||
| 490 | %MRF24WB0M_COMMENTS% #define WF_SPICON1bits (SSP1CON1bits) |
||
| 491 | %MRF24WB0M_COMMENTS% #define WF_SPICON2 (SSP1CON2) |
||
| 492 | %MRF24WB0M_COMMENTS% #define WF_SPI_IE (PIE1bits.SSPIE) |
||
| 493 | %MRF24WB0M_COMMENTS% #define WF_SPI_IP (IPR1bits.SSPIP) |
||
| 494 | |||
| 495 | %EEPROM_COMMENTS% // 25LC256 I/O pins |
||
| 496 | %EEPROM_COMMENTS% #define EEPROM_CS_TRIS (TRISA3) |
||
| 497 | %EEPROM_COMMENTS% #define EEPROM_CS_IO (LATA3) |
||
| 498 | %EEPROM_COMMENTS% #define EEPROM_SCK_TRIS (TRISC3) |
||
| 499 | %EEPROM_COMMENTS% #define EEPROM_SDI_TRIS (TRISC4) |
||
| 500 | %EEPROM_COMMENTS% #define EEPROM_SDO_TRIS (TRISC5) |
||
| 501 | %EEPROM_COMMENTS% #define EEPROM_SPI_IF (SSP1IF) |
||
| 502 | %EEPROM_COMMENTS% #define EEPROM_SSPBUF (SSP1BUF) |
||
| 503 | %EEPROM_COMMENTS% #define EEPROM_SPICON1 (SSP1CON1) |
||
| 504 | %EEPROM_COMMENTS% #define EEPROM_SPICON1bits (SSP1CON1bits) |
||
| 505 | %EEPROM_COMMENTS% #define EEPROM_SPICON2 (SSP1CON2) |
||
| 506 | %EEPROM_COMMENTS% #define EEPROM_SPISTAT (SSP1STAT) |
||
| 507 | %EEPROM_COMMENTS% #define EEPROM_SPISTATbits (SSP1STATbits) |
||
| 508 | |||
| 509 | // LCD I/O pins |
||
| 510 | // TODO: Need to add support for LCD behind MCP23S17 I/O expander. This |
||
| 511 | // requires code that isn't in the TCP/IP stack, not just a hardware |
||
| 512 | // profile change. |
||
| 513 | |||
| 514 | // Register name fix up for certain processors |
||
| 515 | #define SPBRGH SPBRGH1 |
||
| 516 | #define TXSTAbits TXSTA1bits |
||
| 517 | #define RCSTAbits RCSTA1bits |
||
| 518 | #define BAUDCONbits BAUDCON1bits |
||
| 519 | #define GO GODONE |
||
| 520 | #if defined(__18F87J50) || defined(_18F87J50) || defined(__18F87J11) || defined(_18F87J11) |
||
| 521 | #define ADCON2 ADCON1 |
||
| 522 | #endif |
||
| 523 | |||
| 524 | #elif defined(HPC_EXPLORER) && !defined(HI_TECH_C) |
||
| 525 | // PICDEM HPC Explorer + Fast 100Mbps Ethernet PICtail Plus or Ethernet PICtail |
||
| 526 | // I/O pins |
||
| 527 | #define LED0_TRIS (TRISDbits.TRISD0) |
||
| 528 | #define LED0_IO (LATDbits.LATD0) |
||
| 529 | #define LED1_TRIS (TRISDbits.TRISD1) |
||
| 530 | #define LED1_IO (LATDbits.LATD1) |
||
| 531 | #define LED2_TRIS (TRISDbits.TRISD2) |
||
| 532 | #define LED2_IO (LATDbits.LATD2) |
||
| 533 | #define LED3_TRIS (TRISDbits.TRISD3) |
||
| 534 | #define LED3_IO (LATDbits.LATD3) |
||
| 535 | #define LED4_TRIS (TRISDbits.TRISD4) |
||
| 536 | #define LED4_IO (LATDbits.LATD4) |
||
| 537 | #define LED5_TRIS (TRISDbits.TRISD5) |
||
| 538 | #define LED5_IO (LATDbits.LATD5) |
||
| 539 | #define LED6_TRIS (TRISDbits.TRISD6) |
||
| 540 | #define LED6_IO (LATDbits.LATD6) |
||
| 541 | #define LED7_TRIS (TRISDbits.TRISD7) |
||
| 542 | #define LED7_IO (LATDbits.LATD7) |
||
| 543 | #define LED_GET() (LATD) |
||
| 544 | #define LED_PUT(a) (LATD = (a)) |
||
| 545 | |||
| 546 | |||
| 547 | #define BUTTON0_TRIS (TRISBbits.TRISB0) |
||
| 548 | #define BUTTON0_IO (PORTBbits.RB0) |
||
| 549 | #define BUTTON1_TRIS (TRISBbits.TRISB0) // No Button1 on this board, remap to Button0 |
||
| 550 | #define BUTTON1_IO (PORTBbits.RB0) |
||
| 551 | #define BUTTON2_TRIS (TRISBbits.TRISB0) // No Button2 on this board, remap to Button0 |
||
| 552 | #define BUTTON2_IO (PORTBbits.RB0) |
||
| 553 | #define BUTTON3_TRIS (TRISBbits.TRISB0) // No Button3 on this board, remap to Button0 |
||
| 554 | #define BUTTON3_IO (PORTBbits.RB0) |
||
| 555 | |||
| 556 | %ENC100_COMMENTS% // ENC424J600/624J600 Fast 100Mbps Ethernet PICtail Plus defines |
||
| 557 | %ENC100_COMMENTS% #define ENC100_INTERFACE_MODE 0 // Uncomment this line to use the ENC424J600/624J600 Ethernet controller (SPI mode) or comment it out to use some other network controller |
||
| 558 | %ENC100_COMMENTS% |
||
| 559 | %ENC100_COMMENTS% // ENC424J600/624J600 Fast 100Mbps Ethernet PICtail Plus I/O pins |
||
| 560 | %ENC100_COMMENTS% #define ENC100_MDIX_TRIS (TRISBbits.TRISB4) |
||
| 561 | %ENC100_COMMENTS% #define ENC100_MDIX_IO (LATBbits.LATB4) |
||
| 562 | %ENC100_COMMENTS% #define ENC100_POR_TRIS (TRISBbits.TRISB5) |
||
| 563 | %ENC100_COMMENTS% #define ENC100_POR_IO (LATBbits.LATB5) |
||
| 564 | %ENC100_COMMENTS%// #define ENC100_INT_TRIS (TRISBbits.TRISB2) |
||
| 565 | %ENC100_COMMENTS%// #define ENC100_INT_IO (PORTBbits.RB2) |
||
| 566 | %ENC100_COMMENTS% |
||
| 567 | %ENC100_COMMENTS% // ENC424J600/624J600 SPI pinout |
||
| 568 | %ENC100_COMMENTS% #define ENC100_CS_TRIS (TRISBbits.TRISB3) |
||
| 569 | %ENC100_COMMENTS% #define ENC100_CS_IO (LATBbits.LATB3) |
||
| 570 | %ENC100_COMMENTS% #define ENC100_SO_WR_B0SEL_EN_TRIS (TRISCbits.TRISC4) // NOTE: SO is ENC624J600 Serial Out, which needs to connect to the PIC SDI pin for SPI mode |
||
| 571 | %ENC100_COMMENTS% #define ENC100_SO_WR_B0SEL_EN_IO (PORTCbits.RC4) |
||
| 572 | %ENC100_COMMENTS% #define ENC100_SI_RD_RW_TRIS (TRISCbits.TRISC5) // NOTE: SI is ENC624J600 Serial In, which needs to connect to the PIC SDO pin for SPI mode |
||
| 573 | %ENC100_COMMENTS% #define ENC100_SI_RD_RW_IO (LATCbits.LATC5) |
||
| 574 | %ENC100_COMMENTS% #define ENC100_SCK_AL_TRIS (TRISCbits.TRISC3) |
||
| 575 | %ENC100_COMMENTS% #define ENC100_SCK_AL_IO (PORTCbits.RC3) // NOTE: This must be the PORT, not the LATch like it is for the PSP interface. |
||
| 576 | %ENC100_COMMENTS% |
||
| 577 | %ENC100_COMMENTS% // ENC424J600/624J600 SPI SFR register selection (controls which SPI |
||
| 578 | %ENC100_COMMENTS% // peripheral to use on PICs with multiple SPI peripherals). |
||
| 579 | %ENC100_COMMENTS%// #define ENC100_ISR_ENABLE (INTCON3bits.INT2IE) |
||
| 580 | %ENC100_COMMENTS%// #define ENC100_ISR_FLAG (INTCON3bits.INT2IF) |
||
| 581 | %ENC100_COMMENTS%// #define ENC100_ISR_POLARITY (INTCON2bits.INTEDG2) |
||
| 582 | %ENC100_COMMENTS%// #define ENC100_ISR_PRIORITY (INTCON3bits.INT2IP) |
||
| 583 | %ENC100_COMMENTS% #define ENC100_SPI_ENABLE (ENC100_SPISTATbits.SPIEN) |
||
| 584 | %ENC100_COMMENTS% #define ENC100_SPI_IF (PIR1bits.SSPIF) |
||
| 585 | %ENC100_COMMENTS% #define ENC100_SSPBUF (SSP1BUF) |
||
| 586 | %ENC100_COMMENTS% #define ENC100_SPISTAT (SSP1STAT) |
||
| 587 | %ENC100_COMMENTS% #define ENC100_SPISTATbits (SSP1STATbits) |
||
| 588 | %ENC100_COMMENTS% #define ENC100_SPICON1 (SSP1CON1) |
||
| 589 | %ENC100_COMMENTS% #define ENC100_SPICON1bits (SSP1CON1bits) |
||
| 590 | %ENC100_COMMENTS% #define ENC100_SPICON2 (SSP1CON2) |
||
| 591 | |||
| 592 | %ENC28J60_COMMENTS% // ENC28J60 I/O pins |
||
| 593 | %ENC28J60_COMMENTS% #define ENC_RST_TRIS (TRISBbits.TRISB5) |
||
| 594 | %ENC28J60_COMMENTS% #define ENC_RST_IO (LATBbits.LATB5) |
||
| 595 | %ENC28J60_COMMENTS% #define ENC_CS_TRIS (TRISBbits.TRISB3) // Uncomment this line to use the ENC28J60 Ethernet controller or comment it out to use some other network controller |
||
| 596 | %ENC28J60_COMMENTS% #define ENC_CS_IO (LATBbits.LATB3) |
||
| 597 | %ENC28J60_COMMENTS% #define ENC_SCK_TRIS (TRISCbits.TRISC3) |
||
| 598 | %ENC28J60_COMMENTS% #define ENC_SDI_TRIS (TRISCbits.TRISC4) |
||
| 599 | %ENC28J60_COMMENTS% #define ENC_SDO_TRIS (TRISCbits.TRISC5) |
||
| 600 | %ENC28J60_COMMENTS% #define ENC_SPI_IF (PIR1bits.SSPIF) |
||
| 601 | %ENC28J60_COMMENTS% #define ENC_SSPBUF (SSP1BUF) |
||
| 602 | %ENC28J60_COMMENTS% #define ENC_SPISTAT (SSP1STAT) |
||
| 603 | %ENC28J60_COMMENTS% #define ENC_SPISTATbits (SSP1STATbits) |
||
| 604 | %ENC28J60_COMMENTS% #define ENC_SPICON1 (SSP1CON1) |
||
| 605 | %ENC28J60_COMMENTS% #define ENC_SPICON1bits (SSP1CON1bits) |
||
| 606 | %ENC28J60_COMMENTS% #define ENC_SPICON2 (SSP1CON2) |
||
| 607 | |||
| 608 | %EEPROM_COMMENTS% // 25LC256 I/O pins |
||
| 609 | %EEPROM_COMMENTS% #define EEPROM_CS_TRIS (TRISBbits.TRISB4) |
||
| 610 | %EEPROM_COMMENTS% #define EEPROM_CS_IO (LATBbits.LATB4) |
||
| 611 | %EEPROM_COMMENTS% #define EEPROM_SCK_TRIS (TRISCbits.TRISC3) |
||
| 612 | %EEPROM_COMMENTS% #define EEPROM_SDI_TRIS (TRISCbits.TRISC4) |
||
| 613 | %EEPROM_COMMENTS% #define EEPROM_SDO_TRIS (TRISCbits.TRISC5) |
||
| 614 | %EEPROM_COMMENTS% #define EEPROM_SPI_IF (PIR1bits.SSPIF) |
||
| 615 | %EEPROM_COMMENTS% #define EEPROM_SSPBUF (SSP1BUF) |
||
| 616 | %EEPROM_COMMENTS% #define EEPROM_SPICON1 (SSP1CON1) |
||
| 617 | %EEPROM_COMMENTS% #define EEPROM_SPICON1bits (SSP1CON1bits) |
||
| 618 | %EEPROM_COMMENTS% #define EEPROM_SPICON2 (SSP1CON2) |
||
| 619 | %EEPROM_COMMENTS% #define EEPROM_SPISTAT (SSP1STAT) |
||
| 620 | %EEPROM_COMMENTS% #define EEPROM_SPISTATbits (SSP1STATbits) |
||
| 621 | |||
| 622 | // Register name fix up for certain processors |
||
| 623 | #define SPBRGH SPBRGH1 |
||
| 624 | #if defined(__18F87J50) || defined(_18F87J50) || defined(__18F87J11) || defined(_18F87J11) |
||
| 625 | #define ADCON2 ADCON1 |
||
| 626 | #endif |
||
| 627 | |||
| 628 | #elif defined(HPC_EXPLORER) && defined(HI_TECH_C) |
||
| 629 | // PICDEM HPC Explorer + Ethernet PICtail |
||
| 630 | #define TXSTA TXSTA1 |
||
| 631 | #define RCSTA RCSTA1 |
||
| 632 | #define SPBRG SPBRG1 |
||
| 633 | #define SPBRGH SPBRGH1 |
||
| 634 | #define RCREG RCREG1 |
||
| 635 | #define TXREG TXREG1 |
||
| 636 | |||
| 637 | // I/O pins |
||
| 638 | #define LED0_TRIS (TRISD0) |
||
| 639 | #define LED0_IO (LATD0) |
||
| 640 | #define LED1_TRIS (TRISD1) |
||
| 641 | #define LED1_IO (LATD1) |
||
| 642 | #define LED2_TRIS (TRISD2) |
||
| 643 | #define LED2_IO (LATD2) |
||
| 644 | #define LED3_TRIS (TRISD3) |
||
| 645 | #define LED3_IO (LATD3) |
||
| 646 | #define LED4_TRIS (TRISD4) |
||
| 647 | #define LED4_IO (LATD4) |
||
| 648 | #define LED5_TRIS (TRISD5) |
||
| 649 | #define LED5_IO (LATD5) |
||
| 650 | #define LED6_TRIS (TRISD6) |
||
| 651 | #define LED6_IO (LATD6) |
||
| 652 | #define LED7_TRIS (TRISD7) |
||
| 653 | #define LED7_IO (LATD7) |
||
| 654 | #define LED_GET() (LATD) |
||
| 655 | #define LED_PUT(a) (LATD = (a)) |
||
| 656 | |||
| 657 | #define BUTTON0_TRIS (TRISB0) |
||
| 658 | #define BUTTON0_IO (RB0) |
||
| 659 | #define BUTTON1_TRIS (TRISB0) // No Button1 on this board, remap to Button0 |
||
| 660 | #define BUTTON1_IO (RB0) |
||
| 661 | #define BUTTON2_TRIS (TRISB0) // No Button2 on this board, remap to Button0 |
||
| 662 | #define BUTTON2_IO (RB0) |
||
| 663 | #define BUTTON3_TRIS (TRISB0) // No Button3 on this board, remap to Button0 |
||
| 664 | #define BUTTON3_IO (RB0) |
||
| 665 | |||
| 666 | %ENC28J60_COMMENTS% // ENC28J60 I/O pins |
||
| 667 | %ENC28J60_COMMENTS% #define ENC_RST_TRIS (TRISB5) |
||
| 668 | %ENC28J60_COMMENTS% #define ENC_RST_IO (LATB5) |
||
| 669 | %ENC28J60_COMMENTS% #define ENC_CS_TRIS (TRISB3) |
||
| 670 | %ENC28J60_COMMENTS% #define ENC_CS_IO (LATB3) |
||
| 671 | %ENC28J60_COMMENTS% #define ENC_SCK_TRIS (TRISC3) |
||
| 672 | %ENC28J60_COMMENTS% #define ENC_SDI_TRIS (TRISC4) |
||
| 673 | %ENC28J60_COMMENTS% #define ENC_SDO_TRIS (TRISC5) |
||
| 674 | %ENC28J60_COMMENTS% #define ENC_SPI_IF (SSP1IF) |
||
| 675 | %ENC28J60_COMMENTS% #define ENC_SSPBUF (SSP1BUF) |
||
| 676 | %ENC28J60_COMMENTS% #define ENC_SPISTAT (SSP1STAT) |
||
| 677 | %ENC28J60_COMMENTS% #define ENC_SPISTATbits (SSP1STATbits) |
||
| 678 | %ENC28J60_COMMENTS% #define ENC_SPICON1 (SSP1CON1) |
||
| 679 | %ENC28J60_COMMENTS% #define ENC_SPICON1bits (SSP1CON1bits) |
||
| 680 | %ENC28J60_COMMENTS% #define ENC_SPICON2 (SSP1CON2) |
||
| 681 | |||
| 682 | %EEPROM_COMMENTS% // 25LC256 I/O pins |
||
| 683 | %EEPROM_COMMENTS% #define EEPROM_CS_TRIS (TRISB4) |
||
| 684 | %EEPROM_COMMENTS% #define EEPROM_CS_IO (LATB4) |
||
| 685 | %EEPROM_COMMENTS% #define EEPROM_SCK_TRIS (TRISC3) |
||
| 686 | %EEPROM_COMMENTS% #define EEPROM_SDI_TRIS (TRISC4) |
||
| 687 | %EEPROM_COMMENTS% #define EEPROM_SDO_TRIS (TRISC5) |
||
| 688 | %EEPROM_COMMENTS% #define EEPROM_SPI_IF (SSP1IF) |
||
| 689 | %EEPROM_COMMENTS% #define EEPROM_SSPBUF (SSP1BUF) |
||
| 690 | %EEPROM_COMMENTS% #define EEPROM_SPICON1 (SSP1CON1) |
||
| 691 | %EEPROM_COMMENTS% #define EEPROM_SPICON1bits (SSP1CON1bits) |
||
| 692 | %EEPROM_COMMENTS% #define EEPROM_SPICON2 (SSP1CON2) |
||
| 693 | %EEPROM_COMMENTS% #define EEPROM_SPISTAT (SSP1STAT) |
||
| 694 | %EEPROM_COMMENTS% #define EEPROM_SPISTATbits (SSP1STATbits) |
||
| 695 | |||
| 696 | #elif defined(PIC24FJ64GA004_PIM) |
||
| 697 | // Explorer 16 + PIC24FJ64GA004 PIM + Ethernet PICtail Plus |
||
| 698 | |||
| 699 | // Push Button I/O pins |
||
| 700 | #define BUTTON3_TRIS TRISAbits.TRISA10 // Mutliplexed with LED0 |
||
| 701 | #define BUTTON3_IO PORTAbits.RA10 |
||
| 702 | #define BUTTON2_TRIS TRISAbits.TRISA9 // Multiplexed with LED4 |
||
| 703 | #define BUTTON2_IO PORTAbits.RA9 |
||
| 704 | #define BUTTON1_TRIS TRISCbits.TRISC6 // Multiplexed with LED7 |
||
| 705 | #define BUTTON1_IO PORTCbits.RC6 |
||
| 706 | #define BUTTON0_TRIS TRISAbits.TRISA7 // Multiplexed with LED1 |
||
| 707 | #define BUTTON0_IO PORTAbits.RA7 |
||
| 708 | |||
| 709 | // LED I/O pins |
||
| 710 | #define LED0_TRIS TRISAbits.TRISA10 // Multiplexed with BUTTON3 |
||
| 711 | #define LED0_IO LATAbits.LATA10 |
||
| 712 | #define LED1_TRIS TRISAbits.TRISA7 // Multiplexed with BUTTON0 |
||
| 713 | #define LED1_IO LATAbits.LATA7 |
||
| 714 | #define LED2_TRIS TRISBbits.TRISB8 // Multiplexed with LCD_DATA4 |
||
| 715 | #define LED2_IO LATBbits.LATB8 |
||
| 716 | #define LED3_TRIS TRISBbits.TRISB9 // Multiplexed with LCD_DATA3 |
||
| 717 | #define LED3_IO LATBbits.LATB9 |
||
| 718 | #define LED4_TRIS TRISAbits.TRISA9 // Multiplexed with BUTTON2 |
||
| 719 | #define LED4_IO LATAbits.LATA9 |
||
| 720 | #define LED5_TRIS TRISAbits.TRISA8 // Multiplexed with EEPROM_CS |
||
| 721 | #define LED5_IO LATAbits.LATA8 |
||
| 722 | #define LED6_TRIS TRISBbits.TRISB12 // Multiplexed with LCD_DATA0 |
||
| 723 | #define LED6_IO LATBbits.LATB12 |
||
| 724 | #define LED7_TRIS TRISCbits.TRISC6 // Multiplexed with BUTTON1 |
||
| 725 | #define LED7_IO LATCbits.LATC6 |
||
| 726 | #define LED_GET() (0u) |
||
| 727 | #define LED_PUT(a) |
||
| 728 | |||
| 729 | // UART I/O Mapping |
||
| 730 | #define UARTTX_TRIS (TRISCbits.TRISC9) |
||
| 731 | #define UARTTX_IO (PORTCbits.RC9) |
||
| 732 | #define UARTRX_TRIS (TRISCbits.TRISC3) |
||
| 733 | #define UARTRX_IO (PORTCbits.RC3) |
||
| 734 | |||
| 735 | %ENC28J60_COMMENTS% // ENC28J60 I/O pins |
||
| 736 | %ENC28J60_COMMENTS% #define ENC_RST_TRIS (TRISCbits.TRISC8) // Not connected by default |
||
| 737 | %ENC28J60_COMMENTS% #define ENC_RST_IO (PORTCbits.RC8) |
||
| 738 | %ENC28J60_COMMENTS% #define ENC_CS_TRIS (TRISBbits.TRISB3) |
||
| 739 | %ENC28J60_COMMENTS% #define ENC_CS_IO (PORTBbits.RB3) |
||
| 740 | %ENC28J60_COMMENTS% // SPI SCK, SDI, SDO pins are automatically controlled by the |
||
| 741 | %ENC28J60_COMMENTS% // PIC24/dsPIC/PIC32 SPI module |
||
| 742 | %ENC28J60_COMMENTS% #define ENC_SPI_IF (IFS0bits.SPI1IF) |
||
| 743 | %ENC28J60_COMMENTS% #define ENC_SSPBUF (SPI1BUF) |
||
| 744 | %ENC28J60_COMMENTS% #define ENC_SPISTAT (SPI1STAT) |
||
| 745 | %ENC28J60_COMMENTS% #define ENC_SPISTATbits (SPI1STATbits) |
||
| 746 | %ENC28J60_COMMENTS% #define ENC_SPICON1 (SPI1CON1) |
||
| 747 | %ENC28J60_COMMENTS% #define ENC_SPICON1bits (SPI1CON1bits) |
||
| 748 | %ENC28J60_COMMENTS% #define ENC_SPICON2 (SPI1CON2) |
||
| 749 | |||
| 750 | %EEPROM_COMMENTS% // 25LC256 I/O pins |
||
| 751 | %EEPROM_COMMENTS% #define EEPROM_CS_TRIS (TRISAbits.TRISA8) |
||
| 752 | %EEPROM_COMMENTS% #define EEPROM_CS_IO (PORTAbits.RA8) |
||
| 753 | %EEPROM_COMMENTS% #define EEPROM_SCK_TRIS (TRISCbits.TRISC8) |
||
| 754 | %EEPROM_COMMENTS% #define EEPROM_SDI_TRIS (TRISCbits.TRISC4) |
||
| 755 | %EEPROM_COMMENTS% #define EEPROM_SDO_TRIS (TRISCbits.TRISC5) |
||
| 756 | %EEPROM_COMMENTS% #define EEPROM_SPI_IF (IFS2bits.SPI2IF) |
||
| 757 | %EEPROM_COMMENTS% #define EEPROM_SSPBUF (SPI2BUF) |
||
| 758 | %EEPROM_COMMENTS% #define EEPROM_SPICON1 (SPI2CON1) |
||
| 759 | %EEPROM_COMMENTS% #define EEPROM_SPICON1bits (SPI2CON1bits) |
||
| 760 | %EEPROM_COMMENTS% #define EEPROM_SPICON2 (SPI2CON2) |
||
| 761 | %EEPROM_COMMENTS% #define EEPROM_SPISTAT (SPI2STAT) |
||
| 762 | %EEPROM_COMMENTS% #define EEPROM_SPISTATbits (SPI2STATbits) |
||
| 763 | |||
| 764 | // LCD Module I/O pins |
||
| 765 | #define LCD_DATA0_TRIS (TRISBbits.TRISB12) // Multiplexed with LED6 |
||
| 766 | #define LCD_DATA0_IO (LATBbits.LATB12) |
||
| 767 | #define LCD_DATA1_TRIS (TRISBbits.TRISB11) |
||
| 768 | #define LCD_DATA1_IO (LATBbits.LATB11) |
||
| 769 | #define LCD_DATA2_TRIS (TRISBbits.TRISB10) |
||
| 770 | #define LCD_DATA2_IO (LATBbits.LATB10) |
||
| 771 | #define LCD_DATA3_TRIS (TRISBbits.TRISB9) // Multiplexed with LED3 |
||
| 772 | #define LCD_DATA3_IO (LATBbits.LATB9) |
||
| 773 | #define LCD_DATA4_TRIS (TRISBbits.TRISB8) // Multiplexed with LED2 |
||
| 774 | #define LCD_DATA4_IO (LATBbits.LATB8) |
||
| 775 | #define LCD_DATA5_TRIS (TRISBbits.TRISB7) |
||
| 776 | #define LCD_DATA5_IO (LATBbits.LATB7) |
||
| 777 | #define LCD_DATA6_TRIS (TRISBbits.TRISB6) |
||
| 778 | #define LCD_DATA6_IO (LATBbits.LATB6) |
||
| 779 | #define LCD_DATA7_TRIS (TRISBbits.TRISB5) |
||
| 780 | #define LCD_DATA7_IO (LATBbits.LATB5) |
||
| 781 | #define LCD_RD_WR_TRIS (TRISBbits.TRISB13) |
||
| 782 | #define LCD_RD_WR_IO (LATBbits.LATB13) |
||
| 783 | #define LCD_RS_TRIS (TRISCbits.TRISC7) |
||
| 784 | #define LCD_RS_IO (LATCbits.LATC7) |
||
| 785 | #define LCD_E_TRIS (TRISBbits.TRISB14) |
||
| 786 | #define LCD_E_IO (LATBbits.LATB14) |
||
| 787 | |||
| 788 | // Peripheral Pin Select Outputs |
||
| 789 | #define NULL_IO 0 |
||
| 790 | #define C1OUT_IO 1 |
||
| 791 | #define C2OUT_IO 2 |
||
| 792 | #define U1TX_IO 3 |
||
| 793 | #define U1RTS_IO 4 |
||
| 794 | #define U2TX_IO 5 |
||
| 795 | #define U2RTS_IO 6 |
||
| 796 | #define SDO1_IO 7 |
||
| 797 | #define SCK1OUT_IO 8 |
||
| 798 | #define SS1OUT_IO 9 |
||
| 799 | #define SDO2_IO 10 |
||
| 800 | #define SCK2OUT_IO 11 |
||
| 801 | #define SS2OUT_IO 12 |
||
| 802 | #define OC1_IO 18 |
||
| 803 | #define OC2_IO 19 |
||
| 804 | #define OC3_IO 20 |
||
| 805 | #define OC4_IO 21 |
||
| 806 | #define OC5_IO 22 |
||
| 807 | |||
| 808 | #elif defined(EXPLORER_16) |
||
| 809 | // Explorer 16 + PIC24FJ128GA010/PIC24HJ256GP610/dsPIC33FJ256GP710/ |
||
| 810 | // PIC32MX460F512L/PIC32MX360F512L/PIC32MX795F512L PIM + |
||
| 811 | // Fast 100Mbps Ethernet PICtail Plus or Ethernet PICtail Plus or MRF24WB0M WiFi PICtail Plus |
||
| 812 | |||
| 813 | #define LED0_TRIS (TRISAbits.TRISA0) // Ref D3 |
||
| 814 | #define LED0_IO (LATAbits.LATA0) |
||
| 815 | #define LED1_TRIS (TRISAbits.TRISA1) // Ref D4 |
||
| 816 | #define LED1_IO (LATAbits.LATA1) |
||
| 817 | #define LED2_TRIS (TRISAbits.TRISA2) // Ref D5 |
||
| 818 | #define LED2_IO (LATAbits.LATA2) |
||
| 819 | #define LED3_TRIS (TRISAbits.TRISA3) // Ref D6 |
||
| 820 | #define LED3_IO (LATAbits.LATA3) |
||
| 821 | #define LED4_TRIS (TRISAbits.TRISA4) // Ref D7 |
||
| 822 | #define LED4_IO (LATAbits.LATA4) |
||
| 823 | #define LED5_TRIS (TRISAbits.TRISA5) // Ref D8 |
||
| 824 | #define LED5_IO (LATAbits.LATA5) |
||
| 825 | #define LED6_TRIS (TRISAbits.TRISA6) // Ref D9 |
||
| 826 | #define LED6_IO (LATAbits.LATA6) |
||
| 827 | #define LED7_TRIS (TRISAbits.TRISA7) // Ref D10 // Note: This is multiplexed with BUTTON1 |
||
| 828 | #define LED7_IO (LATAbits.LATA7) |
||
| 829 | #define LED_GET() (*((volatile unsigned char*)(&LATA))) |
||
| 830 | #define LED_PUT(a) (*((volatile unsigned char*)(&LATA)) = (a)) |
||
| 831 | |||
| 832 | |||
| 833 | #define BUTTON0_TRIS (TRISDbits.TRISD13) // Ref S4 |
||
| 834 | #define BUTTON0_IO (PORTDbits.RD13) |
||
| 835 | #define BUTTON1_TRIS (TRISAbits.TRISA7) // Ref S5 // Note: This is multiplexed with LED7 |
||
| 836 | #define BUTTON1_IO (PORTAbits.RA7) |
||
| 837 | #define BUTTON2_TRIS (TRISDbits.TRISD7) // Ref S6 |
||
| 838 | #define BUTTON2_IO (PORTDbits.RD7) |
||
| 839 | #define BUTTON3_TRIS (TRISDbits.TRISD6) // Ref S3 |
||
| 840 | #define BUTTON3_IO (PORTDbits.RD6) |
||
| 841 | |||
| 842 | #define UARTTX_TRIS (TRISFbits.TRISF5) |
||
| 843 | #define UARTTX_IO (PORTFbits.RF5) |
||
| 844 | #define UARTRX_TRIS (TRISFbits.TRISF4) |
||
| 845 | #define UARTRX_IO (PORTFbits.RF4) |
||
| 846 | |||
| 847 | %ENC28J60_COMMENTS% // ENC28J60 I/O pins |
||
| 848 | %ENC28J60_COMMENTS% #if defined(__PIC24FJ256GA110__) // PIC24FJ256GA110 must place the ENC28J60 on SPI2 because PIC rev A3 SCK1 output pin is a PPS input only (fixed on A5, but demos use SPI2 for simplicity) |
||
| 849 | %ENC28J60_COMMENTS% #define ENC_CS_TRIS (TRISFbits.TRISF12) // Comment this line out if you are using the ENC424J600/624J600, MRF24WB0M, or other network controller. |
||
| 850 | %ENC28J60_COMMENTS% #define ENC_CS_IO (LATFbits.LATF12) |
||
| 851 | %ENC28J60_COMMENTS% // SPI SCK, SDI, SDO pins are automatically controlled by the |
||
| 852 | %ENC28J60_COMMENTS% // PIC24/dsPIC/PIC32 SPI module |
||
| 853 | %ENC28J60_COMMENTS% #define ENC_SPI_IF (IFS2bits.SPI2IF) |
||
| 854 | %ENC28J60_COMMENTS% #define ENC_SSPBUF (SPI2BUF) |
||
| 855 | %ENC28J60_COMMENTS% #define ENC_SPISTAT (SPI2STAT) |
||
| 856 | %ENC28J60_COMMENTS% #define ENC_SPISTATbits (SPI2STATbits) |
||
| 857 | %ENC28J60_COMMENTS% #define ENC_SPICON1 (SPI2CON1) |
||
| 858 | %ENC28J60_COMMENTS% #define ENC_SPICON1bits (SPI2CON1bits) |
||
| 859 | %ENC28J60_COMMENTS% #define ENC_SPICON2 (SPI2CON2) |
||
| 860 | %ENC28J60_COMMENTS% #else // SPI1 for all other processors |
||
| 861 | %ENC28J60_COMMENTS% #define ENC_CS_TRIS (TRISDbits.TRISD14) // Comment this line out if you are using the ENC424J600/624J600, MRF24WB0M, or other network controller. |
||
| 862 | %ENC28J60_COMMENTS% #define ENC_CS_IO (LATDbits.LATD14) |
||
| 863 | %ENC28J60_COMMENTS% // SPI SCK, SDI, SDO pins are automatically controlled by the |
||
| 864 | %ENC28J60_COMMENTS% // PIC24/dsPIC/PIC32 SPI module |
||
| 865 | %ENC28J60_COMMENTS% #if defined(__C30__) // PIC24F, PIC24H, dsPIC30, dsPIC33 |
||
| 866 | %ENC28J60_COMMENTS% #define ENC_SPI_IF (IFS0bits.SPI1IF) |
||
| 867 | %ENC28J60_COMMENTS% #define ENC_SSPBUF (SPI1BUF) |
||
| 868 | %ENC28J60_COMMENTS% #define ENC_SPISTAT (SPI1STAT) |
||
| 869 | %ENC28J60_COMMENTS% #define ENC_SPISTATbits (SPI1STATbits) |
||
| 870 | %ENC28J60_COMMENTS% #define ENC_SPICON1 (SPI1CON1) |
||
| 871 | %ENC28J60_COMMENTS% #define ENC_SPICON1bits (SPI1CON1bits) |
||
| 872 | %ENC28J60_COMMENTS% #define ENC_SPICON2 (SPI1CON2) |
||
| 873 | %ENC28J60_COMMENTS% #else // PIC32 |
||
| 874 | %ENC28J60_COMMENTS% #define ENC_SPI_IF (IFS0bits.SPI1RXIF) |
||
| 875 | %ENC28J60_COMMENTS% #define ENC_SSPBUF (SPI1BUF) |
||
| 876 | %ENC28J60_COMMENTS% #define ENC_SPISTATbits (SPI1STATbits) |
||
| 877 | %ENC28J60_COMMENTS% #define ENC_SPICON1 (SPI1CON) |
||
| 878 | %ENC28J60_COMMENTS% #define ENC_SPICON1bits (SPI1CONbits) |
||
| 879 | %ENC28J60_COMMENTS% #define ENC_SPIBRG (SPI1BRG) |
||
| 880 | %ENC28J60_COMMENTS% #endif |
||
| 881 | %ENC28J60_COMMENTS% #endif |
||
| 882 | |||
| 883 | |||
| 884 | %ENC100_COMMENTS% // ENC624J600 Interface Configuration |
||
| 885 | %ENC100_COMMENTS% // Comment out ENC100_INTERFACE_MODE if you don't have an ENC624J600 or |
||
| 886 | %ENC100_COMMENTS% // ENC424J600. Otherwise, choose the correct setting for the interface you |
||
| 887 | %ENC100_COMMENTS% // are using. Legal values are: |
||
| 888 | %ENC100_COMMENTS% // - Commented out: No ENC424J600/624J600 present or used. All other |
||
| 889 | %ENC100_COMMENTS% // ENC100_* macros are ignored. |
||
| 890 | %ENC100_COMMENTS% // - 0: SPI mode using CS, SCK, SI, and SO pins |
||
| 891 | %ENC100_COMMENTS% // - 1: 8-bit demultiplexed PSP Mode 1 with RD and WR pins |
||
| 892 | %ENC100_COMMENTS% // - 2: *8-bit demultiplexed PSP Mode 2 with R/Wbar and EN pins |
||
| 893 | %ENC100_COMMENTS% // - 3: *16-bit demultiplexed PSP Mode 3 with RD, WRL, and WRH pins |
||
| 894 | %ENC100_COMMENTS% // - 4: *16-bit demultiplexed PSP Mode 4 with R/Wbar, B0SEL, and B1SEL pins |
||
| 895 | %ENC100_COMMENTS% // - 5: 8-bit multiplexed PSP Mode 5 with RD and WR pins |
||
| 896 | %ENC100_COMMENTS% // - 6: *8-bit multiplexed PSP Mode 6 with R/Wbar and EN pins |
||
| 897 | %ENC100_COMMENTS% // - 9: 16-bit multiplexed PSP Mode 9 with AL, RD, WRL, and WRH pins |
||
| 898 | %ENC100_COMMENTS% // - 10: *16-bit multiplexed PSP Mode 10 with AL, R/Wbar, B0SEL, and B1SEL |
||
| 899 | %ENC100_COMMENTS% // pins |
||
| 900 | %ENC100_COMMENTS% // *IMPORTANT NOTE: DO NOT USE PSP MODE 2, 4, 6, OR 10 ON EXPLORER 16! |
||
| 901 | %ENC100_COMMENTS% // Attempting to do so will cause bus contention with the LCD module which |
||
| 902 | %ENC100_COMMENTS% // shares the PMP. Also, PSP Mode 3 is risky on the Explorer 16 since it |
||
| 903 | %ENC100_COMMENTS% // can randomly cause bus contention with the 25LC256 EEPROM. |
||
| 904 | %ENC100_COMMENTS% #define ENC100_INTERFACE_MODE %ENC100_INTERFACE_MODE% |
||
| 905 | %ENC100_COMMENTS% |
||
| 906 | %ENC100_COMMENTS% // If using a parallel interface, direct RAM addressing can be used (if all |
||
| 907 | %ENC100_COMMENTS% // addresses wires are connected), or a reduced number of pins can be used |
||
| 908 | %ENC100_COMMENTS% // for indirect addressing. If using an SPI interface or PSP Mode 9 or 10 |
||
| 909 | %ENC100_COMMENTS% // (multiplexed 16-bit modes), which require all address lines to always be |
||
| 910 | %ENC100_COMMENTS% // connected, then this option is ignored. Comment out or uncomment this |
||
| 911 | %ENC100_COMMENTS% // macro to match your hardware connections. |
||
| 912 | %ENC100_COMMENTS% #define ENC100_PSP_USE_INDIRECT_RAM_ADDRESSING |
||
| 913 | %ENC100_COMMENTS% |
||
| 914 | %ENC100_COMMENTS% // ENC424J600/624J600 parallel indirect address remapping macro function. |
||
| 915 | %ENC100_COMMENTS% // This section translates SFR and RAM addresses presented to the |
||
| 916 | %ENC100_COMMENTS% // ReadMemory() and WriteMemory() APIs in ENCX24J600.c to the actual |
||
| 917 | %ENC100_COMMENTS% // addresses that must be presented on the parallel interface. This macro |
||
| 918 | %ENC100_COMMENTS% // must be modified to match your hardware if you are using an indirect PSP |
||
| 919 | %ENC100_COMMENTS% // addressing mode (ENC100_PSP_USE_INDIRECT_RAM_ADDRESSING is defined) and |
||
| 920 | %ENC100_COMMENTS% // have some of your address lines tied off to Vdd. If you are using the |
||
| 921 | %ENC100_COMMENTS% // SPI interface, then this section can be ignored or deleted. |
||
| 922 | %ENC100_COMMENTS% #if (ENC100_INTERFACE_MODE == 1) || (ENC100_INTERFACE_MODE == 2) || (ENC100_INTERFACE_MODE == 5) || (ENC100_INTERFACE_MODE == 6) // 8-bit PSP |
||
| 923 | %ENC100_COMMENTS% #define ENC100_TRANSLATE_TO_PIN_ADDR(a) ((((a)&0x0100)<<6) | ((a)&0x00FF)) |
||
| 924 | %ENC100_COMMENTS% #elif (ENC100_INTERFACE_MODE == 3) || (ENC100_INTERFACE_MODE == 4) // 16-bit PSP |
||
| 925 | %ENC100_COMMENTS% #define ENC100_TRANSLATE_TO_PIN_ADDR(a) (a) |
||
| 926 | %ENC100_COMMENTS% #endif |
||
| 927 | %ENC100_COMMENTS% |
||
| 928 | %ENC100_COMMENTS% // Auto-crossover pins on Fast 100Mbps Ethernet PICtail/PICtail Plus. If |
||
| 929 | %ENC100_COMMENTS% // your circuit doesn't have such a feature, delete these two defines. |
||
| 930 | %ENC100_COMMENTS% #define ENC100_MDIX_TRIS (TRISBbits.TRISB3) |
||
| 931 | %ENC100_COMMENTS% #define ENC100_MDIX_IO (LATBbits.LATB3) |
||
| 932 | %ENC100_COMMENTS% |
||
| 933 | %ENC100_COMMENTS% // ENC624J600 I/O control and status pins |
||
| 934 | %ENC100_COMMENTS% // If a pin is not required for your selected ENC100_INTERFACE_MODE |
||
| 935 | %ENC100_COMMENTS% // interface selection (ex: WRH/B1SEL for PSP modes 1, 2, 5, and 6), then |
||
| 936 | %ENC100_COMMENTS% // you can ignore, delete, or put anything for the pin definition. Also, |
||
| 937 | %ENC100_COMMENTS% // the INT and POR pins are entirely optional. If not connected, comment |
||
| 938 | %ENC100_COMMENTS% // them out. |
||
| 939 | %ENC100_COMMENTS% #if defined(__dsPIC33FJ256GP710__) || defined(__PIC24HJ256GP610__) |
||
| 940 | %ENC100_COMMENTS% #define ENC100_INT_TRIS (TRISAbits.TRISA13) // INT signal is optional and currently unused in the Microchip TCP/IP Stack. Leave this pin disconnected and comment out this pin definition if you don't want it. |
||
| 941 | %ENC100_COMMENTS% #define ENC100_INT_IO (PORTAbits.RA13) |
||
| 942 | %ENC100_COMMENTS% #else |
||
| 943 | %ENC100_COMMENTS% #define ENC100_INT_TRIS (TRISEbits.TRISE9) // INT signal is optional and currently unused in the Microchip TCP/IP Stack. Leave this pin disconnected and comment out this pin definition if you don't want it. |
||
| 944 | %ENC100_COMMENTS% #define ENC100_INT_IO (PORTEbits.RE9) |
||
| 945 | %ENC100_COMMENTS% #endif |
||
| 946 | %ENC100_COMMENTS% #if (ENC100_INTERFACE_MODE >= 1) // Parallel mode |
||
| 947 | %ENC100_COMMENTS% // PSP control signal pinout |
||
| 948 | %ENC100_COMMENTS% #define ENC100_CS_TRIS (TRISAbits.TRISA5) // CS is optional in PSP mode. If you are not sharing the parallel bus with another device, tie CS to Vdd and comment out this pin definition. |
||
| 949 | %ENC100_COMMENTS% #define ENC100_CS_IO (LATAbits.LATA5) |
||
| 950 | %ENC100_COMMENTS% #define ENC100_POR_TRIS (TRISCbits.TRISC1) // POR signal is optional. If your application doesn't have a power disconnect feature, comment out this pin definition. |
||
| 951 | %ENC100_COMMENTS% #define ENC100_POR_IO (LATCbits.LATC1) |
||
| 952 | %ENC100_COMMENTS% #define ENC100_SO_WR_B0SEL_EN_TRIS (TRISDbits.TRISD4) |
||
| 953 | %ENC100_COMMENTS% #define ENC100_SO_WR_B0SEL_EN_IO (LATDbits.LATD4) |
||
| 954 | %ENC100_COMMENTS% #define ENC100_SI_RD_RW_TRIS (TRISDbits.TRISD5) |
||
| 955 | %ENC100_COMMENTS% #define ENC100_SI_RD_RW_IO (LATDbits.LATD5) |
||
| 956 | %ENC100_COMMENTS% #define ENC100_SCK_AL_TRIS (TRISBbits.TRISB15) |
||
| 957 | %ENC100_COMMENTS% #define ENC100_SCK_AL_IO (LATBbits.LATB15) |
||
| 958 | %ENC100_COMMENTS% #else |
||
| 959 | %ENC100_COMMENTS% // SPI pinout |
||
| 960 | %ENC100_COMMENTS% #if defined(__PIC24FJ256GA110__) // The PIC24FJ256GA110 must use SPI2 slot on Explorer 16. If you don't have a PIC24FJ256GA110 but want to use SPI2 for some reason, you can use these definitions. |
||
| 961 | %ENC100_COMMENTS% #define ENC100_CS_TRIS (TRISFbits.TRISF12) // CS is mandatory when using the SPI interface |
||
| 962 | %ENC100_COMMENTS% #define ENC100_CS_IO (LATFbits.LATF12) |
||
| 963 | %ENC100_COMMENTS% #define ENC100_POR_TRIS (TRISFbits.TRISF13) // POR signal is optional. If your application doesn't have a power disconnect feature, comment out this pin definition. |
||
| 964 | %ENC100_COMMENTS% #define ENC100_POR_IO (LATFbits.LATF13) |
||
| 965 | %ENC100_COMMENTS% #else // All other PIC24s, dsPICs, and PIC32s use SPI1 slot (top most closest to LCD) |
||
| 966 | %ENC100_COMMENTS% #define ENC100_CS_TRIS (TRISDbits.TRISD14) // CS is mandatory when using the SPI interface |
||
| 967 | %ENC100_COMMENTS% #define ENC100_CS_IO (LATDbits.LATD14) |
||
| 968 | %ENC100_COMMENTS% #define ENC100_POR_TRIS (TRISDbits.TRISD15) // POR signal is optional. If your application doesn't have a power disconnect feature, comment out this pin definition. |
||
| 969 | %ENC100_COMMENTS% #define ENC100_POR_IO (LATDbits.LATD15) |
||
| 970 | %ENC100_COMMENTS% #endif |
||
| 971 | %ENC100_COMMENTS% #endif |
||
| 972 | %ENC100_COMMENTS% |
||
| 973 | %ENC100_COMMENTS% // ENC624J600 Bit Bang PSP I/O macros and pin configuration for address and |
||
| 974 | %ENC100_COMMENTS% // data. If using the SPI interface (ENC100_INTERFACE_MODE is 0) then this |
||
| 975 | %ENC100_COMMENTS% // section is not used and can be ignored or deleted. If using the PIC PMP |
||
| 976 | %ENC100_COMMENTS% // hardware module (if present), then ENC100_BIT_BANG_PMP must be commented |
||
| 977 | %ENC100_COMMENTS% // out and the remaining definitions will be ignored/can be deleted. |
||
| 978 | %ENC100_COMMENTS% // Otherwise, if you are using a parallel interface mode, but do not have a |
||
| 979 | %ENC100_COMMENTS% // PMP (or want to interface using different pins), define |
||
| 980 | %ENC100_COMMENTS% // ENC100_BIT_BANG_PMP and properly configure the applicable macros. |
||
| 981 | %ENC100_COMMENTS% %ENC100_BIT_BANG_PMP%#define ENC100_BIT_BANG_PMP |
||
| 982 | %ENC100_COMMENTS% #if defined(ENC100_BIT_BANG_PMP) |
||
| 983 | %ENC100_COMMENTS% #if ENC100_INTERFACE_MODE == 1 || ENC100_INTERFACE_MODE == 2 // Dumultiplexed 8-bit address/data modes |
||
| 984 | %ENC100_COMMENTS% // SPI2 CANNOT BE ENABLED WHEN ACCESSING THE ENC624J600 FOR THESE TWO MODES AS THE PINS OVERLAP WITH ADDRESS LINES. |
||
| 985 | %ENC100_COMMENTS% #if defined(ENC100_PSP_USE_INDIRECT_RAM_ADDRESSING) // Only ENC624J600 address pins A0-A8 connected (A9-A14 tied to Vdd) |
||
| 986 | %ENC100_COMMENTS% #if defined(__PIC24FJ256GB210__) |
||
| 987 | %ENC100_COMMENTS% #define ENC100_INIT_PSP_BIT_BANG() do{ANSA &= 0xF9E7; ANSB &= 0x3FFF; ANSG &= 0xFCFF;} while(0) // RE0-RE7, RF12, RD11, RD4, RD5 (AD0-AD7, A5, A8, WR, RD) pins are already digital only pins. |
||
| 988 | %ENC100_COMMENTS% #else |
||
| 989 | %ENC100_COMMENTS% #define ENC100_INIT_PSP_BIT_BANG() do{((volatile BYTE*)&AD1PCFGH)[1] = 0xFF; ((volatile BYTE*)&AD1PCFGL)[1] |= 0xC0;}while(0) // Disable AN24-AN31 and AN14-AN15 analog inputs on RE0-RE7 and RB14-RB15 pins (ENCX24J600 AD0-AD7, A1-A0) |
||
| 990 | %ENC100_COMMENTS% #endif |
||
| 991 | %ENC100_COMMENTS% #define ENC100_SET_ADDR_TRIS_OUT() do{TRISA &= 0xF9E7; TRISB &= 0x3FFF; TRISFbits.TRISF12 = 0; TRISGbits.TRISG9 = 0; TRISDbits.TRISD11 = 0;}while(0) |
||
| 992 | %ENC100_COMMENTS% #define ENC100_SET_ADDR_IO(a) do{WORD _SetMacro = (a); LATBbits.LATB15 = 0; LATBbits.LATB14 = 0; LATGbits.LATG9 = 0; LATA &= 0xF9E7; LATFbits.LATF12 = 0; LATDbits.LATD11 = 0; if(_SetMacro & 0x0001) LATBbits.LATB15 = 1; if(_SetMacro & 0x0002) LATBbits.LATB14 = 1; if(_SetMacro & 0x0004) LATGbits.LATG9 = 1; if(_SetMacro & 0x0008) LATAbits.LATA4 = 1; if(_SetMacro & 0x0010) LATAbits.LATA3 = 1; if(_SetMacro & 0x0020) LATFbits.LATF12 = 1; if(_SetMacro & 0x0040) LATAbits.LATA10 = 1; if(_SetMacro & 0x0080) LATAbits.LATA9 = 1; if(_SetMacro & 0x4000) LATDbits.LATD11 = 1;}while(0) |
||
| 993 | %ENC100_COMMENTS% #define ENC100_SET_AD_TRIS_IN() (((volatile BYTE*)&TRISE)[0] = 0xFF) |
||
| 994 | %ENC100_COMMENTS% #define ENC100_SET_AD_TRIS_OUT() (((volatile BYTE*)&TRISE)[0] = 0x00) |
||
| 995 | %ENC100_COMMENTS% #define ENC100_GET_AD_IO() (((volatile BYTE*)&PORTE)[0]) |
||
| 996 | %ENC100_COMMENTS% #define ENC100_SET_AD_IO(data) (((volatile BYTE*)&LATE)[0] = (BYTE)(data)) |
||
| 997 | %ENC100_COMMENTS% #else // All ENC624J600 address pins A0-A14 connected |
||
| 998 | %ENC100_COMMENTS% #if defined(__PIC24FJ256GB210__) |
||
| 999 | %ENC100_COMMENTS% #define ENC100_INIT_PSP_BIT_BANG() do{ANSA &= 0xF9E7; ANSB &= 0x03FF; ANSG &= 0xFCFF;} while(0) // RE0-RE7, RF12, RD11, RD4, RD5 (AD0-AD7, A5, A14, WR, RD) pins are already digital only pins. |
||
| 1000 | %ENC100_COMMENTS% #else |
||
| 1001 | %ENC100_COMMENTS% #define ENC100_INIT_PSP_BIT_BANG() do{((volatile BYTE*)&AD1PCFGH)[1] = 0xFF; ((volatile BYTE*)&AD1PCFGL)[1] |= 0xFC;}while(0) // Disable AN24-AN31 and AN10-AN15 analog inputs on RE0-RE7 and RB10-RB15 pins (ENCX24J600 AD0-AD7, A1-A0, A13-A10) |
||
| 1002 | %ENC100_COMMENTS% #endif |
||
| 1003 | %ENC100_COMMENTS% #define ENC100_SET_ADDR_TRIS_OUT() do{TRISA &= 0xF9E7; TRISB &= 0x03FF; TRISF &= 0xEFCF; TRISGbits.TRISG9 = 0; TRISDbits.TRISD11 = 0;}while(0) |
||
| 1004 | %ENC100_COMMENTS% #define ENC100_SET_ADDR_IO(a) do{WORD _SetMacro = (a); LATA &= 0xF9E7; LATB &= 0x03FF; LATF &= 0xEFCF; LATGbits.LATG9 = 0; LATDbits.LATD11 = 0; if(_SetMacro & 0x0001) LATBbits.LATB15 = 1; if(_SetMacro & 0x0002) LATBbits.LATB14 = 1; if(_SetMacro & 0x0004) LATGbits.LATG9 = 1; if(_SetMacro & 0x0008) LATAbits.LATA4 = 1; if(_SetMacro & 0x0010) LATAbits.LATA3 = 1; if(_SetMacro & 0x0020) LATFbits.LATF12 = 1; if(_SetMacro & 0x0040) LATAbits.LATA10 = 1; if(_SetMacro & 0x0080) LATAbits.LATA9 = 1; if(_SetMacro & 0x0100) LATFbits.LATF5 = 1; if(_SetMacro & 0x0200) LATFbits.LATF4 = 1; if(_SetMacro & 0x0400) LATBbits.LATB13 = 1; if(_SetMacro & 0x0800) LATBbits.LATB12 = 1; if(_SetMacro & 0x1000) LATBbits.LATB11 = 1; if(_SetMacro & 0x2000) LATBbits.LATB10 = 1; if(_SetMacro & 0x4000) LATDbits.LATD11 = 1;}while(0) |
||
| 1005 | %ENC100_COMMENTS% #define ENC100_SET_AD_TRIS_IN() (((volatile BYTE*)&TRISE)[0] = 0xFF) |
||
| 1006 | %ENC100_COMMENTS% #define ENC100_SET_AD_TRIS_OUT() (((volatile BYTE*)&TRISE)[0] = 0x00) |
||
| 1007 | %ENC100_COMMENTS% #define ENC100_GET_AD_IO() (((volatile BYTE*)&PORTE)[0]) |
||
| 1008 | %ENC100_COMMENTS% #define ENC100_SET_AD_IO(data) (((volatile BYTE*)&LATE)[0] = (BYTE)(data)) |
||
| 1009 | %ENC100_COMMENTS% #endif |
||
| 1010 | %ENC100_COMMENTS% #elif ENC100_INTERFACE_MODE == 3 || ENC100_INTERFACE_MODE == 4 // Dumultiplexed 16-bit address/data modes |
||
| 1011 | %ENC100_COMMENTS% #if defined(ENC100_PSP_USE_INDIRECT_RAM_ADDRESSING) // Only ENC624J600 address pins A0-A7 connected (A8-A13 tied to Vdd) |
||
| 1012 | %ENC100_COMMENTS% #if defined(__PIC24FJ256GB210__) |
||
| 1013 | %ENC100_COMMENTS% #define ENC100_INIT_PSP_BIT_BANG() do{ANSA &= 0x79E7; ANSB &= 0x3FFF; ANSD &= 0xCF0F; ANSG &= 0xFCFC;}while(0) |
||
| 1014 | %ENC100_COMMENTS% #else |
||
| 1015 | %ENC100_COMMENTS% #define ENC100_INIT_PSP_BIT_BANG() do{AD1PCFGH = 0xFFFF; AD1PCFGL = 0xFFFF; AD2PCFGL = 0xFFFF;}while(0) |
||
| 1016 | %ENC100_COMMENTS% #endif |
||
| 1017 | %ENC100_COMMENTS% #define ENC100_SET_ADDR_TRIS_OUT() do{TRISA &= 0xF9E7; TRISBbits.TRISB15 = 0; TRISBbits.TRISB14 = 0; TRISFbits.TRISF12 = 0; TRISGbits.TRISG9 = 0;}while(0) |
||
| 1018 | %ENC100_COMMENTS% #define ENC100_SET_ADDR_IO(a) do{WORD _wSetMacro = (a); LATA &= 0xF9E7; LATBbits.LATB15 = 0; LATBbits.LATB14 = 0; LATFbits.LATF12 = 0; LATGbits.LATG9 = 0; if(_wSetMacro & 0x0001) LATBbits.LATB15 = 1; if(_wSetMacro & 0x0002) LATBbits.LATB14 = 1; if(_wSetMacro & 0x0004) LATGbits.LATG9 = 1; if(_wSetMacro & 0x0008) LATAbits.LATA4 = 1; if(_wSetMacro & 0x0010) LATAbits.LATA3 = 1; if(_wSetMacro & 0x0020) LATFbits.LATF12 = 1; if(_wSetMacro & 0x0040) LATAbits.LATA10 = 1; if(_wSetMacro & 0x0080) LATAbits.LATA9 = 1;}while(0) |
||
| 1019 | %ENC100_COMMENTS% #define ENC100_WRH_B1SEL_TRIS ENC100_SO_WR_B0SEL_EN_TRIS |
||
| 1020 | %ENC100_COMMENTS% #define ENC100_WRH_B1SEL_IO ENC100_SO_WR_B0SEL_EN_IO |
||
| 1021 | %ENC100_COMMENTS% #define ENC100_SET_AD_TRIS_IN() do{((volatile BYTE*)&TRISE)[0] = 0xFF; TRISAbits.TRISA15 = 1; TRISCbits.TRISC13 = 1; TRISD |= 0x30C0; TRISGbits.TRISG0 = 1; TRISGbits.TRISG1 = 1;}while(0) |
||
| 1022 | %ENC100_COMMENTS% #define ENC100_SET_AD_TRIS_OUT() do{((volatile BYTE*)&TRISE)[0] = 0x00; TRISAbits.TRISA15 = 0; TRISCbits.TRISC13 = 0; TRISD &= 0xCF3F; TRISGbits.TRISG0 = 0; TRISGbits.TRISG1 = 0;}while(0) |
||
| 1023 | %ENC100_COMMENTS% #define ENC100_GET_AD_IOH() (PORTGbits.RG0 | (PORTGbits.RG1<<1) | (PORTCbits.RC13<<2) | (PORTAbits.RA15<<3) | (PORTDbits.RD12<<4) | (PORTDbits.RD13<<5) | (PORTDbits.RD6<<6) | (PORTDbits.RD7<<7)) |
||
| 1024 | %ENC100_COMMENTS% #define ENC100_GET_AD_IOL() (((volatile BYTE*)&PORTE)[0]) |
||
| 1025 | %ENC100_COMMENTS% #define ENC100_SET_AD_IO(data) do{WORD _wSetMacro = (data); ((volatile BYTE*)&LATE)[0] = ((BYTE*)&_wSetMacro)[0]; LATG &= 0xFFFC; LATCbits.LATC13 = 0; LATAbits.LATA15 = 0; LATD &= 0xCF3F; if(_wSetMacro & 0x0100) LATGbits.LATG0 = 1; if(_wSetMacro & 0x0200) LATGbits.LATG1 = 1; if(_wSetMacro & 0x0400) LATCbits.LATC13 = 1; if(_wSetMacro & 0x0800) LATAbits.LATA15 = 1; if(_wSetMacro & 0x1000) LATDbits.LATD12 = 1; if(_wSetMacro & 0x2000) LATDbits.LATD13 = 1; if(_wSetMacro & 0x4000) LATDbits.LATD6 = 1; if(_wSetMacro & 0x8000) LATDbits.LATD7 = 1;}while(0) |
||
| 1026 | %ENC100_COMMENTS% #define ENC100_SET_AD_IOL(data) (((volatile BYTE*)&LATE)[0] = (BYTE)(data)) |
||
| 1027 | %ENC100_COMMENTS% #else // All ENC624J600 address pins A0-A13 connected |
||
| 1028 | %ENC100_COMMENTS% #if defined(__PIC24FJ256GB210__) |
||
| 1029 | %ENC100_COMMENTS% #define ENC100_INIT_PSP_BIT_BANG() do{ANSA &= 0x79E7; ANSB &= 0x03FF; ANSD &= 0xCF0F; ANSG &= 0xFCFC;}while(0) |
||
| 1030 | %ENC100_COMMENTS% #else |
||
| 1031 | %ENC100_COMMENTS% #define ENC100_INIT_PSP_BIT_BANG() do{AD1PCFGH = 0xFFFF; AD1PCFGL = 0xFFFF; AD2PCFGL = 0xFFFF;}while(0) |
||
| 1032 | %ENC100_COMMENTS% #endif |
||
| 1033 | %ENC100_COMMENTS% #define ENC100_SET_ADDR_TRIS_OUT() do{TRISA &= 0xF9E7; TRISB &= 0x03FF; TRISF &= 0xEFCF; TRISGbits.TRISG9 = 0;}while(0) |
||
| 1034 | %ENC100_COMMENTS% #define ENC100_SET_ADDR_IO(a) do{WORD _wSetMacro = (a); LATA &= 0xF9E7; LATB &= 0x03FF; LATF &= 0xEFCF; LATGbits.LATG9 = 0; if(_wSetMacro & 0x0001) LATBbits.LATB15 = 1; if(_wSetMacro & 0x0002) LATBbits.LATB14 = 1; if(_wSetMacro & 0x0004) LATGbits.LATG9 = 1; if(_wSetMacro & 0x0008) LATAbits.LATA4 = 1; if(_wSetMacro & 0x0010) LATAbits.LATA3 = 1; if(_wSetMacro & 0x0020) LATFbits.LATF12 = 1; if(_wSetMacro & 0x0040) LATAbits.LATA10 = 1; if(_wSetMacro & 0x0080) LATAbits.LATA9 = 1; if(_wSetMacro & 0x0100) LATFbits.LATF5 = 1; if(_wSetMacro & 0x0200) LATFbits.LATF4 = 1; if(_wSetMacro & 0x0400) LATBbits.LATB13 = 1; if(_wSetMacro & 0x0800) LATBbits.LATB12 = 1; if(_wSetMacro & 0x1000) LATBbits.LATB11 = 1; if(_wSetMacro & 0x2000) LATBbits.LATB10 = 1;}while(0) |
||
| 1035 | %ENC100_COMMENTS% #define ENC100_WRH_B1SEL_TRIS ENC100_SO_WR_B0SEL_EN_TRIS |
||
| 1036 | %ENC100_COMMENTS% #define ENC100_WRH_B1SEL_IO ENC100_SO_WR_B0SEL_EN_IO |
||
| 1037 | %ENC100_COMMENTS% #define ENC100_SET_AD_TRIS_IN() do{((volatile BYTE*)&TRISE)[0] = 0xFF; TRISAbits.TRISA15 = 1; TRISCbits.TRISC13 = 1; TRISD |= 0x30C0; TRISGbits.TRISG0 = 1; TRISGbits.TRISG1 = 1;}while(0) |
||
| 1038 | %ENC100_COMMENTS% #define ENC100_SET_AD_TRIS_OUT() do{((volatile BYTE*)&TRISE)[0] = 0x00; TRISAbits.TRISA15 = 0; TRISCbits.TRISC13 = 0; TRISD &= 0xCF3F; TRISGbits.TRISG0 = 0; TRISGbits.TRISG1 = 0;}while(0) |
||
| 1039 | %ENC100_COMMENTS% #define ENC100_GET_AD_IOH() (PORTGbits.RG0 | (PORTGbits.RG1<<1) | (PORTCbits.RC13<<2) | (PORTAbits.RA15<<3) | (PORTDbits.RD12<<4) | (PORTDbits.RD13<<5) | (PORTDbits.RD6<<6) | (PORTDbits.RD7<<7)) |
||
| 1040 | %ENC100_COMMENTS% #define ENC100_GET_AD_IOL() (((volatile BYTE*)&PORTE)[0]) |
||
| 1041 | %ENC100_COMMENTS% #define ENC100_SET_AD_IO(data) do{WORD _wSetMacro = (data); ((volatile BYTE*)&LATE)[0] = ((BYTE*)&_wSetMacro)[0]; LATG &= 0xFFFC; LATCbits.LATC13 = 0; LATAbits.LATA15 = 0; LATD &= 0xCF3F; if(_wSetMacro & 0x0100) LATGbits.LATG0 = 1; if(_wSetMacro & 0x0200) LATGbits.LATG1 = 1; if(_wSetMacro & 0x0400) LATCbits.LATC13 = 1; if(_wSetMacro & 0x0800) LATAbits.LATA15 = 1; if(_wSetMacro & 0x1000) LATDbits.LATD12 = 1; if(_wSetMacro & 0x2000) LATDbits.LATD13 = 1; if(_wSetMacro & 0x4000) LATDbits.LATD6 = 1; if(_wSetMacro & 0x8000) LATDbits.LATD7 = 1;}while(0) |
||
| 1042 | %ENC100_COMMENTS% #define ENC100_SET_AD_IOL(data) (((volatile BYTE*)&LATE)[0] = (BYTE)(data)) |
||
| 1043 | %ENC100_COMMENTS% #endif |
||
| 1044 | %ENC100_COMMENTS% #elif ENC100_INTERFACE_MODE == 5 || ENC100_INTERFACE_MODE == 6 // Mutliplexed 8-bit address/data modes |
||
| 1045 | %ENC100_COMMENTS% #if defined(ENC100_PSP_USE_INDIRECT_RAM_ADDRESSING) // Only ENCX24J600 address pins AD0-AD8 connected (AD9-AD14 tied to Vdd) |
||
| 1046 | %ENC100_COMMENTS% #if defined(__PIC24FJ256GB210__) |
||
| 1047 | %ENC100_COMMENTS% #define ENC100_INIT_PSP_BIT_BANG() do{ANSB &= 0x7FFF; ANSG &= 0xFEFF;} while(0) // RE0-RE7, RD11, RD4, RD5 (AD0-AD7, AD8, WR, RD) pins are already digital only pins. RB15, RG8 (AL, CS) needs to be made digital only. |
||
| 1048 | %ENC100_COMMENTS% #else |
||
| 1049 | %ENC100_COMMENTS% #define ENC100_INIT_PSP_BIT_BANG() do{((volatile BYTE*)&AD1PCFGH)[1] = 0xFF;}while(0) // Disable AN24-AN31 analog inputs on RE0-RE7 pins (ENCX24J600 AD0-AD7) |
||
| 1050 | %ENC100_COMMENTS% #endif |
||
| 1051 | %ENC100_COMMENTS% #define ENC100_SET_AD_TRIS_IN() do{((volatile BYTE*)&TRISE)[0] = 0xFF;}while(0) |
||
| 1052 | %ENC100_COMMENTS% #define ENC100_SET_AD_TRIS_OUT() do{((volatile BYTE*)&TRISE)[0] = 0x00; TRISDbits.TRISD11 = 0;}while(0) |
||
| 1053 | %ENC100_COMMENTS% #define ENC100_GET_AD_IO() (((volatile BYTE*)&PORTE)[0]) |
||
| 1054 | %ENC100_COMMENTS% #define ENC100_SET_AD_IO(data) do{WORD _wSetMacro = (data); ((volatile BYTE*)&LATE)[0] = (BYTE)_wSetMacro; LATDbits.LATD11 = 0; if(_wSetMacro & 0x4000) LATDbits.LATD11 = 1;}while(0) |
||
| 1055 | %ENC100_COMMENTS% #define ENC100_SET_AD_IOL(data) (((volatile BYTE*)&LATE)[0] = (BYTE)(data)) |
||
| 1056 | %ENC100_COMMENTS% #else // All ENCX24J600 address pins AD0-AD14 connected |
||
| 1057 | %ENC100_COMMENTS% // This pinout is bad for doing 8-bit bit-bang operations with all address lines. The Fast 100Mbps Ethernet PICtail Plus hardware is wired for PMP hardware support, which requires this pinout. However, if you are designing a custom board, you can simplify these read/write operations dramatically if you wire things more logically by putting all 15 I/O pins, in order, on PORTB or PORTD. Such a change would enhance performance. |
||
| 1058 | %ENC100_COMMENTS% // UART2 CANNOT BE USED OR ENABLED FOR THESE TWO MODES AS THE PINS OVERLAP WITH ADDRESS LINES. |
||
| 1059 | %ENC100_COMMENTS% #if defined(__PIC24FJ256GB210__) |
||
| 1060 | %ENC100_COMMENTS% #define ENC100_INIT_PSP_BIT_BANG() do{ANSB &= 0x43FF; ANSG &= 0xFEFF;} while(0) // Set pins as digital I/Os (not analog). RD11, RD5, RD4, RE0-RE7, RF4, RF5 are all digital-only pins and therefore no writes to ANSD, ANSE, or ANSF are needed. |
||
| 1061 | %ENC100_COMMENTS% #else |
||
| 1062 | %ENC100_COMMENTS% #define ENC100_INIT_PSP_BIT_BANG() do{AD1PCFGL |= 0x3C00; ((volatile BYTE*)&AD1PCFGH)[1] = 0xFF;}while(0) // Disable AN10-AN13 and AN24-AN31 analog inputs on RB10-RB13 and RE0-RE7 pins (ENCX24J600 AD13-AD10 and AD0-AD7) |
||
| 1063 | %ENC100_COMMENTS% #endif |
||
| 1064 | %ENC100_COMMENTS% #define ENC100_SET_AD_TRIS_IN() do{((volatile BYTE*)&TRISE)[0] = 0xFF;}while(0) |
||
| 1065 | %ENC100_COMMENTS% #define ENC100_SET_AD_TRIS_OUT() do{((volatile BYTE*)&TRISE)[0] = 0x00; TRISFbits.TRISF5 = 0; TRISFbits.TRISF4 = 0; TRISB &= 0x43FF; TRISDbits.TRISD11 = 0;}while(0) |
||
| 1066 | %ENC100_COMMENTS% #define ENC100_GET_AD_IO() (((volatile BYTE*)&PORTE)[0]) |
||
| 1067 | %ENC100_COMMENTS% #define ENC100_SET_AD_IO(data) do{WORD _wSetMacro = (data); ((volatile BYTE*)&LATE)[0] = (BYTE)_wSetMacro; LATFbits.LATF5 = 0; LATFbits.LATF4 = 0; LATB &= 0x43FF; LATDbits.LATD11 = 0; if(_wSetMacro & 0x0100) LATFbits.LATF5 = 1; if(_wSetMacro & 0x0200) LATFbits.LATF4 = 1; if(_wSetMacro & 0x0400) LATBbits.LATB13 = 1; if(_wSetMacro & 0x0800) LATBbits.LATB12 = 1; if(_wSetMacro & 0x1000) LATBbits.LATB11 = 1; if(_wSetMacro & 0x2000) LATBbits.LATB10 = 1; if(_wSetMacro & 0x4000) LATDbits.LATD11 = 1;}while(0) |
||
| 1068 | %ENC100_COMMENTS% #define ENC100_SET_AD_IOL(data) (((volatile BYTE*)&LATE)[0] = (BYTE)(data)) |
||
| 1069 | %ENC100_COMMENTS% #endif |
||
| 1070 | %ENC100_COMMENTS% #elif ENC100_INTERFACE_MODE == 9 || ENC100_INTERFACE_MODE == 10 // Mutliplexed 16-bit address/data modes |
||
| 1071 | %ENC100_COMMENTS% // All ENC624J600 adddress/data pins AD0-AD15 connected (required for 16-bit data, so there is no differentiation for indirect versus direct addressing mode) |
||
| 1072 | %ENC100_COMMENTS% // This pinout is awful for doing 16-bit bit-bang operations. The Fast 100Mbps Ethernet PICtail Plus hardware is wired for PMP hardware support, which requires this pinout. However, if you are designing a custom board, you can simplify these read/write operations dramatically if you wire things more logically by putting all 16 I/O pins, in order, on PORTB or PORTD. Such a change would enhance performance. |
||
| 1073 | %ENC100_COMMENTS% #if defined(__PIC24FJ256GB210__) |
||
| 1074 | %ENC100_COMMENTS% #define ENC100_INIT_PSP_BIT_BANG() do{ANSBbits.ANSB15 = 0; ANSCbits.ANSC13 = 0; ANSD &= 0xCF0F; ANSGbits.ANSG8 = 0;}while(0) // Set pins as digital I/Os (not analog). RA15 and RE0-RE7 are all digital-only pins and therefore no writes to ANSA or ANSE are needed. |
||
| 1075 | %ENC100_COMMENTS% #else |
||
| 1076 | %ENC100_COMMENTS% #define ENC100_INIT_PSP_BIT_BANG() do{((volatile BYTE*)&AD1PCFGH)[1] = 0xFF;}while(0) // Disable AN24-AN31 analog inputs on RE0-RE7 pins (ENCX24J600 AD0-AD7) |
||
| 1077 | %ENC100_COMMENTS% #endif |
||
| 1078 | %ENC100_COMMENTS% #define ENC100_WRH_B1SEL_TRIS ENC100_SO_WR_B0SEL_EN_TRIS |
||
| 1079 | %ENC100_COMMENTS% #define ENC100_WRH_B1SEL_IO ENC100_SO_WR_B0SEL_EN_IO |
||
| 1080 | %ENC100_COMMENTS% #define ENC100_SET_AD_TRIS_IN() do{((volatile BYTE*)&TRISE)[0] = 0xFF; TRISAbits.TRISA15 = 1; TRISCbits.TRISC13 = 1; TRISD |= 0x30C0; TRISGbits.TRISG0 = 1; TRISGbits.TRISG1 = 1;}while(0) |
||
| 1081 | %ENC100_COMMENTS% #define ENC100_SET_AD_TRIS_OUT() do{((volatile BYTE*)&TRISE)[0] = 0x00; TRISAbits.TRISA15 = 0; TRISCbits.TRISC13 = 0; TRISD &= 0xCF3F; TRISGbits.TRISG0 = 0; TRISGbits.TRISG1 = 0;}while(0) |
||
| 1082 | %ENC100_COMMENTS% #define ENC100_GET_AD_IOH() (PORTGbits.RG0 | (PORTGbits.RG1<<1) | (PORTCbits.RC13<<2) | (PORTAbits.RA15<<3) | (PORTDbits.RD12<<4) | (PORTDbits.RD13<<5) | (PORTDbits.RD6<<6) | (PORTDbits.RD7<<7)) |
||
| 1083 | %ENC100_COMMENTS% #define ENC100_GET_AD_IOL() (((volatile BYTE*)&PORTE)[0]) |
||
| 1084 | %ENC100_COMMENTS% #define ENC100_SET_AD_IO(data) do{WORD _wSetMacro = (data); ((volatile BYTE*)&LATE)[0] = ((BYTE*)&_wSetMacro)[0]; LATG &= 0xFFFC; LATCbits.LATC13 = 0; LATAbits.LATA15 = 0; LATD &= 0xCF3F; if(_wSetMacro & 0x0100) LATGbits.LATG0 = 1; if(_wSetMacro & 0x0200) LATGbits.LATG1 = 1; if(_wSetMacro & 0x0400) LATCbits.LATC13 = 1; if(_wSetMacro & 0x0800) LATAbits.LATA15 = 1; if(_wSetMacro & 0x1000) LATDbits.LATD12 = 1; if(_wSetMacro & 0x2000) LATDbits.LATD13 = 1; if(_wSetMacro & 0x4000) LATDbits.LATD6 = 1; if(_wSetMacro & 0x8000) LATDbits.LATD7 = 1;}while(0) |
||
| 1085 | %ENC100_COMMENTS% #define ENC100_SET_AD_IOL(data) (((volatile BYTE*)&LATE)[0] = (BYTE)(data)) |
||
| 1086 | %ENC100_COMMENTS% #endif |
||
| 1087 | %ENC100_COMMENTS% #endif |
||
| 1088 | %ENC100_COMMENTS% |
||
| 1089 | %ENC100_COMMENTS% // ENC624J600 SPI SFR register selection (controls which SPI peripheral to |
||
| 1090 | %ENC100_COMMENTS% // use on PICs with multiple SPI peripherals). If a parallel interface is |
||
| 1091 | %ENC100_COMMENTS% // used (ENC100_INTERFACE_MODE is >= 1), then the SPI is not used and this |
||
| 1092 | %ENC100_COMMENTS% // section can be ignored or deleted. |
||
| 1093 | %ENC100_COMMENTS% #if defined(__C30__) // PIC24F, PIC24H, dsPIC30, dsPIC33 |
||
| 1094 | %ENC100_COMMENTS% #if defined(__PIC24FJ256GA110__) // The PIC24FJ256GA110 must use SPI2 slot on Explorer 16. If you don't have a PIC24FJ256GA110 but want to use SPI2 for some reason, you can use these definitions. |
||
| 1095 | %ENC100_COMMENTS% #define ENC100_ISR_ENABLE (IEC3bits.INT4IE) |
||
| 1096 | %ENC100_COMMENTS% #define ENC100_ISR_FLAG (IFS3bits.INT4IF) |
||
| 1097 | %ENC100_COMMENTS% #define ENC100_ISR_POLARITY (INTCON2bits.INT4EP) |
||
| 1098 | %ENC100_COMMENTS% #define ENC100_ISR_PRIORITY (IPC13bits.INT4IP) |
||
| 1099 | %ENC100_COMMENTS% #define ENC100_SPI_ENABLE (ENC100_SPISTATbits.SPIEN) |
||
| 1100 | %ENC100_COMMENTS% #define ENC100_SPI_IF (IFS1bits.SPI2IF) |
||
| 1101 | %ENC100_COMMENTS% #define ENC100_SSPBUF (SPI2BUF) |
||
| 1102 | %ENC100_COMMENTS% #define ENC100_SPISTAT (SPI2STAT) |
||
| 1103 | %ENC100_COMMENTS% #define ENC100_SPISTATbits (SPI2STATbits) |
||
| 1104 | %ENC100_COMMENTS% #define ENC100_SPICON1 (SPI2CON1) |
||
| 1105 | %ENC100_COMMENTS% #define ENC100_SPICON1bits (SPI2CON1bits) |
||
| 1106 | %ENC100_COMMENTS% #define ENC100_SPICON2 (SPI2CON2) |
||
| 1107 | %ENC100_COMMENTS% #else // All other PIC24s and dsPICs use SPI1 slot (top most closest to LCD) |
||
| 1108 | %ENC100_COMMENTS% #define ENC100_ISR_ENABLE (IEC1bits.INT2IE) |
||
| 1109 | %ENC100_COMMENTS% #define ENC100_ISR_FLAG (IFS1bits.INT2IF) |
||
| 1110 | %ENC100_COMMENTS% #define ENC100_ISR_POLARITY (INTCON2bits.INT2EP) |
||
| 1111 | %ENC100_COMMENTS% #define ENC100_ISR_PRIORITY (IPC7bits.INT2IP) |
||
| 1112 | %ENC100_COMMENTS% #define ENC100_SPI_ENABLE (ENC100_SPISTATbits.SPIEN) |
||
| 1113 | %ENC100_COMMENTS% #define ENC100_SPI_IF (IFS0bits.SPI1IF) |
||
| 1114 | %ENC100_COMMENTS% #define ENC100_SSPBUF (SPI1BUF) |
||
| 1115 | %ENC100_COMMENTS% #define ENC100_SPISTAT (SPI1STAT) |
||
| 1116 | %ENC100_COMMENTS% #define ENC100_SPISTATbits (SPI1STATbits) |
||
| 1117 | %ENC100_COMMENTS% #define ENC100_SPICON1 (SPI1CON1) |
||
| 1118 | %ENC100_COMMENTS% #define ENC100_SPICON1bits (SPI1CON1bits) |
||
| 1119 | %ENC100_COMMENTS% #define ENC100_SPICON2 (SPI1CON2) |
||
| 1120 | %ENC100_COMMENTS% #endif |
||
| 1121 | %ENC100_COMMENTS% #else // PIC32MX |
||
| 1122 | %ENC100_COMMENTS% #define ENC100_ISR_ENABLE (IEC0bits.INT2IE) |
||
| 1123 | %ENC100_COMMENTS% #define ENC100_ISR_FLAG (IFS0bits.INT2IF) |
||
| 1124 | %ENC100_COMMENTS% #define ENC100_ISR_POLARITY (INTCONbits.INT2EP) |
||
| 1125 | %ENC100_COMMENTS% #define ENC100_ISR_PRIORITY (IPC2bits.INT2IP) |
||
| 1126 | %ENC100_COMMENTS% #define ENC100_SPI_ENABLE (ENC100_SPICON1bits.ON) |
||
| 1127 | %ENC100_COMMENTS% #define ENC100_SPI_IF (IFS0bits.SPI1RXIF) |
||
| 1128 | %ENC100_COMMENTS% #define ENC100_SSPBUF (SPI1BUF) |
||
| 1129 | %ENC100_COMMENTS% #define ENC100_SPICON1 (SPI1CON) |
||
| 1130 | %ENC100_COMMENTS% #define ENC100_SPISTATbits (SPI1STATbits) |
||
| 1131 | %ENC100_COMMENTS% #define ENC100_SPICON1bits (SPI1CONbits) |
||
| 1132 | %ENC100_COMMENTS% #define ENC100_SPIBRG (SPI1BRG) |
||
| 1133 | %ENC100_COMMENTS% #endif |
||
| 1134 | |||
| 1135 | |||
| 1136 | %EEPROM_COMMENTS% // 25LC256 I/O pins |
||
| 1137 | %EEPROM_COMMENTS% #if defined(__PIC24FJ256GB110__) |
||
| 1138 | %EEPROM_COMMENTS% // PIC24FJ256GB110 USB PIM has RD12 pin on Explorer 16 schematic |
||
| 1139 | %EEPROM_COMMENTS% // remapped and actually connected to PIC24FJ256GB110 pin 90 (RG0). |
||
| 1140 | %EEPROM_COMMENTS% #define EEPROM_CS_TRIS (TRISGbits.TRISG0) |
||
| 1141 | %EEPROM_COMMENTS% #define EEPROM_CS_IO (LATGbits.LATG0) |
||
| 1142 | %EEPROM_COMMENTS% #elif defined(__PIC24FJ256GB210__) |
||
| 1143 | %EEPROM_COMMENTS% // PIC24FJ256GB210 USB PIM has RD12 pin on Explorer 16 schematic |
||
| 1144 | %EEPROM_COMMENTS% // remapped and actually connected to PIC24FJ256GB210 pin 90 (RG0) when |
||
| 1145 | %EEPROM_COMMENTS% // JP1 on PIM has pins 1-2 shorted (USB). When JP1 pins 2-3 are shorted |
||
| 1146 | %EEPROM_COMMENTS% // (PMP), PIC pin 90 does connect to RD12. To make the PIM work with |
||
| 1147 | %EEPROM_COMMENTS% // either jumper setting, we will drive both RG0 and RD12 simultaneously |
||
| 1148 | %EEPROM_COMMENTS% // as chip select to the same states. For an actual application, you'd |
||
| 1149 | %EEPROM_COMMENTS% // want to specify only the single necessary pin as this double |
||
| 1150 | %EEPROM_COMMENTS% // assignment operation generates inefficient code by the C compiler. |
||
| 1151 | %EEPROM_COMMENTS% #define EEPROM_CS_TRIS TRISGbits.TRISG0 = TRISDbits.TRISD12 |
||
| 1152 | %EEPROM_COMMENTS% #define EEPROM_CS_IO LATGbits.LATG0 = LATDbits.LATD12 |
||
| 1153 | %EEPROM_COMMENTS% #else |
||
| 1154 | %EEPROM_COMMENTS% #define EEPROM_CS_TRIS (TRISDbits.TRISD12) |
||
| 1155 | %EEPROM_COMMENTS% #define EEPROM_CS_IO (LATDbits.LATD12) |
||
| 1156 | %EEPROM_COMMENTS% #endif |
||
| 1157 | %EEPROM_COMMENTS% #define EEPROM_SCK_TRIS (TRISGbits.TRISG6) |
||
| 1158 | %EEPROM_COMMENTS% #define EEPROM_SDI_TRIS (TRISGbits.TRISG7) |
||
| 1159 | %EEPROM_COMMENTS% #define EEPROM_SDO_TRIS (TRISGbits.TRISG8) |
||
| 1160 | %EEPROM_COMMENTS% #if defined(__C30__) // PIC24F, PIC24H, dsPIC30, dsPIC33 |
||
| 1161 | %EEPROM_COMMENTS% #define EEPROM_SPI_IF (IFS2bits.SPI2IF) |
||
| 1162 | %EEPROM_COMMENTS% #define EEPROM_SSPBUF (SPI2BUF) |
||
| 1163 | %EEPROM_COMMENTS% #define EEPROM_SPICON1 (SPI2CON1) |
||
| 1164 | %EEPROM_COMMENTS% #define EEPROM_SPICON1bits (SPI2CON1bits) |
||
| 1165 | %EEPROM_COMMENTS% #define EEPROM_SPICON2 (SPI2CON2) |
||
| 1166 | %EEPROM_COMMENTS% #define EEPROM_SPISTAT (SPI2STAT) |
||
| 1167 | %EEPROM_COMMENTS% #define EEPROM_SPISTATbits (SPI2STATbits) |
||
| 1168 | %EEPROM_COMMENTS% #else // PIC32 |
||
| 1169 | %EEPROM_COMMENTS% #define EEPROM_SPI_IF (IFS1bits.SPI2RXIF) |
||
| 1170 | %EEPROM_COMMENTS% #define EEPROM_SSPBUF (SPI2BUF) |
||
| 1171 | %EEPROM_COMMENTS% #define EEPROM_SPICON1 (SPI2CON) |
||
| 1172 | %EEPROM_COMMENTS% #define EEPROM_SPICON1bits (SPI2CONbits) |
||
| 1173 | %EEPROM_COMMENTS% #define EEPROM_SPIBRG (SPI2BRG) |
||
| 1174 | %EEPROM_COMMENTS% #define EEPROM_SPISTAT (SPI2STAT) |
||
| 1175 | %EEPROM_COMMENTS% #define EEPROM_SPISTATbits (SPI2STATbits) |
||
| 1176 | %EEPROM_COMMENTS% #endif |
||
| 1177 | |||
| 1178 | |||
| 1179 | // LCD Module I/O pins. NOTE: On the Explorer 16, the LCD is wired to the |
||
| 1180 | // same PMP lines required to communicate with an ENCX24J600 in parallel |
||
| 1181 | // mode. Since the LCD does not have a chip select wire, if you are using |
||
| 1182 | // the ENC424J600/624J600 in parallel mode, the LCD cannot be used. |
||
| 1183 | #if !defined(ENC100_INTERFACE_MODE) || (ENC100_INTERFACE_MODE == 0) // SPI only |
||
| 1184 | #define LCD_DATA_TRIS (*((volatile BYTE*)&TRISE)) |
||
| 1185 | #define LCD_DATA_IO (*((volatile BYTE*)&LATE)) |
||
| 1186 | #define LCD_RD_WR_TRIS (TRISDbits.TRISD5) |
||
| 1187 | #define LCD_RD_WR_IO (LATDbits.LATD5) |
||
| 1188 | #define LCD_RS_TRIS (TRISBbits.TRISB15) |
||
| 1189 | #define LCD_RS_IO (LATBbits.LATB15) |
||
| 1190 | #define LCD_E_TRIS (TRISDbits.TRISD4) |
||
| 1191 | #define LCD_E_IO (LATDbits.LATD4) |
||
| 1192 | #endif |
||
| 1193 | |||
| 1194 | |||
| 1195 | // // Serial Flash/SRAM/UART PICtail Plus attached to SPI2 (middle pin group) |
||
| 1196 | // // This daughter card is not in production, but if you custom attach an SPI |
||
| 1197 | // // RAM or SPI Flash chip to your board, then use these definitions as a |
||
| 1198 | // // starting point. |
||
| 1199 | // #define SPIRAM_CS_TRIS (TRISGbits.TRISG9) |
||
| 1200 | // #define SPIRAM_CS_IO (LATGbits.LATG9) |
||
| 1201 | // #define SPIRAM_SCK_TRIS (TRISGbits.TRISG6) |
||
| 1202 | // #define SPIRAM_SDI_TRIS (TRISGbits.TRISG7) |
||
| 1203 | // #define SPIRAM_SDO_TRIS (TRISGbits.TRISG8) |
||
| 1204 | // #if defined(__C30__) // PIC24F, PIC24H, dsPIC30, dsPIC33 |
||
| 1205 | // #define SPIRAM_SPI_IF (IFS2bits.SPI2IF) |
||
| 1206 | // #define SPIRAM_SSPBUF (SPI2BUF) |
||
| 1207 | // #define SPIRAM_SPICON1 (SPI2CON1) |
||
| 1208 | // #define SPIRAM_SPICON1bits (SPI2CON1bits) |
||
| 1209 | // #define SPIRAM_SPICON2 (SPI2CON2) |
||
| 1210 | // #define SPIRAM_SPISTAT (SPI2STAT) |
||
| 1211 | // #define SPIRAM_SPISTATbits (SPI2STATbits) |
||
| 1212 | // #else // PIC32 |
||
| 1213 | // #define SPIRAM_SPI_IF (IFS1bits.SPI2RXIF) |
||
| 1214 | // #define SPIRAM_SSPBUF (SPI2BUF) |
||
| 1215 | // #define SPIRAM_SPICON1 (SPI2CON) |
||
| 1216 | // #define SPIRAM_SPICON1bits (SPI2CONbits) |
||
| 1217 | // #define SPIRAM_SPIBRG (SPI2BRG) |
||
| 1218 | // #endif |
||
| 1219 | // |
||
| 1220 | // // NOTE: You must also set the SPI_FLASH_SST/SPI_FLASH_SPANSION, |
||
| 1221 | // // SPI_FLASH_SECTOR_SIZE, and SPI_FLASH_PAGE_SIZE macros in |
||
| 1222 | // // SPIFlash.h to match your particular Flash memory chip!!! |
||
| 1223 | // #define SPIFLASH_CS_TRIS (TRISBbits.TRISB8) |
||
| 1224 | // #define SPIFLASH_CS_IO (LATBbits.LATB8) |
||
| 1225 | // #define SPIFLASH_SCK_TRIS (TRISGbits.TRISG6) |
||
| 1226 | // #define SPIFLASH_SDI_TRIS (TRISGbits.TRISG7) |
||
| 1227 | // #define SPIFLASH_SDI_IO (PORTGbits.RG7) |
||
| 1228 | // #define SPIFLASH_SDO_TRIS (TRISGbits.TRISG8) |
||
| 1229 | // #if defined(__C30__) // PIC24F, PIC24H, dsPIC30, dsPIC33 |
||
| 1230 | // #define SPIFLASH_SPI_IF (IFS2bits.SPI2IF) |
||
| 1231 | // #define SPIFLASH_SSPBUF (SPI2BUF) |
||
| 1232 | // #define SPIFLASH_SPICON1 (SPI2CON1) |
||
| 1233 | // #define SPIFLASH_SPICON1bits (SPI2CON1bits) |
||
| 1234 | // #define SPIFLASH_SPICON2 (SPI2CON2) |
||
| 1235 | // #define SPIFLASH_SPISTAT (SPI2STAT) |
||
| 1236 | // #define SPIFLASH_SPISTATbits (SPI2STATbits) |
||
| 1237 | // #else // PIC32 |
||
| 1238 | // #define SPIFLASH_SPI_IF (IFS1bits.SPI2RXIF) |
||
| 1239 | // #define SPIFLASH_SSPBUF (SPI2BUF) |
||
| 1240 | // #define SPIFLASH_SPICON1 (SPI2CON) |
||
| 1241 | // #define SPIFLASH_SPICON1bits (SPI2CONbits) |
||
| 1242 | // #define SPIFLASH_SPISTATbits (SPI2STATbits) |
||
| 1243 | // #define SPIFLASH_SPIBRG (SPI2BRG) |
||
| 1244 | // #endif |
||
| 1245 | |||
| 1246 | %MRF24WB0M_COMMENTS% //---------------------------- |
||
| 1247 | %MRF24WB0M_COMMENTS% // MRF24WB0M WiFi I/O pins |
||
| 1248 | %MRF24WB0M_COMMENTS% //---------------------------- |
||
| 1249 | %MRF24WB0M_COMMENTS% // If you have a MRF24WB0M WiFi PICtail, you must uncomment one of |
||
| 1250 | %MRF24WB0M_COMMENTS% // these two lines to use it. SPI1 is the top-most slot in the Explorer 16 |
||
| 1251 | %MRF24WB0M_COMMENTS% // (closer to the LCD and prototyping area) while SPI2 corresponds to |
||
| 1252 | %MRF24WB0M_COMMENTS% // insertion of the PICtail into the middle of the side edge connector slot. |
||
| 1253 | %MRF24WB0M_COMMENTS% %MRF24WB0M_IN_SPI1%#define MRF24WB0M_IN_SPI1 |
||
| 1254 | %MRF24WB0M_COMMENTS% %MRF24WB0M_IN_SPI2%#define MRF24WB0M_IN_SPI2 |
||
| 1255 | %MRF24WB0M_COMMENTS% |
||
| 1256 | %MRF24WB0M_COMMENTS% // PIC24FJ256GA110 PIM on Explorer 16 must use SPI2, not SPI1 |
||
| 1257 | %MRF24WB0M_COMMENTS% #if defined(MRF24WB0M_IN_SPI1) && defined(__PIC24FJ256GA110__) |
||
| 1258 | %MRF24WB0M_COMMENTS% #undef MRF24WB0M_IN_SPI1 |
||
| 1259 | %MRF24WB0M_COMMENTS% #define MRF24WB0M_IN_SPI2 |
||
| 1260 | %MRF24WB0M_COMMENTS% #endif |
||
| 1261 | %MRF24WB0M_COMMENTS% |
||
| 1262 | %MRF24WB0M_COMMENTS% #if defined( MRF24WB0M_IN_SPI1 ) && !defined(__32MX460F512L__) && !defined(__32MX795F512L__) && !defined(__PIC24FJ256GA110__) |
||
| 1263 | %MRF24WB0M_COMMENTS% // MRF24WB0M in SPI1 slot |
||
| 1264 | %MRF24WB0M_COMMENTS% #define WF_CS_TRIS (TRISBbits.TRISB2) |
||
| 1265 | %MRF24WB0M_COMMENTS% #define WF_CS_IO (LATBbits.LATB2) |
||
| 1266 | %MRF24WB0M_COMMENTS% #define WF_SDI_TRIS (TRISFbits.TRISF7) |
||
| 1267 | %MRF24WB0M_COMMENTS% #define WF_SCK_TRIS (TRISFbits.TRISF6) |
||
| 1268 | %MRF24WB0M_COMMENTS% #define WF_SDO_TRIS (TRISFbits.TRISF8) |
||
| 1269 | %MRF24WB0M_COMMENTS% #define WF_RESET_TRIS (TRISFbits.TRISF0) |
||
| 1270 | %MRF24WB0M_COMMENTS% #define WF_RESET_IO (LATFbits.LATF0) |
||
| 1271 | %MRF24WB0M_COMMENTS% #if defined(__dsPIC33FJ256GP710__) || defined(__PIC24HJ256GP610__) |
||
| 1272 | %MRF24WB0M_COMMENTS% #define WF_INT_TRIS (TRISAbits.TRISA12) |
||
| 1273 | %MRF24WB0M_COMMENTS% #define WF_INT_IO (PORTAbits.RA12) |
||
| 1274 | %MRF24WB0M_COMMENTS% #else |
||
| 1275 | %MRF24WB0M_COMMENTS% #define WF_INT_TRIS (TRISEbits.TRISE8) // INT1 |
||
| 1276 | %MRF24WB0M_COMMENTS% #define WF_INT_IO (PORTEbits.RE8) |
||
| 1277 | %MRF24WB0M_COMMENTS% #endif |
||
| 1278 | %MRF24WB0M_COMMENTS% #define WF_HIBERNATE_TRIS (TRISFbits.TRISF1) |
||
| 1279 | %MRF24WB0M_COMMENTS% #define WF_HIBERNATE_IO (PORTFbits.RF1) |
||
| 1280 | %MRF24WB0M_COMMENTS% #if defined( __C30__ ) |
||
| 1281 | %MRF24WB0M_COMMENTS% #define WF_INT_EDGE (INTCON2bits.INT1EP) |
||
| 1282 | %MRF24WB0M_COMMENTS% #define WF_INT_IE (IEC1bits.INT1IE) |
||
| 1283 | %MRF24WB0M_COMMENTS% #define WF_INT_IF (IFS1bits.INT1IF) |
||
| 1284 | %MRF24WB0M_COMMENTS% #elif defined( __PIC32MX__ ) |
||
| 1285 | %MRF24WB0M_COMMENTS% #define WF_INT_EDGE (INTCONbits.INT1EP) |
||
| 1286 | %MRF24WB0M_COMMENTS% #define WF_INT_IE (IEC0bits.INT1IE) |
||
| 1287 | %MRF24WB0M_COMMENTS% #define WF_INT_IF (IFS0bits.INT1IF) |
||
| 1288 | %MRF24WB0M_COMMENTS% #define WF_INT_IE_CLEAR IEC0CLR |
||
| 1289 | %MRF24WB0M_COMMENTS% #define WF_INT_IF_CLEAR IFS0CLR |
||
| 1290 | %MRF24WB0M_COMMENTS% #define WF_INT_IE_SET IEC0SET |
||
| 1291 | %MRF24WB0M_COMMENTS% #define WF_INT_IF_SET IFS0SET |
||
| 1292 | %MRF24WB0M_COMMENTS% #define WF_INT_BIT 0x00000080 |
||
| 1293 | %MRF24WB0M_COMMENTS% #define WF_INT_IPCSET IPC1SET |
||
| 1294 | %MRF24WB0M_COMMENTS% #define WF_INT_IPCCLR IPC1CLR |
||
| 1295 | %MRF24WB0M_COMMENTS% #define WF_INT_IPC_MASK 0xFF000000 |
||
| 1296 | %MRF24WB0M_COMMENTS% #define WF_INT_IPC_VALUE 0x0C000000 |
||
| 1297 | %MRF24WB0M_COMMENTS% #else |
||
| 1298 | %MRF24WB0M_COMMENTS% #error Determine MRF24WB0M external interrupt |
||
| 1299 | %MRF24WB0M_COMMENTS% #endif |
||
| 1300 | %MRF24WB0M_COMMENTS% |
||
| 1301 | %MRF24WB0M_COMMENTS% #define WF_SSPBUF (SPI1BUF) |
||
| 1302 | %MRF24WB0M_COMMENTS% #define WF_SPISTAT (SPI1STAT) |
||
| 1303 | %MRF24WB0M_COMMENTS% #define WF_SPISTATbits (SPI1STATbits) |
||
| 1304 | %MRF24WB0M_COMMENTS% #if defined( __C30__ ) |
||
| 1305 | %MRF24WB0M_COMMENTS% #define WF_SPICON1 (SPI1CON1) |
||
| 1306 | %MRF24WB0M_COMMENTS% #define WF_SPICON1bits (SPI1CON1bits) |
||
| 1307 | %MRF24WB0M_COMMENTS% #define WF_SPICON2 (SPI1CON2) |
||
| 1308 | %MRF24WB0M_COMMENTS% #define WF_SPI_IE (IEC0bits.SPI1IE) |
||
| 1309 | %MRF24WB0M_COMMENTS% // #define WF_SPI_IP (IPC2bits.SPI1IP) |
||
| 1310 | %MRF24WB0M_COMMENTS% #define WF_SPI_IF (IFS0bits.SPI1IF) |
||
| 1311 | %MRF24WB0M_COMMENTS% #elif defined( __PIC32MX__ ) |
||
| 1312 | %MRF24WB0M_COMMENTS% #define WF_SPICON1 (SPI1CON) |
||
| 1313 | %MRF24WB0M_COMMENTS% #define WF_SPICON1bits (SPI1CONbits) |
||
| 1314 | %MRF24WB0M_COMMENTS% #define WF_SPI_IE_CLEAR IEC0CLR |
||
| 1315 | %MRF24WB0M_COMMENTS% #define WF_SPI_IF_CLEAR IFS0CLR |
||
| 1316 | %MRF24WB0M_COMMENTS% #define WF_SPI_INT_BITS 0x03800000 |
||
| 1317 | %MRF24WB0M_COMMENTS% #define WF_SPI_BRG (SPI1BRG) |
||
| 1318 | %MRF24WB0M_COMMENTS% #define WF_MAX_SPI_FREQ (10000000ul) // Hz |
||
| 1319 | %MRF24WB0M_COMMENTS% #else |
||
| 1320 | %MRF24WB0M_COMMENTS% #error Determine MRF24WB0M SPI information |
||
| 1321 | %MRF24WB0M_COMMENTS% #endif |
||
| 1322 | %MRF24WB0M_COMMENTS% |
||
| 1323 | %MRF24WB0M_COMMENTS% #elif defined( MRF24WB0M_IN_SPI2 ) && !defined(__32MX460F512L__) && !defined(__32MX795F512L__) |
||
| 1324 | %MRF24WB0M_COMMENTS% // MRF24WB0M in SPI2 slot |
||
| 1325 | %MRF24WB0M_COMMENTS% #define WF_CS_TRIS (TRISGbits.TRISG9) |
||
| 1326 | %MRF24WB0M_COMMENTS% #define WF_CS_IO (LATGbits.LATG9) |
||
| 1327 | %MRF24WB0M_COMMENTS% #define WF_SDI_TRIS (TRISGbits.TRISG7) |
||
| 1328 | %MRF24WB0M_COMMENTS% #define WF_SCK_TRIS (TRISGbits.TRISG6) |
||
| 1329 | %MRF24WB0M_COMMENTS% #define WF_SDO_TRIS (TRISGbits.TRISG8) |
||
| 1330 | %MRF24WB0M_COMMENTS% #define WF_RESET_TRIS (TRISGbits.TRISG0) |
||
| 1331 | %MRF24WB0M_COMMENTS% #define WF_RESET_IO (LATGbits.LATG0) |
||
| 1332 | %MRF24WB0M_COMMENTS% #if defined(__PIC24FJ256GB110__) || defined(__PIC24FJ256GB210__) |
||
| 1333 | %MRF24WB0M_COMMENTS% #define WF_INT_TRIS (TRISCbits.TRISC3) // INT3 |
||
| 1334 | %MRF24WB0M_COMMENTS% #define WF_INT_IO (PORTCbits.RC3) |
||
| 1335 | %MRF24WB0M_COMMENTS% #else |
||
| 1336 | %MRF24WB0M_COMMENTS% #define WF_INT_TRIS (TRISAbits.TRISA14) // INT3 |
||
| 1337 | %MRF24WB0M_COMMENTS% #define WF_INT_IO (PORTAbits.RA14) |
||
| 1338 | %MRF24WB0M_COMMENTS% #endif |
||
| 1339 | %MRF24WB0M_COMMENTS% #define WF_HIBERNATE_TRIS (TRISGbits.TRISG1) |
||
| 1340 | %MRF24WB0M_COMMENTS% #define WF_HIBERNATE_IO (PORTGbits.RG1) |
||
| 1341 | %MRF24WB0M_COMMENTS% #if defined( __C30__ ) |
||
| 1342 | %MRF24WB0M_COMMENTS% #define WF_INT_EDGE (INTCON2bits.INT3EP) |
||
| 1343 | %MRF24WB0M_COMMENTS% #define WF_INT_IE (IEC3bits.INT3IE) |
||
| 1344 | %MRF24WB0M_COMMENTS% #define WF_INT_IF (IFS3bits.INT3IF) |
||
| 1345 | %MRF24WB0M_COMMENTS% #elif defined( __PIC32MX__ ) |
||
| 1346 | %MRF24WB0M_COMMENTS% #define WF_INT_EDGE (INTCONbits.INT3EP) |
||
| 1347 | %MRF24WB0M_COMMENTS% #define WF_INT_IE (IEC0bits.INT3IE) |
||
| 1348 | %MRF24WB0M_COMMENTS% #define WF_INT_IF (IFS0bits.INT3IF) |
||
| 1349 | %MRF24WB0M_COMMENTS% #define WF_INT_IE_CLEAR IEC0CLR |
||
| 1350 | %MRF24WB0M_COMMENTS% #define WF_INT_IF_CLEAR IFS0CLR |
||
| 1351 | %MRF24WB0M_COMMENTS% #define WF_INT_IE_SET IEC0SET |
||
| 1352 | %MRF24WB0M_COMMENTS% #define WF_INT_IF_SET IFS0SET |
||
| 1353 | %MRF24WB0M_COMMENTS% #define WF_INT_BIT 0x00008000 |
||
| 1354 | %MRF24WB0M_COMMENTS% #define WF_INT_IPCSET IPC3SET |
||
| 1355 | %MRF24WB0M_COMMENTS% #define WF_INT_IPCCLR IPC3CLR |
||
| 1356 | %MRF24WB0M_COMMENTS% #define WF_INT_IPC_MASK 0xFF000000 |
||
| 1357 | %MRF24WB0M_COMMENTS% #define WF_INT_IPC_VALUE 0x0C000000 |
||
| 1358 | %MRF24WB0M_COMMENTS% #else |
||
| 1359 | %MRF24WB0M_COMMENTS% #error Determine MRF24WB0M external interrupt |
||
| 1360 | %MRF24WB0M_COMMENTS% #endif |
||
| 1361 | %MRF24WB0M_COMMENTS% |
||
| 1362 | %MRF24WB0M_COMMENTS% #define WF_SSPBUF (SPI2BUF) |
||
| 1363 | %MRF24WB0M_COMMENTS% #define WF_SPISTAT (SPI2STAT) |
||
| 1364 | %MRF24WB0M_COMMENTS% #define WF_SPISTATbits (SPI2STATbits) |
||
| 1365 | %MRF24WB0M_COMMENTS% #if defined( __C30__ ) |
||
| 1366 | %MRF24WB0M_COMMENTS% #define WF_SPICON1 (SPI2CON1) |
||
| 1367 | %MRF24WB0M_COMMENTS% #define WF_SPICON1bits (SPI2CON1bits) |
||
| 1368 | %MRF24WB0M_COMMENTS% #define WF_SPICON2 (SPI2CON2) |
||
| 1369 | %MRF24WB0M_COMMENTS% #define WF_SPI_IE (IEC2bits.SPI2IE) |
||
| 1370 | %MRF24WB0M_COMMENTS% // #define WF_SPI_IP (IPC8bits.SPI2IP) |
||
| 1371 | %MRF24WB0M_COMMENTS% #define WF_SPI_IF (IFS2bits.SPI2IF) |
||
| 1372 | %MRF24WB0M_COMMENTS% #elif defined( __PIC32MX__ ) |
||
| 1373 | %MRF24WB0M_COMMENTS% #define WF_SPICON1 (SPI2CON) |
||
| 1374 | %MRF24WB0M_COMMENTS% #define WF_SPICON1bits (SPI2CONbits) |
||
| 1375 | %MRF24WB0M_COMMENTS% #define WF_SPI_IE_CLEAR IEC1CLR |
||
| 1376 | %MRF24WB0M_COMMENTS% #define WF_SPI_IF_CLEAR IFS1CLR |
||
| 1377 | %MRF24WB0M_COMMENTS% #define WF_SPI_INT_BITS 0x000000e0 |
||
| 1378 | %MRF24WB0M_COMMENTS% #define WF_SPI_BRG (SPI2BRG) |
||
| 1379 | %MRF24WB0M_COMMENTS% #define WF_MAX_SPI_FREQ (10000000ul) // Hz |
||
| 1380 | %MRF24WB0M_COMMENTS% #else |
||
| 1381 | %MRF24WB0M_COMMENTS% #error Determine MRF24WB0M SPI information |
||
| 1382 | %MRF24WB0M_COMMENTS% #endif |
||
| 1383 | %MRF24WB0M_COMMENTS% |
||
| 1384 | %MRF24WB0M_COMMENTS% #elif defined( MRF24WB0M_IN_SPI1 ) && (defined(__32MX460F512L__) || defined(__32MX795F512L__)) |
||
| 1385 | %MRF24WB0M_COMMENTS% // MRF24WB0M in SPI1 slot |
||
| 1386 | %MRF24WB0M_COMMENTS% #define WF_CS_TRIS (TRISDbits.TRISD9) |
||
| 1387 | %MRF24WB0M_COMMENTS% #define WF_CS_IO (LATDbits.LATD9) |
||
| 1388 | %MRF24WB0M_COMMENTS% #define WF_SDI_TRIS (TRISCbits.TRISC4) |
||
| 1389 | %MRF24WB0M_COMMENTS% #define WF_SCK_TRIS (TRISDbits.TRISD10) |
||
| 1390 | %MRF24WB0M_COMMENTS% #define WF_SDO_TRIS (TRISDbits.TRISD0) |
||
| 1391 | %MRF24WB0M_COMMENTS% #define WF_RESET_TRIS (TRISFbits.TRISF0) |
||
| 1392 | %MRF24WB0M_COMMENTS% #define WF_RESET_IO (LATFbits.LATF0) |
||
| 1393 | %MRF24WB0M_COMMENTS% #define WF_INT_TRIS (TRISEbits.TRISE8) // INT1 |
||
| 1394 | %MRF24WB0M_COMMENTS% #define WF_INT_IO (PORTEbits.RE8) |
||
| 1395 | %MRF24WB0M_COMMENTS% #define WF_HIBERNATE_TRIS (TRISFbits.TRISF1) |
||
| 1396 | %MRF24WB0M_COMMENTS% #define WF_HIBERNATE_IO (PORTFbits.RF1) |
||
| 1397 | %MRF24WB0M_COMMENTS% #if defined( __C30__ ) |
||
| 1398 | %MRF24WB0M_COMMENTS% #define WF_INT_EDGE (INTCON2bits.INT1EP) |
||
| 1399 | %MRF24WB0M_COMMENTS% #define WF_INT_IE (IEC1bits.INT1IE) |
||
| 1400 | %MRF24WB0M_COMMENTS% #define WF_INT_IF (IFS1bits.INT1IF) |
||
| 1401 | %MRF24WB0M_COMMENTS% #elif defined( __PIC32MX__ ) |
||
| 1402 | %MRF24WB0M_COMMENTS% #define WF_INT_EDGE (INTCONbits.INT1EP) |
||
| 1403 | %MRF24WB0M_COMMENTS% #define WF_INT_IE (IEC0bits.INT1IE) |
||
| 1404 | %MRF24WB0M_COMMENTS% #define WF_INT_IF (IFS0bits.INT1IF) |
||
| 1405 | %MRF24WB0M_COMMENTS% #define WF_INT_IE_CLEAR IEC0CLR |
||
| 1406 | %MRF24WB0M_COMMENTS% #define WF_INT_IF_CLEAR IFS0CLR |
||
| 1407 | %MRF24WB0M_COMMENTS% #define WF_INT_IE_SET IEC0SET |
||
| 1408 | %MRF24WB0M_COMMENTS% #define WF_INT_IF_SET IFS0SET |
||
| 1409 | %MRF24WB0M_COMMENTS% #define WF_INT_BIT 0x00000080 |
||
| 1410 | %MRF24WB0M_COMMENTS% #define WF_INT_IPCSET IPC1SET |
||
| 1411 | %MRF24WB0M_COMMENTS% #define WF_INT_IPCCLR IPC1CLR |
||
| 1412 | %MRF24WB0M_COMMENTS% #define WF_INT_IPC_MASK 0xFF000000 |
||
| 1413 | %MRF24WB0M_COMMENTS% #define WF_INT_IPC_VALUE 0x0C000000 |
||
| 1414 | %MRF24WB0M_COMMENTS% #else |
||
| 1415 | %MRF24WB0M_COMMENTS% #error Determine MRF24WB0M external interrupt |
||
| 1416 | %MRF24WB0M_COMMENTS% #endif |
||
| 1417 | %MRF24WB0M_COMMENTS% |
||
| 1418 | %MRF24WB0M_COMMENTS% #define WF_SSPBUF (SPI1BUF) |
||
| 1419 | %MRF24WB0M_COMMENTS% #define WF_SPISTAT (SPI1STAT) |
||
| 1420 | %MRF24WB0M_COMMENTS% #define WF_SPISTATbits (SPI1STATbits) |
||
| 1421 | %MRF24WB0M_COMMENTS% #if defined( __C30__ ) |
||
| 1422 | %MRF24WB0M_COMMENTS% #define WF_SPICON1 (SPI1CON1) |
||
| 1423 | %MRF24WB0M_COMMENTS% #define WF_SPICON1bits (SPI1CON1bits) |
||
| 1424 | %MRF24WB0M_COMMENTS% #define WF_SPICON2 (SPI1CON2) |
||
| 1425 | %MRF24WB0M_COMMENTS% #define WF_SPI_IE (IEC0bits.SPI1IE) |
||
| 1426 | %MRF24WB0M_COMMENTS% // #define WF_SPI_IP (IPC2bits.SPI1IP) |
||
| 1427 | %MRF24WB0M_COMMENTS% #define WF_SPI_IF (IFS0bits.SPI1IF) |
||
| 1428 | %MRF24WB0M_COMMENTS% #elif defined( __PIC32MX__ ) |
||
| 1429 | %MRF24WB0M_COMMENTS% #define WF_SPICON1 (SPI1CON) |
||
| 1430 | %MRF24WB0M_COMMENTS% #define WF_SPICON1bits (SPI1CONbits) |
||
| 1431 | %MRF24WB0M_COMMENTS% #define WF_SPI_IE_CLEAR IEC0CLR |
||
| 1432 | %MRF24WB0M_COMMENTS% #define WF_SPI_IF_CLEAR IFS0CLR |
||
| 1433 | %MRF24WB0M_COMMENTS% #define WF_SPI_INT_BITS 0x03800000 |
||
| 1434 | %MRF24WB0M_COMMENTS% #define WF_SPI_BRG (SPI1BRG) |
||
| 1435 | %MRF24WB0M_COMMENTS% #define WF_MAX_SPI_FREQ (10000000ul) // Hz |
||
| 1436 | %MRF24WB0M_COMMENTS% #else |
||
| 1437 | %MRF24WB0M_COMMENTS% #error Determine MRF24WB0M SPI information |
||
| 1438 | %MRF24WB0M_COMMENTS% #endif |
||
| 1439 | %MRF24WB0M_COMMENTS% #elif defined( MRF24WB0M_IN_SPI2 ) && (defined(__32MX460F512L__) || defined(__32MX795F512L__)) |
||
| 1440 | %MRF24WB0M_COMMENTS% #error "/RST and /CE are on RG2 and RG3 which are multiplexed with USB D+ and D-." |
||
| 1441 | %MRF24WB0M_COMMENTS% #endif |
||
| 1442 | |||
| 1443 | #elif defined(DSPICDEM11) |
||
| 1444 | // dsPICDEM 1.1 Development Board + Ethernet PICtail airwired. There |
||
| 1445 | // is no PICtail header on this development board. The following |
||
| 1446 | // airwires must be made: |
||
| 1447 | // 1. dsPICDEM GND <-> PICtail GND (PICtail pin 27) |
||
| 1448 | // 2. dsPICDEM Vdd <- PICtail VPIC (PICtail pin 25) |
||
| 1449 | // 3. dsPICDEM RG2 -> PICtail ENC28J60 CS (PICtail pin 22) |
||
| 1450 | // 4. dsPICDEM RF6 -> PICtail SCK (PICtail pin 11) |
||
| 1451 | // 5. dsPICDEM RF7 <- PICtail SDI (PICtail pin 9) |
||
| 1452 | // 6. dsPICDEM RF8 -> PICtail SDO (PICtail pin 7) |
||
| 1453 | // 7. dsPICDEM RG3 -> PICtail 25LC256 CS (PICtail pin 20) |
||
| 1454 | |||
| 1455 | #define LED0_TRIS (TRISDbits.TRISD3) // Ref LED4 |
||
| 1456 | #define LED0_IO (PORTDbits.RD3) |
||
| 1457 | #define LED1_TRIS (TRISDbits.TRISD2) // Ref LED3 |
||
| 1458 | #define LED1_IO (PORTDbits.RD2) |
||
| 1459 | #define LED2_TRIS (TRISDbits.TRISD1) // Ref LED2 |
||
| 1460 | #define LED2_IO (PORTDbits.RD1) |
||
| 1461 | #define LED3_TRIS (TRISDbits.TRISD0) // Ref LED1 |
||
| 1462 | #define LED3_IO (PORTDbits.RD0) |
||
| 1463 | #define LED4_TRIS (TRISDbits.TRISD3) // No LED, Remapped to Ref LED4 |
||
| 1464 | #define LED4_IO (PORTDbits.RD3) |
||
| 1465 | #define LED5_TRIS (TRISDbits.TRISD2) // No LED, Remapped to Ref LED3 |
||
| 1466 | #define LED5_IO (PORTDbits.RD2) |
||
| 1467 | #define LED6_TRIS (TRISDbits.TRISD1) // No LED, Remapped to Ref LED2 |
||
| 1468 | #define LED6_IO (PORTDbits.RD1) |
||
| 1469 | #define LED7_TRIS (TRISDbits.TRISD0) // No LED, Remapped to Ref LED1 |
||
| 1470 | #define LED7_IO (PORTDbits.RD0) |
||
| 1471 | #define LED_GET() ((LED3_IO<<3) | (LED2_IO<<2) | (LED1_IO<<1) | LED0_IO) |
||
| 1472 | #define LED_PUT(a) do{BYTE vTemp = (a); LED0_IO = vTemp&0x1; LED1_IO = vTemp&0x2; LED2_IO = vTemp&0x4; LED3_IO = vTemp&0x8;} while(0) |
||
| 1473 | |||
| 1474 | #define BUTTON0_TRIS (TRISAbits.TRISA15) // Ref SW4 |
||
| 1475 | #define BUTTON0_IO (PORTAbits.RA15) |
||
| 1476 | #define BUTTON1_TRIS (TRISAbits.TRISA14) // Ref SW3 |
||
| 1477 | #define BUTTON1_IO (PORTAbits.RA14) |
||
| 1478 | #define BUTTON2_TRIS (TRISAbits.TRISA13) // Ref SW2 |
||
| 1479 | #define BUTTON2_IO (PORTAbits.RA13) |
||
| 1480 | #define BUTTON3_TRIS (TRISAbits.TRISA12) // Ref SW1 |
||
| 1481 | #define BUTTON3_IO (PORTAbits.RA12) |
||
| 1482 | |||
| 1483 | #define UARTTX_TRIS (TRISFbits.TRISF3) |
||
| 1484 | #define UARTTX_IO (PORTFbits.RF3) |
||
| 1485 | #define UARTRX_TRIS (TRISFbits.TRISF2) |
||
| 1486 | #define UARTRX_IO (PORTFbits.RF2) |
||
| 1487 | |||
| 1488 | %ENC28J60_COMMENTS% // ENC28J60 I/O pins |
||
| 1489 | %ENC28J60_COMMENTS% #define ENC_CS_TRIS (TRISGbits.TRISG2) // User must airwire this |
||
| 1490 | %ENC28J60_COMMENTS% #define ENC_CS_IO (PORTGbits.RG2) |
||
| 1491 | %ENC28J60_COMMENTS% // SPI SCK, SDI, SDO pins are automatically controlled by the |
||
| 1492 | %ENC28J60_COMMENTS% // PIC24/dsPIC/PIC32 SPI module |
||
| 1493 | %ENC28J60_COMMENTS% #define ENC_SPI_IF (IFS0bits.SPI1IF) |
||
| 1494 | %ENC28J60_COMMENTS% #define ENC_SSPBUF (SPI1BUF) |
||
| 1495 | %ENC28J60_COMMENTS% #define ENC_SPICON1 (SPI1CON) |
||
| 1496 | %ENC28J60_COMMENTS% #define ENC_SPICON1bits (SPI1CONbits) |
||
| 1497 | %ENC28J60_COMMENTS% #define ENC_SPICON2 (SPI1BUF) // SPI1CON2 doesn't exist, remap to unimportant register |
||
| 1498 | %ENC28J60_COMMENTS% #define ENC_SPISTAT (SPI1STAT) |
||
| 1499 | %ENC28J60_COMMENTS% #define ENC_SPISTATbits (SPI1STATbits) |
||
| 1500 | |||
| 1501 | %EEPROM_COMMENTS% // 25LC256 I/O pins |
||
| 1502 | %EEPROM_COMMENTS% #define EEPROM_CS_TRIS (TRISGbits.TRISG3) // User must airwire this |
||
| 1503 | %EEPROM_COMMENTS% #define EEPROM_CS_IO (PORTGbits.RG3) |
||
| 1504 | %EEPROM_COMMENTS% #define EEPROM_SCK_TRIS (TRISGbits.TRISG6) |
||
| 1505 | %EEPROM_COMMENTS% #define EEPROM_SDI_TRIS (TRISGbits.TRISG7) |
||
| 1506 | %EEPROM_COMMENTS% #define EEPROM_SDO_TRIS (TRISGbits.TRISG8) |
||
| 1507 | %EEPROM_COMMENTS% #define EEPROM_SPI_IF (IFS0bits.SPI1IF) |
||
| 1508 | %EEPROM_COMMENTS% #define EEPROM_SSPBUF (SPI1BUF) |
||
| 1509 | %EEPROM_COMMENTS% #define EEPROM_SPICON1 (SPI1CON) |
||
| 1510 | %EEPROM_COMMENTS% #define EEPROM_SPICON1bits (SPI1CONbits) |
||
| 1511 | %EEPROM_COMMENTS% #define EEPROM_SPICON2 (SPI1BUF) // SPI1CON2 doesn't exist, remap to unimportant register |
||
| 1512 | %EEPROM_COMMENTS% #define EEPROM_SPISTAT (SPI1STAT) |
||
| 1513 | %EEPROM_COMMENTS% #define EEPROM_SPISTATbits (SPI1STATbits) |
||
| 1514 | |||
| 1515 | // SI3000 codec pins |
||
| 1516 | #define CODEC_RST_TRIS (TRISFbits.TRISF6) |
||
| 1517 | #define CODEC_RST_IO (PORTFbits.RF6) |
||
| 1518 | |||
| 1519 | // PIC18F252 LCD Controller |
||
| 1520 | #define LCDCTRL_CS_TRIS (TRISGbits.TRISG9) |
||
| 1521 | #define LCDCTRL_CS_IO (PORTGbits.RG9) |
||
| 1522 | |||
| 1523 | #elif defined(PICDEMNET2) && !defined(HI_TECH_C) |
||
| 1524 | // PICDEM.net 2 (PIC18F97J60 + ENC28J60 or ENC624J600) |
||
| 1525 | |||
| 1526 | // I/O pins |
||
| 1527 | #define LED0_TRIS (TRISJbits.TRISJ0) |
||
| 1528 | #define LED0_IO (LATJbits.LATJ0) |
||
| 1529 | #define LED1_TRIS (TRISJbits.TRISJ1) |
||
| 1530 | #define LED1_IO (LATJbits.LATJ1) |
||
| 1531 | #define LED2_TRIS (TRISJbits.TRISJ2) |
||
| 1532 | #define LED2_IO (LATJbits.LATJ2) |
||
| 1533 | #define LED3_TRIS (TRISJbits.TRISJ3) |
||
| 1534 | #define LED3_IO (LATJbits.LATJ3) |
||
| 1535 | #define LED4_TRIS (TRISJbits.TRISJ4) |
||
| 1536 | #define LED4_IO (LATJbits.LATJ4) |
||
| 1537 | #define LED5_TRIS (TRISJbits.TRISJ5) |
||
| 1538 | #define LED5_IO (LATJbits.LATJ5) |
||
| 1539 | #define LED6_TRIS (TRISJbits.TRISJ6) |
||
| 1540 | #define LED6_IO (LATJbits.LATJ6) |
||
| 1541 | #define LED7_TRIS (TRISJbits.TRISJ7) |
||
| 1542 | #define LED7_IO (LATJbits.LATJ7) |
||
| 1543 | #define LED_GET() (LATJ) |
||
| 1544 | #define LED_PUT(a) (LATJ = (a)) |
||
| 1545 | |||
| 1546 | #define BUTTON0_TRIS (TRISBbits.TRISB3) |
||
| 1547 | #define BUTTON0_IO (PORTBbits.RB3) |
||
| 1548 | #define BUTTON1_TRIS (TRISBbits.TRISB2) |
||
| 1549 | #define BUTTON1_IO (PORTBbits.RB2) |
||
| 1550 | #define BUTTON2_TRIS (TRISBbits.TRISB1) |
||
| 1551 | #define BUTTON2_IO (PORTBbits.RB1) |
||
| 1552 | #define BUTTON3_TRIS (TRISBbits.TRISB0) |
||
| 1553 | #define BUTTON3_IO (PORTBbits.RB0) |
||
| 1554 | |||
| 1555 | %ENC100_COMMENTS% // ENC424J600/624J600 Fast 100Mbps Ethernet PICtail Plus defines |
||
| 1556 | %ENC100_COMMENTS% #define ENC100_INTERFACE_MODE 0 // Uncomment this to use the ENC424J600/624J600 Ethernet controller |
||
| 1557 | %ENC100_COMMENTS% |
||
| 1558 | %ENC100_COMMENTS% // ENC424J600/624J600 Fast 100Mbps Ethernet PICtail Plus I/O pins |
||
| 1559 | %ENC100_COMMENTS% #define ENC100_MDIX_TRIS (TRISBbits.TRISB4) |
||
| 1560 | %ENC100_COMMENTS% #define ENC100_MDIX_IO (LATBbits.LATB4) |
||
| 1561 | %ENC100_COMMENTS% #define ENC100_POR_TRIS (TRISBbits.TRISB5) |
||
| 1562 | %ENC100_COMMENTS% #define ENC100_POR_IO (LATBbits.LATB5) |
||
| 1563 | %ENC100_COMMENTS% #define ENC100_INT_TRIS (TRISBbits.TRISB2) |
||
| 1564 | %ENC100_COMMENTS% #define ENC100_INT_IO (PORTBbits.RB2) |
||
| 1565 | %ENC100_COMMENTS% |
||
| 1566 | %ENC100_COMMENTS% // ENC424J600/624J600 SPI pinout |
||
| 1567 | %ENC100_COMMENTS% #define ENC100_CS_TRIS (TRISBbits.TRISB3) |
||
| 1568 | %ENC100_COMMENTS% #define ENC100_CS_IO (LATBbits.LATB3) |
||
| 1569 | %ENC100_COMMENTS% #define ENC100_SO_WR_B0SEL_EN_TRIS (TRISCbits.TRISC4) // NOTE: SO is ENC624J600 Serial Out, which needs to connect to the PIC SDI pin for SPI mode |
||
| 1570 | %ENC100_COMMENTS% #define ENC100_SO_WR_B0SEL_EN_IO (PORTCbits.RC4) |
||
| 1571 | %ENC100_COMMENTS% #define ENC100_SI_RD_RW_TRIS (TRISCbits.TRISC5) // NOTE: SI is ENC624J600 Serial In, which needs to connect to the PIC SDO pin for SPI mode |
||
| 1572 | %ENC100_COMMENTS% #define ENC100_SI_RD_RW_IO (LATCbits.LATC5) |
||
| 1573 | %ENC100_COMMENTS% #define ENC100_SCK_AL_TRIS (TRISCbits.TRISC3) |
||
| 1574 | %ENC100_COMMENTS% #define ENC100_SCK_AL_IO (PORTCbits.RC3) // NOTE: This must be the PORT, not the LATch like it is for the PSP interface. |
||
| 1575 | %ENC100_COMMENTS% |
||
| 1576 | %ENC100_COMMENTS% // ENC424J600/624J600 SPI SFR register selection (controls which SPI |
||
| 1577 | %ENC100_COMMENTS% // peripheral to use on PICs with multiple SPI peripherals). |
||
| 1578 | %ENC100_COMMENTS%// #define ENC100_ISR_ENABLE (INTCON3bits.INT2IE) |
||
| 1579 | %ENC100_COMMENTS%// #define ENC100_ISR_FLAG (INTCON3bits.INT2IF) |
||
| 1580 | %ENC100_COMMENTS%// #define ENC100_ISR_POLARITY (INTCON2bits.INTEDG2) |
||
| 1581 | %ENC100_COMMENTS%// #define ENC100_ISR_PRIORITY (INTCON3bits.INT2IP) |
||
| 1582 | %ENC100_COMMENTS% #define ENC100_SPI_ENABLE (ENC100_SPISTATbits.SPIEN) |
||
| 1583 | %ENC100_COMMENTS% #define ENC100_SPI_IF (PIR1bits.SSP1IF) |
||
| 1584 | %ENC100_COMMENTS% #define ENC100_SSPBUF (SSP1BUF) |
||
| 1585 | %ENC100_COMMENTS% #define ENC100_SPISTAT (SSP1STAT) |
||
| 1586 | %ENC100_COMMENTS% #define ENC100_SPISTATbits (SSP1STATbits) |
||
| 1587 | %ENC100_COMMENTS% #define ENC100_SPICON1 (SSP1CON1) |
||
| 1588 | %ENC100_COMMENTS% #define ENC100_SPICON1bits (SSP1CON1bits) |
||
| 1589 | %ENC100_COMMENTS% #define ENC100_SPICON2 (SSP1CON2) |
||
| 1590 | |||
| 1591 | |||
| 1592 | %ENC28J60_COMMENTS% // ENC28J60 I/O pins |
||
| 1593 | %ENC28J60_COMMENTS% #define ENC_RST_TRIS (TRISDbits.TRISD2) // Not connected by default |
||
| 1594 | %ENC28J60_COMMENTS% #define ENC_RST_IO (LATDbits.LATD2) |
||
| 1595 | %ENC28J60_COMMENTS% %EXTRA_ENC28J60_COMMENT_FOR_PICDEMNET2%#define ENC_CS_TRIS (TRISDbits.TRISD3) // Uncomment this line if you wish to use the ENC28J60 on the PICDEM.net 2 board instead of the internal PIC18F97J60 Ethernet module |
||
| 1596 | %ENC28J60_COMMENTS% #define ENC_CS_IO (LATDbits.LATD3) |
||
| 1597 | %ENC28J60_COMMENTS% #define ENC_SCK_TRIS (TRISCbits.TRISC3) |
||
| 1598 | %ENC28J60_COMMENTS% #define ENC_SDI_TRIS (TRISCbits.TRISC4) |
||
| 1599 | %ENC28J60_COMMENTS% #define ENC_SDO_TRIS (TRISCbits.TRISC5) |
||
| 1600 | %ENC28J60_COMMENTS% #define ENC_SPI_IF (PIR1bits.SSP1IF) |
||
| 1601 | %ENC28J60_COMMENTS% #define ENC_SSPBUF (SSP1BUF) |
||
| 1602 | %ENC28J60_COMMENTS% #define ENC_SPISTAT (SSP1STAT) |
||
| 1603 | %ENC28J60_COMMENTS% #define ENC_SPISTATbits (SSP1STATbits) |
||
| 1604 | %ENC28J60_COMMENTS% #define ENC_SPICON1 (SSP1CON1) |
||
| 1605 | %ENC28J60_COMMENTS% #define ENC_SPICON1bits (SSP1CON1bits) |
||
| 1606 | %ENC28J60_COMMENTS% #define ENC_SPICON2 (SSP1CON2) |
||
| 1607 | |||
| 1608 | %MRF24WB0M_COMMENTS% //---------------- |
||
| 1609 | %MRF24WB0M_COMMENTS% // MRF24WB0M I/O pins |
||
| 1610 | %MRF24WB0M_COMMENTS% //---------------- |
||
| 1611 | %MRF24WB0M_COMMENTS% #define WF_CS_TRIS (TRISCbits.TRISC2) // Uncomment this line if you wish to use the MRF24WB0M on the PICDEM.net 2 board instead of the internal PIC18F97J60 Ethernet module |
||
| 1612 | %MRF24WB0M_COMMENTS% #define WF_SDI_TRIS (TRISCbits.TRISC4) |
||
| 1613 | %MRF24WB0M_COMMENTS% #define WF_SCK_TRIS (TRISCbits.TRISC3) |
||
| 1614 | %MRF24WB0M_COMMENTS% #define WF_SDO_TRIS (TRISCbits.TRISC5) |
||
| 1615 | %MRF24WB0M_COMMENTS% #define WF_RESET_TRIS (TRISBbits.TRISB1) |
||
| 1616 | %MRF24WB0M_COMMENTS% #define WF_RESET_IO (LATBbits.LATB1) |
||
| 1617 | %MRF24WB0M_COMMENTS% #define WF_INT_TRIS (TRISBbits.TRISB0) |
||
| 1618 | %MRF24WB0M_COMMENTS% #define WF_INT_IO (PORTBbits.RB0) |
||
| 1619 | %MRF24WB0M_COMMENTS% #define WF_CS_IO (LATCbits.LATC2) |
||
| 1620 | %MRF24WB0M_COMMENTS% #define WF_HIBERNATE_TRIS (TRISBbits.TRISB2) |
||
| 1621 | %MRF24WB0M_COMMENTS% #define WF_HIBERNATE_IO (PORTBbits.RB2) |
||
| 1622 | %MRF24WB0M_COMMENTS% #define WF_INT_EDGE (INTCON2bits.INTEDG0) |
||
| 1623 | %MRF24WB0M_COMMENTS% #define WF_INT_IE (INTCONbits.INT0IE) |
||
| 1624 | %MRF24WB0M_COMMENTS% #define WF_INT_IF (INTCONbits.INT0IF) |
||
| 1625 | %MRF24WB0M_COMMENTS% #define WF_SPI_IF (PIR1bits.SSPIF) |
||
| 1626 | %MRF24WB0M_COMMENTS% #define WF_SSPBUF (SSP1BUF) |
||
| 1627 | %MRF24WB0M_COMMENTS% #define WF_SPISTAT (SSP1STAT) |
||
| 1628 | %MRF24WB0M_COMMENTS% #define WF_SPISTATbits (SSP1STATbits) |
||
| 1629 | %MRF24WB0M_COMMENTS% #define WF_SPICON1 (SSP1CON1) |
||
| 1630 | %MRF24WB0M_COMMENTS% #define WF_SPICON1bits (SSP1CON1bits) |
||
| 1631 | %MRF24WB0M_COMMENTS% #define WF_SPICON2 (SSP1CON2) |
||
| 1632 | %MRF24WB0M_COMMENTS% #define WF_SPI_IE (PIE1bits.SSPIE) |
||
| 1633 | %MRF24WB0M_COMMENTS% #define WF_SPI_IP (IPR1bits.SSPIP) |
||
| 1634 | |||
| 1635 | %EEPROM_COMMENTS% // 25LC256 I/O pins |
||
| 1636 | %EEPROM_COMMENTS% #define EEPROM_CS_TRIS (TRISDbits.TRISD7) |
||
| 1637 | %EEPROM_COMMENTS% #define EEPROM_CS_IO (LATDbits.LATD7) |
||
| 1638 | %EEPROM_COMMENTS% #define EEPROM_SCK_TRIS (TRISCbits.TRISC3) |
||
| 1639 | %EEPROM_COMMENTS% #define EEPROM_SDI_TRIS (TRISCbits.TRISC4) |
||
| 1640 | %EEPROM_COMMENTS% #define EEPROM_SDO_TRIS (TRISCbits.TRISC5) |
||
| 1641 | %EEPROM_COMMENTS% #define EEPROM_SPI_IF (PIR1bits.SSP1IF) |
||
| 1642 | %EEPROM_COMMENTS% #define EEPROM_SSPBUF (SSP1BUF) |
||
| 1643 | %EEPROM_COMMENTS% #define EEPROM_SPICON1 (SSP1CON1) |
||
| 1644 | %EEPROM_COMMENTS% #define EEPROM_SPICON1bits (SSP1CON1bits) |
||
| 1645 | %EEPROM_COMMENTS% #define EEPROM_SPICON2 (SSP1CON2) |
||
| 1646 | %EEPROM_COMMENTS% #define EEPROM_SPISTAT (SSP1STAT) |
||
| 1647 | %EEPROM_COMMENTS% #define EEPROM_SPISTATbits (SSP1STATbits) |
||
| 1648 | |||
| 1649 | // LCD I/O pins |
||
| 1650 | #define LCD_DATA_TRIS (TRISE) |
||
| 1651 | #define LCD_DATA_IO (LATE) |
||
| 1652 | #define LCD_RD_WR_TRIS (TRISHbits.TRISH1) |
||
| 1653 | #define LCD_RD_WR_IO (LATHbits.LATH1) |
||
| 1654 | #define LCD_RS_TRIS (TRISHbits.TRISH2) |
||
| 1655 | #define LCD_RS_IO (LATHbits.LATH2) |
||
| 1656 | #define LCD_E_TRIS (TRISHbits.TRISH0) |
||
| 1657 | #define LCD_E_IO (LATHbits.LATH0) |
||
| 1658 | |||
| 1659 | // Serial Flash/SRAM/UART PICtail |
||
| 1660 | // #define SPIRAM_CS_TRIS (TRISBbits.TRISB5) |
||
| 1661 | // #define SPIRAM_CS_IO (LATBbits.LATB5) |
||
| 1662 | // #define SPIRAM_SCK_TRIS (TRISCbits.TRISC3) |
||
| 1663 | // #define SPIRAM_SDI_TRIS (TRISCbits.TRISC4) |
||
| 1664 | // #define SPIRAM_SDO_TRIS (TRISCbits.TRISC5) |
||
| 1665 | // #define SPIRAM_SPI_IF (PIR1bits.SSPIF) |
||
| 1666 | // #define SPIRAM_SSPBUF (SSP1BUF) |
||
| 1667 | // #define SPIRAM_SPICON1 (SSP1CON1) |
||
| 1668 | // #define SPIRAM_SPICON1bits (SSP1CON1bits) |
||
| 1669 | // #define SPIRAM_SPICON2 (SSP1CON2) |
||
| 1670 | // #define SPIRAM_SPISTAT (SSP1STAT) |
||
| 1671 | // #define SPIRAM_SPISTATbits (SSP1STATbits) |
||
| 1672 | // |
||
| 1673 | // // NOTE: You must also set the SPI_FLASH_SST/SPI_FLASH_SPANSION, |
||
| 1674 | // // SPI_FLASH_SECTOR_SIZE, and SPI_FLASH_PAGE_SIZE macros in |
||
| 1675 | // // SPIFlash.h to match your particular Flash memory chip!!! |
||
| 1676 | // #define SPIFLASH_CS_TRIS (TRISBbits.TRISB4) |
||
| 1677 | // #define SPIFLASH_CS_IO (LATBbits.LATB4) |
||
| 1678 | // #define SPIFLASH_SCK_TRIS (TRISCbits.TRISC3) |
||
| 1679 | // #define SPIFLASH_SDI_TRIS (TRISCbits.TRISC4) |
||
| 1680 | // #define SPIFLASH_SDI_IO (PORTCbits.RC4) |
||
| 1681 | // #define SPIFLASH_SDO_TRIS (TRISCbits.TRISC5) |
||
| 1682 | // #define SPIFLASH_SPI_IF (PIR1bits.SSPIF) |
||
| 1683 | // #define SPIFLASH_SSPBUF (SSP1BUF) |
||
| 1684 | // #define SPIFLASH_SPICON1 (SSP1CON1) |
||
| 1685 | // #define SPIFLASH_SPICON1bits (SSP1CON1bits) |
||
| 1686 | // #define SPIFLASH_SPICON2 (SSP1CON2) |
||
| 1687 | // #define SPIFLASH_SPISTAT (SSP1STAT) |
||
| 1688 | // #define SPIFLASH_SPISTATbits (SSP1STATbits) |
||
| 1689 | |||
| 1690 | #elif defined(PICDEMNET2) && defined(HI_TECH_C) |
||
| 1691 | // PICDEM.net 2 (PIC18F97J60 + ENC28J60) + HI-TECH PICC-18 compiler |
||
| 1692 | // Optionally may use Fast 100Mbps Ethernet PICtail Plus (ENC624J600) |
||
| 1693 | // I/O pins |
||
| 1694 | #define LED0_TRIS (TRISJ0) |
||
| 1695 | #define LED0_IO (LATJ0) |
||
| 1696 | #define LED1_TRIS (TRISJ1) |
||
| 1697 | #define LED1_IO (LATJ1) |
||
| 1698 | #define LED2_TRIS (TRISJ2) |
||
| 1699 | #define LED2_IO (LATJ2) |
||
| 1700 | #define LED3_TRIS (TRISJ3) |
||
| 1701 | #define LED3_IO (LATJ3) |
||
| 1702 | #define LED4_TRIS (TRISJ4) |
||
| 1703 | #define LED4_IO (LATJ4) |
||
| 1704 | #define LED5_TRIS (TRISJ5) |
||
| 1705 | #define LED5_IO (LATJ5) |
||
| 1706 | #define LED6_TRIS (TRISJ6) |
||
| 1707 | #define LED6_IO (LATJ6) |
||
| 1708 | #define LED7_TRIS (TRISJ7) |
||
| 1709 | #define LED7_IO (LATJ7) |
||
| 1710 | #define LED_GET() (LATJ) |
||
| 1711 | #define LED_PUT(a) (LATJ = (a)) |
||
| 1712 | |||
| 1713 | #define BUTTON0_TRIS (TRISB3) |
||
| 1714 | #define BUTTON0_IO (RB3) |
||
| 1715 | #define BUTTON1_TRIS (TRISB2) |
||
| 1716 | #define BUTTON1_IO (RB2) |
||
| 1717 | #define BUTTON2_TRIS (TRISB1) |
||
| 1718 | #define BUTTON2_IO (RB1) |
||
| 1719 | #define BUTTON3_TRIS (TRISB0) |
||
| 1720 | #define BUTTON3_IO (RB0) |
||
| 1721 | |||
| 1722 | %ENC28J60_COMMENTS% // ENC28J60 I/O pins |
||
| 1723 | %ENC28J60_COMMENTS% #define ENC_RST_TRIS (TRISD2) // Not connected by default |
||
| 1724 | %ENC28J60_COMMENTS% #define ENC_RST_IO (LATD2) |
||
| 1725 | %ENC28J60_COMMENTS% %EXTRA_ENC28J60_COMMENT_FOR_PICDEMNET2%#define ENC_CS_TRIS (TRISD3) // Uncomment this line if you wish to use the ENC28J60 on the PICDEM.net 2 board instead of the internal PIC18F97J60 Ethernet module |
||
| 1726 | %ENC28J60_COMMENTS% #define ENC_CS_IO (LATD3) |
||
| 1727 | %ENC28J60_COMMENTS% #define ENC_SCK_TRIS (TRISC3) |
||
| 1728 | %ENC28J60_COMMENTS% #define ENC_SDI_TRIS (TRISC4) |
||
| 1729 | %ENC28J60_COMMENTS% #define ENC_SDO_TRIS (TRISC5) |
||
| 1730 | %ENC28J60_COMMENTS% #define ENC_SPI_IF (SSPIF) |
||
| 1731 | %ENC28J60_COMMENTS% #define ENC_SSPBUF (SSP1BUF) |
||
| 1732 | %ENC28J60_COMMENTS% #define ENC_SPISTAT (SSP1STAT) |
||
| 1733 | %ENC28J60_COMMENTS% #define ENC_SPISTATbits (SSP1STATbits) |
||
| 1734 | %ENC28J60_COMMENTS% #define ENC_SPICON1 (SSP1CON1) |
||
| 1735 | %ENC28J60_COMMENTS% #define ENC_SPICON1bits (SSP1CON1bits) |
||
| 1736 | %ENC28J60_COMMENTS% #define ENC_SPICON2 (SSP1CON2) |
||
| 1737 | |||
| 1738 | %ENC100_COMMENTS% // ENC424J600/624J600 Fast 100Mbps Ethernet PICtail Plus defines |
||
| 1739 | %ENC100_COMMENTS% #define ENC100_INTERFACE_MODE 0 // Uncomment this to use the ENC424J600/624J600 Ethernet controller |
||
| 1740 | %ENC100_COMMENTS% |
||
| 1741 | %ENC100_COMMENTS% // ENC424J600/624J600 Fast 100Mbps Ethernet PICtail Plus I/O pins |
||
| 1742 | %ENC100_COMMENTS% #define ENC100_MDIX_TRIS (TRISB4) |
||
| 1743 | %ENC100_COMMENTS% #define ENC100_MDIX_IO (LATB4) |
||
| 1744 | %ENC100_COMMENTS% #define ENC100_POR_TRIS (TRISB5) |
||
| 1745 | %ENC100_COMMENTS% #define ENC100_POR_IO (LATB5) |
||
| 1746 | %ENC100_COMMENTS% #define ENC100_INT_TRIS (TRISB2) |
||
| 1747 | %ENC100_COMMENTS% #define ENC100_INT_IO (RB2) |
||
| 1748 | %ENC100_COMMENTS% |
||
| 1749 | %ENC100_COMMENTS% // ENC424J600/624J600 SPI pinout |
||
| 1750 | %ENC100_COMMENTS% #define ENC100_CS_TRIS (TRISB3) |
||
| 1751 | %ENC100_COMMENTS% #define ENC100_CS_IO (LATB3) |
||
| 1752 | %ENC100_COMMENTS% #define ENC100_SO_WR_B0SEL_EN_TRIS (TRISC4) // NOTE: SO is ENC624J600 Serial Out, which needs to connect to the PIC SDI pin for SPI mode |
||
| 1753 | %ENC100_COMMENTS% #define ENC100_SO_WR_B0SEL_EN_IO (RC4) |
||
| 1754 | %ENC100_COMMENTS% #define ENC100_SI_RD_RW_TRIS (TRISC5) // NOTE: SI is ENC624J600 Serial In, which needs to connect to the PIC SDO pin for SPI mode |
||
| 1755 | %ENC100_COMMENTS% #define ENC100_SI_RD_RW_IO (LATC5) |
||
| 1756 | %ENC100_COMMENTS% #define ENC100_SCK_AL_TRIS (TRISC3) |
||
| 1757 | %ENC100_COMMENTS% #define ENC100_SCK_AL_IO (RC3) // NOTE: This must be the PORT, not the LATch like it is for the PSP interface. |
||
| 1758 | %ENC100_COMMENTS% |
||
| 1759 | %ENC100_COMMENTS% // ENC424J600/624J600 SPI SFR register selection (controls which SPI |
||
| 1760 | %ENC100_COMMENTS% // peripheral to use on PICs with multiple SPI peripherals). |
||
| 1761 | %ENC100_COMMENTS%// #define ENC100_ISR_ENABLE (INT2IE) |
||
| 1762 | %ENC100_COMMENTS%// #define ENC100_ISR_FLAG (INT2IF) |
||
| 1763 | %ENC100_COMMENTS%// #define ENC100_ISR_POLARITY (INTEDG2) |
||
| 1764 | %ENC100_COMMENTS%// #define ENC100_ISR_PRIORITY (INT2IP) |
||
| 1765 | %ENC100_COMMENTS% #define ENC100_SPI_ENABLE (ENC100_SPISTATbits.SPIEN) |
||
| 1766 | %ENC100_COMMENTS% #define ENC100_SPI_IF (PIR1bits.SSP1IF) |
||
| 1767 | %ENC100_COMMENTS% #define ENC100_SSPBUF (SSP1BUF) |
||
| 1768 | %ENC100_COMMENTS% #define ENC100_SPISTAT (SSP1STAT) |
||
| 1769 | %ENC100_COMMENTS% #define ENC100_SPISTATbits (SSP1STATbits) |
||
| 1770 | %ENC100_COMMENTS% #define ENC100_SPICON1 (SSP1CON1) |
||
| 1771 | %ENC100_COMMENTS% #define ENC100_SPICON1bits (SSP1CON1bits) |
||
| 1772 | %ENC100_COMMENTS% #define ENC100_SPICON2 (SSP1CON2) |
||
| 1773 | |||
| 1774 | %EEPROM_COMMENTS% // 25LC256 I/O pins |
||
| 1775 | %EEPROM_COMMENTS% #define EEPROM_CS_TRIS (TRISD7) |
||
| 1776 | %EEPROM_COMMENTS% #define EEPROM_CS_IO (LATD7) |
||
| 1777 | %EEPROM_COMMENTS% #define EEPROM_SCK_TRIS (TRISC3) |
||
| 1778 | %EEPROM_COMMENTS% #define EEPROM_SDI_TRIS (TRISC4) |
||
| 1779 | %EEPROM_COMMENTS% #define EEPROM_SDO_TRIS (TRISC5) |
||
| 1780 | %EEPROM_COMMENTS% #define EEPROM_SPI_IF (SSP1IF) |
||
| 1781 | %EEPROM_COMMENTS% #define EEPROM_SSPBUF (SSP1BUF) |
||
| 1782 | %EEPROM_COMMENTS% #define EEPROM_SPICON1 (SSP1CON1) |
||
| 1783 | %EEPROM_COMMENTS% #define EEPROM_SPICON1bits (SSP1CON1bits) |
||
| 1784 | %EEPROM_COMMENTS% #define EEPROM_SPICON2 (SSP1CON2) |
||
| 1785 | %EEPROM_COMMENTS% #define EEPROM_SPISTAT (SSP1STAT) |
||
| 1786 | %EEPROM_COMMENTS% #define EEPROM_SPISTATbits (SSP1STATbits) |
||
| 1787 | |||
| 1788 | // LCD I/O pins |
||
| 1789 | #define LCD_DATA_TRIS (TRISE) |
||
| 1790 | #define LCD_DATA_IO (LATE) |
||
| 1791 | #define LCD_RD_WR_TRIS (TRISH1) |
||
| 1792 | #define LCD_RD_WR_IO (LATH1) |
||
| 1793 | #define LCD_RS_TRIS (TRISH2) |
||
| 1794 | #define LCD_RS_IO (LATH2) |
||
| 1795 | #define LCD_E_TRIS (TRISH0) |
||
| 1796 | #define LCD_E_IO (LATH0) |
||
| 1797 | |||
| 1798 | // Serial Flash/SRAM/UART PICtail |
||
| 1799 | // #define SPIRAM_CS_TRIS (TRISB5) |
||
| 1800 | // #define SPIRAM_CS_IO (LATB5) |
||
| 1801 | // #define SPIRAM_SCK_TRIS (TRISC3) |
||
| 1802 | // #define SPIRAM_SDI_TRIS (TRISC4) |
||
| 1803 | // #define SPIRAM_SDO_TRIS (TRISC5) |
||
| 1804 | // #define SPIRAM_SPI_IF (SSPIF) |
||
| 1805 | // #define SPIRAM_SSPBUF (SSP1BUF) |
||
| 1806 | // #define SPIRAM_SPICON1 (SSP1CON1) |
||
| 1807 | // #define SPIRAM_SPICON1bits (SSP1CON1bits) |
||
| 1808 | // #define SPIRAM_SPICON2 (SSP1CON2) |
||
| 1809 | // #define SPIRAM_SPISTAT (SSP1STAT) |
||
| 1810 | // #define SPIRAM_SPISTATbits (SSP1STATbits) |
||
| 1811 | // |
||
| 1812 | // // NOTE: You must also set the SPI_FLASH_SST/SPI_FLASH_SPANSION, |
||
| 1813 | // // SPI_FLASH_SECTOR_SIZE, and SPI_FLASH_PAGE_SIZE macros in |
||
| 1814 | // // SPIFlash.h to match your particular Flash memory chip!!! |
||
| 1815 | // #define SPIFLASH_CS_TRIS (TRISB4) |
||
| 1816 | // #define SPIFLASH_CS_IO (LATB4) |
||
| 1817 | // #define SPIFLASH_SCK_TRIS (TRISC3) |
||
| 1818 | // #define SPIFLASH_SDI_TRIS (TRISC4) |
||
| 1819 | // #define SPIFLASH_SDI_IO (RC4) |
||
| 1820 | // #define SPIFLASH_SDO_TRIS (TRISC5) |
||
| 1821 | // #define SPIFLASH_SPI_IF (SSPIF) |
||
| 1822 | // #define SPIFLASH_SSPBUF (SSP1BUF) |
||
| 1823 | // #define SPIFLASH_SPICON1 (SSP1CON1) |
||
| 1824 | // #define SPIFLASH_SPICON1bits (SSP1CON1bits) |
||
| 1825 | // #define SPIFLASH_SPICON2 (SSP1CON2) |
||
| 1826 | // #define SPIFLASH_SPISTAT (SSP1STAT) |
||
| 1827 | // #define SPIFLASH_SPISTATbits (SSP1STATbits) |
||
| 1828 | |||
| 1829 | // Register name fixup for certain processors |
||
| 1830 | #define SPBRGH SPBRGH1 |
||
| 1831 | #define TXSTAbits TXSTA1bits |
||
| 1832 | #define RCSTAbits RCSTA1bits |
||
| 1833 | #define BAUDCONbits BAUDCON1bits |
||
| 1834 | #define GO GODONE |
||
| 1835 | |||
| 1836 | #elif defined(INTERNET_RADIO) // Internet Radio board |
||
| 1837 | // Internet Radio board (05-60142) |
||
| 1838 | // I/O pins |
||
| 1839 | #define LED0_TRIS (TRISCbits.TRISC2) |
||
| 1840 | #define LED0_IO (LATCbits.LATC2) |
||
| 1841 | #define LED1_TRIS (PRODL) // No LED1 on this board |
||
| 1842 | #define LED1_IO (PRODL) |
||
| 1843 | #define LED2_TRIS (PRODL) // No LED2 on this board |
||
| 1844 | #define LED2_IO (PRODL) |
||
| 1845 | #define LED3_TRIS (PRODL) // No LED3 on this board |
||
| 1846 | #define LED3_IO (PRODL) |
||
| 1847 | #define LED4_TRIS (PRODL) // No LED4 on this board |
||
| 1848 | #define LED4_IO (PRODL) |
||
| 1849 | #define LED5_TRIS (PRODL) // No LED5 on this board |
||
| 1850 | #define LED5_IO (PRODL) |
||
| 1851 | #define LED6_TRIS (PRODL) // No LED6 on this board |
||
| 1852 | #define LED6_IO (PRODL) |
||
| 1853 | #define LED7_TRIS (PRODL) // No LED7 on this board |
||
| 1854 | #define LED7_IO (PRODL) |
||
| 1855 | #define LED_GET() (LED0_IO) |
||
| 1856 | #define LED_PUT(a) (LED0_IO = (a)) |
||
| 1857 | |||
| 1858 | #define BUTTON0_TRIS (TRISBbits.TRISB5) |
||
| 1859 | #define BUTTON0_IO (PORTBbits.RB5) |
||
| 1860 | #define BUTTON1_TRIS (TRISFbits.TRISF1) |
||
| 1861 | #define BUTTON1_IO (PORTFbits.RF1) |
||
| 1862 | #define BUTTON2_TRIS (TRISBbits.TRISB4) |
||
| 1863 | #define BUTTON2_IO (PORTBbits.RB4) |
||
| 1864 | #define BUTTON3_TRIS (PRODL) // No BUTTON3 on this board |
||
| 1865 | #define BUTTON3_IO (PRODL) |
||
| 1866 | |||
| 1867 | // Serial SRAM |
||
| 1868 | #define SPIRAM_CS_TRIS (TRISEbits.TRISE4) |
||
| 1869 | #define SPIRAM_CS_IO (LATEbits.LATE4) |
||
| 1870 | #define SPIRAM_SCK_TRIS (TRISCbits.TRISC3) |
||
| 1871 | #define SPIRAM_SDI_TRIS (TRISCbits.TRISC4) |
||
| 1872 | #define SPIRAM_SDO_TRIS (TRISCbits.TRISC5) |
||
| 1873 | #define SPIRAM_SPI_IF (PIR1bits.SSPIF) |
||
| 1874 | #define SPIRAM_SSPBUF (SSP1BUF) |
||
| 1875 | #define SPIRAM_SPICON1 (SSP1CON1) |
||
| 1876 | #define SPIRAM_SPICON1bits (SSP1CON1bits) |
||
| 1877 | #define SPIRAM_SPICON2 (SSP1CON2) |
||
| 1878 | #define SPIRAM_SPISTAT (SSP1STAT) |
||
| 1879 | #define SPIRAM_SPISTATbits (SSP1STATbits) |
||
| 1880 | #define SPIRAM2_CS_TRIS (TRISEbits.TRISE5) |
||
| 1881 | #define SPIRAM2_CS_IO (LATEbits.LATE5) |
||
| 1882 | #define SPIRAM2_SCK_TRIS (TRISCbits.TRISC3) |
||
| 1883 | #define SPIRAM2_SDI_TRIS (TRISCbits.TRISC4) |
||
| 1884 | #define SPIRAM2_SDO_TRIS (TRISCbits.TRISC5) |
||
| 1885 | #define SPIRAM2_SPI_IF (PIR1bits.SSPIF) |
||
| 1886 | #define SPIRAM2_SSPBUF (SSP1BUF) |
||
| 1887 | #define SPIRAM2_SPICON1 (SSP1CON1) |
||
| 1888 | #define SPIRAM2_SPICON1bits (SSP1CON1bits) |
||
| 1889 | #define SPIRAM2_SPICON2 (SSP1CON2) |
||
| 1890 | #define SPIRAM2_SPISTAT (SSP1STAT) |
||
| 1891 | #define SPIRAM2_SPISTATbits (SSP1STATbits) |
||
| 1892 | |||
| 1893 | // VLSI VS1011/VS1053 audio encoder/decoder and DAC |
||
| 1894 | #define MP3_DREQ_TRIS (TRISBbits.TRISB0) // Data Request |
||
| 1895 | #define MP3_DREQ_IO (PORTBbits.RB0) |
||
| 1896 | #define MP3_XRESET_TRIS (TRISDbits.TRISD0) // Reset, active low |
||
| 1897 | #define MP3_XRESET_IO (LATDbits.LATD0) |
||
| 1898 | #define MP3_XDCS_TRIS (TRISBbits.TRISB1) // Data Chip Select |
||
| 1899 | #define MP3_XDCS_IO (LATBbits.LATB1) |
||
| 1900 | #define MP3_XCS_TRIS (TRISBbits.TRISB2) // Control Chip Select |
||
| 1901 | #define MP3_XCS_IO (LATBbits.LATB2) |
||
| 1902 | #define MP3_SCK_TRIS (TRISCbits.TRISC3) |
||
| 1903 | #define MP3_SDI_TRIS (TRISCbits.TRISC4) |
||
| 1904 | #define MP3_SDO_TRIS (TRISCbits.TRISC5) |
||
| 1905 | #define MP3_SPI_IF (PIR1bits.SSP1IF) |
||
| 1906 | #define MP3_SSPBUF (SSP1BUF) |
||
| 1907 | #define MP3_SPICON1 (SSP1CON1) |
||
| 1908 | #define MP3_SPICON1bits (SSP1CON1bits) |
||
| 1909 | #define MP3_SPICON2 (SSP1CON2) |
||
| 1910 | #define MP3_SPISTAT (SSP1STAT) |
||
| 1911 | #define MP3_SPISTATbits (SSP1STATbits) |
||
| 1912 | |||
| 1913 | // OLED Display |
||
| 1914 | #define oledWR (PORTAbits.RA3) |
||
| 1915 | #define oledWR_TRIS (TRISAbits.TRISA3) |
||
| 1916 | #define oledRD (PORTAbits.RA4) |
||
| 1917 | #define oledRD_TRIS (TRISAbits.TRISA4) |
||
| 1918 | #define oledCS (PORTAbits.RA5) |
||
| 1919 | #define oledCS_TRIS (TRISAbits.TRISA5) |
||
| 1920 | #define oledRESET (PORTDbits.RD1) |
||
| 1921 | #define oledRESET_TRIS (TRISDbits.TRISD1) |
||
| 1922 | #define oledD_C (PORTGbits.RG4) |
||
| 1923 | #define oledD_C_TRIS (TRISGbits.TRISG4) |
||
| 1924 | |||
| 1925 | |||
| 1926 | #elif defined(PIC32_GP_SK_DM320001) || defined(PIC32_USB_DM320003_1) || defined(PIC32_USB_SK_DM320003_2) |
||
| 1927 | // PIC32 (General Purpose) Starter Kit (02-02002) with PIC32MX360F512L processor, |
||
| 1928 | // PIC32 USB Starter Board (02-02030) with PIC32MX460F512L processor, or |
||
| 1929 | // PIC32 USB Starter Kit II (02-02148) with PIC32MX795F512L processor + |
||
| 1930 | // PIC32 I/O Expansion Board (05-02029) + |
||
| 1931 | // Ethernet PICtail Plus, Fast 100Mbps Ethernet PICtail Plus, or |
||
| 1932 | // MRF24WB0M 802.11 WiFi PICtail Plus |
||
| 1933 | |||
| 1934 | // Specify which SPI to use for the ENC28J60 or ENC624J600. SPI1 is |
||
| 1935 | // the topmost slot with pin 1 on it. SPI2 is the middle slot |
||
| 1936 | // starting on pin 33. |
||
| 1937 | #define ENC_IN_SPI1 |
||
| 1938 | //#define ENC_IN_SPI2 |
||
| 1939 | |||
| 1940 | // Note that SPI1 cannot be used when using the PIC32 USB Starter |
||
| 1941 | // Board or PIC32 USB Starter Kit II due to the USB peripheral pins |
||
| 1942 | // mapping on top of the ordinary SPI1 pinout. |
||
| 1943 | #if defined(ENC_IN_SPI1) && (defined(__32MX460F512L__) || defined(__32MX795F512L__)) |
||
| 1944 | #undef ENC_IN_SPI1 |
||
| 1945 | #define ENC_IN_SPI2 |
||
| 1946 | #endif |
||
| 1947 | |||
| 1948 | |||
| 1949 | // Hardware mappings |
||
| 1950 | #define LED0_TRIS (TRISDbits.TRISD0) // Ref LED1 |
||
| 1951 | #define LED0_IO (LATDbits.LATD0) |
||
| 1952 | #define LED1_TRIS (TRISDbits.TRISD1) // Ref LED2 |
||
| 1953 | #define LED1_IO (LATDbits.LATD1) |
||
| 1954 | #define LED2_TRIS (TRISDbits.TRISD2) // Ref LED3 |
||
| 1955 | #define LED2_IO (LATDbits.LATD2) |
||
| 1956 | #define LED3_TRIS (LED2_TRIS) // No such LED |
||
| 1957 | #define LED3_IO (LATDbits.LATD6) |
||
| 1958 | #define LED4_TRIS (LED2_TRIS) // No such LED |
||
| 1959 | #define LED4_IO (LATDbits.LATD6) |
||
| 1960 | #define LED5_TRIS (LED2_TRIS) // No such LED |
||
| 1961 | #define LED5_IO (LATDbits.LATD6) |
||
| 1962 | #define LED6_TRIS (LED2_TRIS) // No such LED |
||
| 1963 | #define LED6_IO (LATDbits.LATD6) |
||
| 1964 | #define LED7_TRIS (LED2_TRIS) // No such LED |
||
| 1965 | #define LED7_IO (LATDbits.LATD6) |
||
| 1966 | |||
| 1967 | #define LED_GET() ((BYTE)LATD & 0x07) |
||
| 1968 | #define LED_PUT(a) do{LATD = (LATD & 0xFFF8) | ((a)&0x07);}while(0) |
||
| 1969 | |||
| 1970 | #define BUTTON0_TRIS (TRISDbits.TRISD6) // Ref SW1 |
||
| 1971 | #define BUTTON0_IO (PORTDbits.RD6) |
||
| 1972 | #define BUTTON1_TRIS (TRISDbits.TRISD7) // Ref SW2 |
||
| 1973 | #define BUTTON1_IO (PORTDbits.RD7) |
||
| 1974 | #define BUTTON2_TRIS (TRISDbits.TRISD13) // Ref SW3 |
||
| 1975 | #define BUTTON2_IO (PORTDbits.RD13) |
||
| 1976 | #define BUTTON3_TRIS (TRISDbits.TRISD13) // No BUTTON3 on this board |
||
| 1977 | #define BUTTON3_IO (1) |
||
| 1978 | |||
| 1979 | // UART configuration (not too important since we don't have a UART |
||
| 1980 | // connector attached normally, but needed to compile if the STACK_USE_UART |
||
| 1981 | // or STACK_USE_UART2TCP_BRIDGE features are enabled. |
||
| 1982 | #define UARTTX_TRIS (TRISFbits.TRISF3) |
||
| 1983 | #define UARTRX_TRIS (TRISFbits.TRISF2) |
||
| 1984 | |||
| 1985 | |||
| 1986 | %ENC28J60_COMMENTS% // ENC28J60 I/O pins |
||
| 1987 | %ENC28J60_COMMENTS% #if defined ENC_IN_SPI1 |
||
| 1988 | %ENC28J60_COMMENTS% #define ENC_CS_TRIS (TRISDbits.TRISD14) // Comment this line out if you are using the ENC424J600/624J600, MRF24WB0M, or other network controller. |
||
| 1989 | %ENC28J60_COMMENTS% #define ENC_CS_IO (PORTDbits.RD14) |
||
| 1990 | %ENC28J60_COMMENTS% //#define ENC_RST_TRIS (TRISDbits.TRISD15) // Not connected by default. It is okay to leave this pin completely unconnected, in which case this macro should simply be left undefined. |
||
| 1991 | %ENC28J60_COMMENTS% //#define ENC_RST_IO (PORTDbits.RD15) |
||
| 1992 | %ENC28J60_COMMENTS% |
||
| 1993 | %ENC28J60_COMMENTS% // SPI SCK, SDI, SDO pins are automatically controlled by the |
||
| 1994 | %ENC28J60_COMMENTS% #define ENC_SPI_IF (IFS0bits.SPI1RXIF) |
||
| 1995 | %ENC28J60_COMMENTS% #define ENC_SSPBUF (SPI1BUF) |
||
| 1996 | %ENC28J60_COMMENTS% #define ENC_SPICON1 (SPI1CON) |
||
| 1997 | %ENC28J60_COMMENTS% #define ENC_SPICON1bits (SPI1CONbits) |
||
| 1998 | %ENC28J60_COMMENTS% #define ENC_SPIBRG (SPI1BRG) |
||
| 1999 | %ENC28J60_COMMENTS% #define ENC_SPISTATbits (SPI1STATbits) |
||
| 2000 | %ENC28J60_COMMENTS% #elif defined ENC_IN_SPI2 |
||
| 2001 | %ENC28J60_COMMENTS% #define ENC_CS_TRIS (TRISFbits.TRISF12) // Comment this line out if you are using the ENC424J600/624J600, MRF24WB0M, or other network controller. |
||
| 2002 | %ENC28J60_COMMENTS% #define ENC_CS_IO (PORTFbits.RF12) |
||
| 2003 | %ENC28J60_COMMENTS% //#define ENC_RST_TRIS (TRISFbits.TRISF13) // Not connected by default |
||
| 2004 | %ENC28J60_COMMENTS% //#define ENC_RST_IO (PORTFbits.RF13) |
||
| 2005 | %ENC28J60_COMMENTS% |
||
| 2006 | %ENC28J60_COMMENTS% // SPI SCK, SDI, SDO pins are automatically controlled by the |
||
| 2007 | %ENC28J60_COMMENTS% // PIC32 SPI module |
||
| 2008 | %ENC28J60_COMMENTS% #define ENC_SPI_IF (IFS1bits.SPI2RXIF) |
||
| 2009 | %ENC28J60_COMMENTS% #define ENC_SSPBUF (SPI2BUF) |
||
| 2010 | %ENC28J60_COMMENTS% #define ENC_SPICON1 (SPI2CON) |
||
| 2011 | %ENC28J60_COMMENTS% #define ENC_SPISTATbits (SPI2STATbits) |
||
| 2012 | %ENC28J60_COMMENTS% #define ENC_SPICON1bits (SPI2CONbits) |
||
| 2013 | %ENC28J60_COMMENTS% #define ENC_SPIBRG (SPI2BRG) |
||
| 2014 | %ENC28J60_COMMENTS% #endif |
||
| 2015 | |||
| 2016 | |||
| 2017 | |||
| 2018 | %ENC100_COMMENTS% // ENC624J600 Interface Configuration |
||
| 2019 | %ENC100_COMMENTS% // Comment out ENC100_INTERFACE_MODE if you don't have an ENC624J600 or |
||
| 2020 | %ENC100_COMMENTS% // ENC424J600. Otherwise, choose the correct setting for the interface you |
||
| 2021 | %ENC100_COMMENTS% // are using. Legal values are: |
||
| 2022 | %ENC100_COMMENTS% // - Commented out: No ENC424J600/624J600 present or used. All other |
||
| 2023 | %ENC100_COMMENTS% // ENC100_* macros are ignored. |
||
| 2024 | %ENC100_COMMENTS% // - 0: SPI mode using CS, SCK, SI, and SO pins |
||
| 2025 | %ENC100_COMMENTS% // - 1: 8-bit demultiplexed PSP Mode 1 with RD and WR pins |
||
| 2026 | %ENC100_COMMENTS% // - 2: 8-bit demultiplexed PSP Mode 2 with R/Wbar and EN pins |
||
| 2027 | %ENC100_COMMENTS% // - 3: 16-bit demultiplexed PSP Mode 3 with RD, WRL, and WRH pins |
||
| 2028 | %ENC100_COMMENTS% // - 4: 16-bit demultiplexed PSP Mode 4 with R/Wbar, B0SEL, and B1SEL pins |
||
| 2029 | %ENC100_COMMENTS% // - 5: 8-bit multiplexed PSP Mode 5 with RD and WR pins |
||
| 2030 | %ENC100_COMMENTS% // - 6: 8-bit multiplexed PSP Mode 6 with R/Wbar and EN pins |
||
| 2031 | %ENC100_COMMENTS% // - 9: 16-bit multiplexed PSP Mode 9 with AL, RD, WRL, and WRH pins |
||
| 2032 | %ENC100_COMMENTS% // - 10: 16-bit multiplexed PSP Mode 10 with AL, R/Wbar, B0SEL, and B1SEL |
||
| 2033 | %ENC100_COMMENTS% // pins |
||
| 2034 | %ENC100_COMMENTS% #define ENC100_INTERFACE_MODE %ENC100_INTERFACE_MODE% |
||
| 2035 | %ENC100_COMMENTS% |
||
| 2036 | %ENC100_COMMENTS% // If using a parallel interface, direct RAM addressing can be used (if all |
||
| 2037 | %ENC100_COMMENTS% // addresses wires are connected), or a reduced number of pins can be used |
||
| 2038 | %ENC100_COMMENTS% // for indirect addressing. If using an SPI interface or PSP Mode 9 or 10 |
||
| 2039 | %ENC100_COMMENTS% // (multiplexed 16-bit modes), which require all address lines to always be |
||
| 2040 | %ENC100_COMMENTS% // connected, then this option is ignored. Comment out or uncomment this |
||
| 2041 | %ENC100_COMMENTS% // macro to match your hardware connections. |
||
| 2042 | %ENC100_COMMENTS% #define ENC100_PSP_USE_INDIRECT_RAM_ADDRESSING |
||
| 2043 | %ENC100_COMMENTS% |
||
| 2044 | %ENC100_COMMENTS% // ENC424J600/624J600 parallel indirect address remapping macro function. |
||
| 2045 | %ENC100_COMMENTS% // This section translates SFR and RAM addresses presented to the |
||
| 2046 | %ENC100_COMMENTS% // ReadMemory() and WriteMemory() APIs in ENCX24J600.c to the actual |
||
| 2047 | %ENC100_COMMENTS% // addresses that must be presented on the parallel interface. This macro |
||
| 2048 | %ENC100_COMMENTS% // must be modified to match your hardware if you are using an indirect PSP |
||
| 2049 | %ENC100_COMMENTS% // addressing mode (ENC100_PSP_USE_INDIRECT_RAM_ADDRESSING is defined) and |
||
| 2050 | %ENC100_COMMENTS% // have some of your address lines tied off to Vdd. If you are using the |
||
| 2051 | %ENC100_COMMENTS% // SPI interface, then this section can be ignored or deleted. |
||
| 2052 | %ENC100_COMMENTS% #if (ENC100_INTERFACE_MODE == 1) || (ENC100_INTERFACE_MODE == 2) || (ENC100_INTERFACE_MODE == 5) || (ENC100_INTERFACE_MODE == 6) // 8-bit PSP |
||
| 2053 | %ENC100_COMMENTS% #define ENC100_TRANSLATE_TO_PIN_ADDR(a) ((((a)&0x0100)<<6) | ((a)&0x00FF)) |
||
| 2054 | %ENC100_COMMENTS% #elif (ENC100_INTERFACE_MODE == 3) || (ENC100_INTERFACE_MODE == 4) // 16-bit PSP |
||
| 2055 | %ENC100_COMMENTS% #define ENC100_TRANSLATE_TO_PIN_ADDR(a) (a) |
||
| 2056 | %ENC100_COMMENTS% #endif |
||
| 2057 | %ENC100_COMMENTS% |
||
| 2058 | %ENC100_COMMENTS% // Auto-crossover pins on Fast 100Mbps Ethernet PICtail/PICtail Plus. If |
||
| 2059 | %ENC100_COMMENTS% // your circuit doesn't have such a feature, delete these two defines. |
||
| 2060 | %ENC100_COMMENTS% #define ENC100_MDIX_TRIS (TRISBbits.TRISB3) |
||
| 2061 | %ENC100_COMMENTS% #define ENC100_MDIX_IO (LATBbits.LATB3) |
||
| 2062 | %ENC100_COMMENTS% |
||
| 2063 | %ENC100_COMMENTS% // ENC624J600 I/O control and status pins |
||
| 2064 | %ENC100_COMMENTS% // If a pin is not required for your selected ENC100_INTERFACE_MODE |
||
| 2065 | %ENC100_COMMENTS% // interface selection (ex: WRH/B1SEL for PSP modes 1, 2, 5, and 6), then |
||
| 2066 | %ENC100_COMMENTS% // you can ignore, delete, or put anything for the pin definition. Also, |
||
| 2067 | %ENC100_COMMENTS% // the INT and POR pins are entirely optional. If not connected, comment |
||
| 2068 | %ENC100_COMMENTS% // them out. |
||
| 2069 | %ENC100_COMMENTS% #define ENC100_INT_TRIS (TRISEbits.TRISE9) // INT signal is optional and currently unused in the Microchip TCP/IP Stack. Leave this pin disconnected and comment out this pin definition if you don't want it. |
||
| 2070 | %ENC100_COMMENTS% #define ENC100_INT_IO (PORTEbits.RE9) |
||
| 2071 | %ENC100_COMMENTS% #if (ENC100_INTERFACE_MODE >= 1) // Parallel mode |
||
| 2072 | %ENC100_COMMENTS% // PSP control signal pinout |
||
| 2073 | %ENC100_COMMENTS% #define ENC100_CS_TRIS (TRISAbits.TRISA5) // CS is optional in PSP mode. If you are not sharing the parallel bus with another device, tie CS to Vdd and comment out this pin definition. |
||
| 2074 | %ENC100_COMMENTS% #define ENC100_CS_IO (LATAbits.LATA5) |
||
| 2075 | %ENC100_COMMENTS% #define ENC100_POR_TRIS (TRISCbits.TRISC1) // POR signal is optional. If your application doesn't have a power disconnect feature, comment out this pin definition. |
||
| 2076 | %ENC100_COMMENTS% #define ENC100_POR_IO (LATCbits.LATC1) |
||
| 2077 | %ENC100_COMMENTS% #define ENC100_SO_WR_B0SEL_EN_TRIS (TRISDbits.TRISD4) |
||
| 2078 | %ENC100_COMMENTS% #define ENC100_SO_WR_B0SEL_EN_IO (LATDbits.LATD4) |
||
| 2079 | %ENC100_COMMENTS% #define ENC100_SI_RD_RW_TRIS (TRISDbits.TRISD5) |
||
| 2080 | %ENC100_COMMENTS% #define ENC100_SI_RD_RW_IO (LATDbits.LATD5) |
||
| 2081 | %ENC100_COMMENTS% #define ENC100_SCK_AL_TRIS (TRISBbits.TRISB15) |
||
| 2082 | %ENC100_COMMENTS% #define ENC100_SCK_AL_IO (LATBbits.LATB15) |
||
| 2083 | %ENC100_COMMENTS% #else |
||
| 2084 | %ENC100_COMMENTS% // SPI pinout |
||
| 2085 | %ENC100_COMMENTS% #if defined ENC_IN_SPI1 |
||
| 2086 | %ENC100_COMMENTS% #define ENC100_CS_TRIS (TRISDbits.TRISD14) // CS is mandatory when using the SPI interface |
||
| 2087 | %ENC100_COMMENTS% #define ENC100_CS_IO (LATDbits.LATD14) |
||
| 2088 | %ENC100_COMMENTS% #define ENC100_POR_TRIS (TRISDbits.TRISD15) // POR signal is optional. If your application doesn't have a power disconnect feature, comment out this pin definition. |
||
| 2089 | %ENC100_COMMENTS% #define ENC100_POR_IO (LATDbits.LATD15) |
||
| 2090 | %ENC100_COMMENTS% #define ENC100_SO_WR_B0SEL_EN_TRIS (TRISFbits.TRISF7) // SO is ENCX24J600 Serial Out, which needs to connect to the PIC SDI pin for SPI mode |
||
| 2091 | %ENC100_COMMENTS% #define ENC100_SO_WR_B0SEL_EN_IO (PORTFbits.RF7) |
||
| 2092 | %ENC100_COMMENTS% #define ENC100_SI_RD_RW_TRIS (TRISFbits.TRISF8) // SI is ENCX24J600 Serial In, which needs to connect to the PIC SDO pin for SPI mode |
||
| 2093 | %ENC100_COMMENTS% #define ENC100_SI_RD_RW_IO (LATFbits.LATF8) |
||
| 2094 | %ENC100_COMMENTS% #define ENC100_SCK_AL_TRIS (TRISFbits.TRISF6) |
||
| 2095 | %ENC100_COMMENTS% #elif defined ENC_IN_SPI2 |
||
| 2096 | %ENC100_COMMENTS% #define ENC100_CS_TRIS (TRISFbits.TRISF12) |
||
| 2097 | %ENC100_COMMENTS% #define ENC100_CS_IO (LATFbits.LATF12) |
||
| 2098 | %ENC100_COMMENTS% #define ENC100_POR_TRIS (TRISFbits.TRISF13) |
||
| 2099 | %ENC100_COMMENTS% #define ENC100_POR_IO (LATFbits.LATF13) |
||
| 2100 | %ENC100_COMMENTS% #define ENC100_SO_WR_B0SEL_EN_TRIS (TRISGbits.TRISG7) // NOTE: SO is ENC624J600 Serial Out, which needs to connect to the PIC SDI pin for SPI mode |
||
| 2101 | %ENC100_COMMENTS% #define ENC100_SO_WR_B0SEL_EN_IO (PORTGbits.RG7) |
||
| 2102 | %ENC100_COMMENTS% #define ENC100_SI_RD_RW_TRIS (TRISGbits.TRISG8) // NOTE: SI is ENC624J600 Serial In, which needs to connect to the PIC SDO pin for SPI mode |
||
| 2103 | %ENC100_COMMENTS% #define ENC100_SI_RD_RW_IO (LATGbits.LATG8) |
||
| 2104 | %ENC100_COMMENTS% #define ENC100_SCK_AL_TRIS (TRISGbits.TRISG6) |
||
| 2105 | %ENC100_COMMENTS% #define ENC100_SCK_AL_IO (PORTGbits.RG6) // NOTE: This must be the PORT, not the LATch like it is for the PSP interface. |
||
| 2106 | %ENC100_COMMENTS% #endif |
||
| 2107 | %ENC100_COMMENTS% #endif |
||
| 2108 | %ENC100_COMMENTS% |
||
| 2109 | %ENC100_COMMENTS% |
||
| 2110 | %ENC100_COMMENTS% // ENC624J600 SPI SFR register selection (controls which SPI peripheral to |
||
| 2111 | %ENC100_COMMENTS% // use on PICs with multiple SPI peripherals). If a parallel interface is |
||
| 2112 | %ENC100_COMMENTS% // used (ENC100_INTERFACE_MODE is >= 1), then the SPI is not used and this |
||
| 2113 | %ENC100_COMMENTS% // section can be ignored or deleted. |
||
| 2114 | %ENC100_COMMENTS% #if defined ENC_IN_SPI1 |
||
| 2115 | %ENC100_COMMENTS% #define ENC100_ISR_ENABLE (IEC0bits.INT2IE) |
||
| 2116 | %ENC100_COMMENTS% #define ENC100_ISR_FLAG (IFS0bits.INT2IF) |
||
| 2117 | %ENC100_COMMENTS% #define ENC100_ISR_POLARITY (INTCONbits.INT2EP) |
||
| 2118 | %ENC100_COMMENTS% #define ENC100_ISR_PRIORITY (IPC2bits.INT2IP) |
||
| 2119 | %ENC100_COMMENTS% #define ENC100_SPI_ENABLE (ENC100_SPICON1bits.ON) |
||
| 2120 | %ENC100_COMMENTS% #define ENC100_SPI_IF (IFS0bits.SPI1RXIF) |
||
| 2121 | %ENC100_COMMENTS% #define ENC100_SSPBUF (SPI1BUF) |
||
| 2122 | %ENC100_COMMENTS% #define ENC100_SPICON1 (SPI1CON) |
||
| 2123 | %ENC100_COMMENTS% #define ENC100_SPISTATbits (SPI1STATbits) |
||
| 2124 | %ENC100_COMMENTS% #define ENC100_SPICON1bits (SPI1CONbits) |
||
| 2125 | %ENC100_COMMENTS% #define ENC100_SPIBRG (SPI1BRG) |
||
| 2126 | %ENC100_COMMENTS% #elif defined ENC_IN_SPI2 |
||
| 2127 | %ENC100_COMMENTS% #define ENC100_ISR_ENABLE (IEC0bits.INT4IE) |
||
| 2128 | %ENC100_COMMENTS% #define ENC100_ISR_FLAG (IFS0bits.INT4IF) |
||
| 2129 | %ENC100_COMMENTS% #define ENC100_ISR_POLARITY (INTCONbits.INT4EP) |
||
| 2130 | %ENC100_COMMENTS% #define ENC100_ISR_PRIORITY (IPC2bits.INT4IP) |
||
| 2131 | %ENC100_COMMENTS% #define ENC100_SPI_ENABLE (ENC100_SPICON1bits.ON) |
||
| 2132 | %ENC100_COMMENTS% #define ENC100_SPI_IF (IFS1bits.SPI2RXIF) |
||
| 2133 | %ENC100_COMMENTS% #define ENC100_SSPBUF (SPI2BUF) |
||
| 2134 | %ENC100_COMMENTS% #define ENC100_SPICON1 (SPI2CON) |
||
| 2135 | %ENC100_COMMENTS% #define ENC100_SPISTATbits (SPI2STATbits) |
||
| 2136 | %ENC100_COMMENTS% #define ENC100_SPICON1bits (SPI2CONbits) |
||
| 2137 | %ENC100_COMMENTS% #define ENC100_SPIBRG (SPI2BRG) |
||
| 2138 | %ENC100_COMMENTS% #endif |
||
| 2139 | |||
| 2140 | |||
| 2141 | %MRF24WB0M_COMMENTS% //---------------------------- |
||
| 2142 | %MRF24WB0M_COMMENTS% // MRF24WB0M WiFi I/O pins |
||
| 2143 | %MRF24WB0M_COMMENTS% //---------------------------- |
||
| 2144 | %MRF24WB0M_COMMENTS% // If you have a MRF24WB0M WiFi PICtail, you must uncomment one of |
||
| 2145 | %MRF24WB0M_COMMENTS% // these two lines to use it. SPI1 is the top-most slot while SPI2 corresponds to |
||
| 2146 | %MRF24WB0M_COMMENTS% // insertion of the PICtail into the middle of the side edge connector slot. |
||
| 2147 | %MRF24WB0M_COMMENTS% |
||
| 2148 | %MRF24WB0M_COMMENTS% %MRF24WB0M_IN_SPI1%#define MRF24WB0M_IN_SPI1 |
||
| 2149 | %MRF24WB0M_COMMENTS% %MRF24WB0M_IN_SPI2%#define MRF24WB0M_IN_SPI2 |
||
| 2150 | %MRF24WB0M_COMMENTS% #if defined( MRF24WB0M_IN_SPI1 ) |
||
| 2151 | %MRF24WB0M_COMMENTS% // MRF24WB0M in SPI1 slot |
||
| 2152 | %MRF24WB0M_COMMENTS% #define WF_CS_TRIS (TRISBbits.TRISB2) |
||
| 2153 | %MRF24WB0M_COMMENTS% #define WF_CS_IO (LATBbits.LATB2) |
||
| 2154 | %MRF24WB0M_COMMENTS% #define WF_SDI_TRIS (TRISFbits.TRISF7) |
||
| 2155 | %MRF24WB0M_COMMENTS% #define WF_SCK_TRIS (TRISFbits.TRISF6) |
||
| 2156 | %MRF24WB0M_COMMENTS% #define WF_SDO_TRIS (TRISFbits.TRISF8) |
||
| 2157 | %MRF24WB0M_COMMENTS% #define WF_RESET_TRIS (TRISFbits.TRISF0) |
||
| 2158 | %MRF24WB0M_COMMENTS% #define WF_RESET_IO (LATFbits.LATF0) |
||
| 2159 | %MRF24WB0M_COMMENTS% #define WF_INT_TRIS (TRISEbits.TRISE8) // INT1 |
||
| 2160 | %MRF24WB0M_COMMENTS% #define WF_INT_IO (PORTEbits.RE8) |
||
| 2161 | %MRF24WB0M_COMMENTS% #define WF_HIBERNATE_TRIS (TRISFbits.TRISF1) |
||
| 2162 | %MRF24WB0M_COMMENTS% #define WF_HIBERNATE_IO (PORTFbits.RF1) |
||
| 2163 | %MRF24WB0M_COMMENTS% #define WF_INT_EDGE (INTCONbits.INT1EP) |
||
| 2164 | %MRF24WB0M_COMMENTS% #define WF_INT_IE (IEC0bits.INT1IE) |
||
| 2165 | %MRF24WB0M_COMMENTS% #define WF_INT_IF (IFS0bits.INT1IF) |
||
| 2166 | %MRF24WB0M_COMMENTS% #define WF_INT_IE_CLEAR IEC0CLR |
||
| 2167 | %MRF24WB0M_COMMENTS% #define WF_INT_IF_CLEAR IFS0CLR |
||
| 2168 | %MRF24WB0M_COMMENTS% #define WF_INT_IE_SET IEC0SET |
||
| 2169 | %MRF24WB0M_COMMENTS% #define WF_INT_IF_SET IFS0SET |
||
| 2170 | %MRF24WB0M_COMMENTS% #define WF_INT_BIT 0x00000080 |
||
| 2171 | %MRF24WB0M_COMMENTS% #define WF_INT_IPCSET IPC1SET |
||
| 2172 | %MRF24WB0M_COMMENTS% #define WF_INT_IPCCLR IPC1CLR |
||
| 2173 | %MRF24WB0M_COMMENTS% #define WF_INT_IPC_MASK 0xFF000000 |
||
| 2174 | %MRF24WB0M_COMMENTS% #define WF_INT_IPC_VALUE 0x0C000000 |
||
| 2175 | %MRF24WB0M_COMMENTS% |
||
| 2176 | %MRF24WB0M_COMMENTS% #define WF_SSPBUF (SPI1BUF) |
||
| 2177 | %MRF24WB0M_COMMENTS% #define WF_SPISTAT (SPI1STAT) |
||
| 2178 | %MRF24WB0M_COMMENTS% #define WF_SPISTATbits (SPI1STATbits) |
||
| 2179 | %MRF24WB0M_COMMENTS% #define WF_SPICON1 (SPI1CON) |
||
| 2180 | %MRF24WB0M_COMMENTS% #define WF_SPICON1bits (SPI1CONbits) |
||
| 2181 | %MRF24WB0M_COMMENTS% #define WF_SPI_IE_CLEAR IEC0CLR |
||
| 2182 | %MRF24WB0M_COMMENTS% #define WF_SPI_IF_CLEAR IFS0CLR |
||
| 2183 | %MRF24WB0M_COMMENTS% #define WF_SPI_INT_BITS 0x03800000 |
||
| 2184 | %MRF24WB0M_COMMENTS% #define WF_SPI_BRG (SPI1BRG) |
||
| 2185 | %MRF24WB0M_COMMENTS% #define WF_MAX_SPI_FREQ (10000000ul) // Hz |
||
| 2186 | %MRF24WB0M_COMMENTS% |
||
| 2187 | %MRF24WB0M_COMMENTS% #elif defined( MRF24WB0M_IN_SPI2 ) |
||
| 2188 | %MRF24WB0M_COMMENTS% // MRF24WB0M in SPI2 slot |
||
| 2189 | %MRF24WB0M_COMMENTS% #define WF_CS_TRIS (TRISGbits.TRISG9) |
||
| 2190 | %MRF24WB0M_COMMENTS% #define WF_CS_IO (LATGbits.LATG9) |
||
| 2191 | %MRF24WB0M_COMMENTS% #define WF_SDI_TRIS (TRISGbits.TRISG7) |
||
| 2192 | %MRF24WB0M_COMMENTS% #define WF_SCK_TRIS (TRISGbits.TRISG6) |
||
| 2193 | %MRF24WB0M_COMMENTS% #define WF_SDO_TRIS (TRISGbits.TRISG8) |
||
| 2194 | %MRF24WB0M_COMMENTS% #define WF_RESET_TRIS (TRISGbits.TRISG0) |
||
| 2195 | %MRF24WB0M_COMMENTS% #define WF_RESET_IO (LATGbits.LATG0) |
||
| 2196 | %MRF24WB0M_COMMENTS% #define WF_INT_TRIS (TRISAbits.TRISA14) // INT3 |
||
| 2197 | %MRF24WB0M_COMMENTS% #define WF_INT_IO (PORTAbits.RA14) |
||
| 2198 | %MRF24WB0M_COMMENTS% #define WF_HIBERNATE_TRIS (TRISGbits.TRISG1) |
||
| 2199 | %MRF24WB0M_COMMENTS% #define WF_HIBERNATE_IO (PORTGbits.RG1) |
||
| 2200 | %MRF24WB0M_COMMENTS% #define WF_INT_EDGE (INTCONbits.INT3EP) |
||
| 2201 | %MRF24WB0M_COMMENTS% #define WF_INT_IE (IEC0bits.INT3IE) |
||
| 2202 | %MRF24WB0M_COMMENTS% #define WF_INT_IF (IFS0bits.INT3IF) |
||
| 2203 | %MRF24WB0M_COMMENTS% #define WF_INT_IE_CLEAR IEC0CLR |
||
| 2204 | %MRF24WB0M_COMMENTS% #define WF_INT_IF_CLEAR IFS0CLR |
||
| 2205 | %MRF24WB0M_COMMENTS% #define WF_INT_IE_SET IEC0SET |
||
| 2206 | %MRF24WB0M_COMMENTS% #define WF_INT_IF_SET IFS0SET |
||
| 2207 | %MRF24WB0M_COMMENTS% #define WF_INT_BIT 0x00008000 |
||
| 2208 | %MRF24WB0M_COMMENTS% #define WF_INT_IPCSET IPC3SET |
||
| 2209 | %MRF24WB0M_COMMENTS% #define WF_INT_IPCCLR IPC3CLR |
||
| 2210 | %MRF24WB0M_COMMENTS% #define WF_INT_IPC_MASK 0xFF000000 |
||
| 2211 | %MRF24WB0M_COMMENTS% #define WF_INT_IPC_VALUE 0x0C000000 |
||
| 2212 | %MRF24WB0M_COMMENTS% |
||
| 2213 | %MRF24WB0M_COMMENTS% #define WF_SSPBUF (SPI2BUF) |
||
| 2214 | %MRF24WB0M_COMMENTS% #define WF_SPISTAT (SPI2STAT) |
||
| 2215 | %MRF24WB0M_COMMENTS% #define WF_SPISTATbits (SPI2STATbits) |
||
| 2216 | %MRF24WB0M_COMMENTS% #define WF_SPICON1 (SPI2CON) |
||
| 2217 | %MRF24WB0M_COMMENTS% #define WF_SPICON1bits (SPI2CONbits) |
||
| 2218 | %MRF24WB0M_COMMENTS% #define WF_SPI_IE_CLEAR IEC1CLR |
||
| 2219 | %MRF24WB0M_COMMENTS% #define WF_SPI_IF_CLEAR IFS1CLR |
||
| 2220 | %MRF24WB0M_COMMENTS% #define WF_SPI_INT_BITS 0x000000e0 |
||
| 2221 | %MRF24WB0M_COMMENTS% #define WF_SPI_BRG (SPI2BRG) |
||
| 2222 | %MRF24WB0M_COMMENTS% #define WF_MAX_SPI_FREQ (10000000ul) // Hz |
||
| 2223 | %MRF24WB0M_COMMENTS% #endif |
||
| 2224 | |||
| 2225 | |||
| 2226 | #elif defined(PIC32_ENET_SK_DM320004) |
||
| 2227 | // PIC32 Ethernet Starter Kit (04-02146) with PIC32MX795F512L processor and National DP83848 10/100 PHY |
||
| 2228 | // External SMSC PHY configuration |
||
| 2229 | #define PHY_RMII // external PHY runs in RMII mode |
||
| 2230 | #define PHY_CONFIG_ALTERNATE // alternate configuration used |
||
| 2231 | #define PHY_ADDRESS 0x1 // the address of the National DP83848 PHY |
||
| 2232 | |||
| 2233 | // Hardware mappings |
||
| 2234 | #define LED0_TRIS (TRISDbits.TRISD0) // Ref LED1 |
||
| 2235 | #define LED0_IO (LATDbits.LATD0) |
||
| 2236 | #define LED1_TRIS (TRISDbits.TRISD1) // Ref LED2 |
||
| 2237 | #define LED1_IO (LATDbits.LATD1) |
||
| 2238 | #define LED2_TRIS (TRISDbits.TRISD2) // Ref LED3 |
||
| 2239 | #define LED2_IO (LATDbits.LATD2) |
||
| 2240 | #define LED3_TRIS (LED2_TRIS) // No such LED |
||
| 2241 | #define LED3_IO (LATDbits.LATD6) |
||
| 2242 | #define LED4_TRIS (LED2_TRIS) // No such LED |
||
| 2243 | #define LED4_IO (LATDbits.LATD6) |
||
| 2244 | #define LED5_TRIS (LED2_TRIS) // No such LED |
||
| 2245 | #define LED5_IO (LATDbits.LATD6) |
||
| 2246 | #define LED6_TRIS (LED2_TRIS) // No such LED |
||
| 2247 | #define LED6_IO (LATDbits.LATD6) |
||
| 2248 | #define LED7_TRIS (LED2_TRIS) // No such LED |
||
| 2249 | #define LED7_IO (LATDbits.LATD6) |
||
| 2250 | |||
| 2251 | #define LED_GET() ((BYTE)LATD & 0x07) |
||
| 2252 | #define LED_PUT(a) do{LATD = (LATD & 0xFFF8) | ((a)&0x07);}while(0) |
||
| 2253 | |||
| 2254 | #define BUTTON0_TRIS (TRISDbits.TRISD6) // Ref SW1 |
||
| 2255 | #define BUTTON0_IO (PORTDbits.RD6) |
||
| 2256 | #define BUTTON1_TRIS (TRISDbits.TRISD7) // Ref SW2 |
||
| 2257 | #define BUTTON1_IO (PORTDbits.RD7) |
||
| 2258 | #define BUTTON2_TRIS (TRISDbits.TRISD13) // Ref SW3 |
||
| 2259 | #define BUTTON2_IO (PORTDbits.RD13) |
||
| 2260 | #define BUTTON3_TRIS (TRISDbits.TRISD13) // No BUTTON3 on this board |
||
| 2261 | #define BUTTON3_IO (1) |
||
| 2262 | |||
| 2263 | |||
| 2264 | // Note, it is not possible to use a MRF24WB0M 802.11 WiFi PICtail |
||
| 2265 | // Plus card with this starter kit. The required interrupt signal, among |
||
| 2266 | // possibly other I/O pins aren't available on the Starter Kit board. |
||
| 2267 | |||
| 2268 | #elif defined(PIC24FJ256DA210_DEV_BOARD) |
||
| 2269 | // PIC24FJ256DA210 Development Board (Graphics) + |
||
| 2270 | // Fast 100Mbps Ethernet PICtail Plus or Ethernet PICtail Plus or MRF24WB0M WiFi PICtail Plus |
||
| 2271 | |||
| 2272 | #define LED0_TRIS (TRISAbits.TRISA7) // Ref D4: Jumper JP11 must have a shunt shorting pins 1 and 2 together |
||
| 2273 | #define LED0_IO (LATAbits.LATA7) |
||
| 2274 | #define LED1_TRIS (((BYTE*)&NVMKEY)[1]) // No such LED, map to dummy register. D3 is the natural choice for LED0, but the D3 pin (RB5) is multiplexed with R3 potentiometer and MDIX signal on Fast 100Mbps Ethernet PICtail Plus, so it cannot be used |
||
| 2275 | #define LED1_IO (((BYTE*)&NVMKEY)[1]) |
||
| 2276 | #define LED2_TRIS (TRISEbits.TRISE9) // Ref D2. NOTE: When using the PSP interface, this RE9 signal also controls the POR (SHDN) signal on the Fast 100Mbps Ethernet PICtail Plus. |
||
| 2277 | #define LED2_IO (LATEbits.LATE9) |
||
| 2278 | #define LED3_TRIS (TRISGbits.TRISG8) // Ref D1. NOTE: When using the PSP interface, this RG8 signal also controls the CS signal on the Fast 100Mbps Ethernet PICtail Plus. |
||
| 2279 | #define LED3_IO (LATGbits.LATG8) |
||
| 2280 | #define LED4_TRIS (((BYTE*)&NVMKEY)[1]) // No such LED, map to dummy register |
||
| 2281 | #define LED4_IO (((BYTE*)&NVMKEY)[1]) |
||
| 2282 | #define LED5_TRIS (((BYTE*)&NVMKEY)[1]) // No such LED, map to dummy register |
||
| 2283 | #define LED5_IO (((BYTE*)&NVMKEY)[1]) |
||
| 2284 | #define LED6_TRIS (((BYTE*)&NVMKEY)[1]) // No such LED, map to dummy register |
||
| 2285 | #define LED6_IO (((BYTE*)&NVMKEY)[1]) |
||
| 2286 | #define LED7_TRIS (((BYTE*)&NVMKEY)[1]) // No such LED, map to dummy register |
||
| 2287 | #define LED7_IO (((BYTE*)&NVMKEY)[1]) |
||
| 2288 | #define LED_GET() ((LATGbits.LATG8<<3) | (LATEbits.LATE9<<2) | LATAbits.LATA7) |
||
| 2289 | #define LED_PUT(a) do{BYTE vTemp = (a); LED0_IO = vTemp&0x1; LED2_IO = vTemp&0x4; LED3_IO = vTemp&0x8;} while(0) |
||
| 2290 | |||
| 2291 | |||
| 2292 | #define BUTTON0_TRIS (((BYTE*)&NVMKEY)[1]) // Ref S3: NOTE: This pin is multiplexed with D3 and cannot be used simulatneously. Therefore, we will pretend there is no such button. |
||
| 2293 | #define BUTTON0_IO (1) |
||
| 2294 | #define BUTTON1_TRIS (((BYTE*)&NVMKEY)[1]) // Ref S2: NOTE: This pin is multiplexed with D2 and cannot be used simulatneously. Therefore, we will pretend there is no such button. |
||
| 2295 | #define BUTTON1_IO (1) |
||
| 2296 | #define BUTTON2_TRIS (((BYTE*)&NVMKEY)[1]) // Ref S1: NOTE: This pin is multiplexed with D1 and cannot be used simulatneously. Therefore, we will pretend there is no such button. |
||
| 2297 | #define BUTTON2_IO (1) |
||
| 2298 | #define BUTTON3_TRIS (((BYTE*)&NVMKEY)[1]) // No such button |
||
| 2299 | #define BUTTON3_IO (1) |
||
| 2300 | |||
| 2301 | |||
| 2302 | #define UARTTX_TRIS (TRISFbits.TRISF3) |
||
| 2303 | #define UARTTX_IO (PORTFbits.RF3) |
||
| 2304 | #define UARTRX_TRIS (TRISDbits.TRISD0) |
||
| 2305 | #define UARTRX_IO (PORTDbits.RD0) |
||
| 2306 | |||
| 2307 | |||
| 2308 | // NOTE: You must also set SPIFlash.h file to define SPI_FLASH_SST, define |
||
| 2309 | // SPI_FLASH_SECTOR_SIZE as 4096, and define SPI_FLASH_PAGE_SIZE as 0. |
||
| 2310 | // Jumper JP23 must have a shunt shorting pins 2-3 (not the default). |
||
| 2311 | // SST SST25VF016B (16Mbit/2Mbyte) |
||
| 2312 | #define SPIFLASH_CS_TRIS (TRISAbits.TRISA14) |
||
| 2313 | #define SPIFLASH_CS_IO (LATAbits.LATA14) |
||
| 2314 | #define SPIFLASH_SCK_TRIS (TRISDbits.TRISD8) |
||
| 2315 | #define SPIFLASH_SDI_TRIS (TRISBbits.TRISB0) |
||
| 2316 | #define SPIFLASH_SDI_IO (PORTBbits.RB0) |
||
| 2317 | #define SPIFLASH_SDO_TRIS (TRISBbits.TRISB1) |
||
| 2318 | #define SPIFLASH_SPI_IF (IFS0bits.SPI1IF) |
||
| 2319 | #define SPIFLASH_SSPBUF (SPI1BUF) |
||
| 2320 | #define SPIFLASH_SPICON1 (SPI1CON1) |
||
| 2321 | #define SPIFLASH_SPICON1bits (SPI1CON1bits) |
||
| 2322 | #define SPIFLASH_SPICON2 (SPI1CON2) |
||
| 2323 | #define SPIFLASH_SPISTAT (SPI1STAT) |
||
| 2324 | #define SPIFLASH_SPISTATbits (SPI1STATbits) |
||
| 2325 | |||
| 2326 | |||
| 2327 | %ENC28J60_COMMENTS% // ENC28J60 I/O pins |
||
| 2328 | %ENC28J60_COMMENTS% #define ENC_CS_TRIS (TRISGbits.TRISG6) // Comment this line out if you are using the ENC424J600/624J600, MRF24WB0M, or other network controller. |
||
| 2329 | %ENC28J60_COMMENTS% #define ENC_CS_IO (LATGbits.LATG6) |
||
| 2330 | %ENC28J60_COMMENTS% //#define ENC_RST_TRIS (TRISAbits.TRISA7) // Not connected by default. It is okay to leave this pin completely unconnected, in which case this macro should simply be left undefined. |
||
| 2331 | %ENC28J60_COMMENTS% //#define ENC_RST_IO (LATAbits.LATA7) |
||
| 2332 | %ENC28J60_COMMENTS% // SPI SCK, SDI, SDO pins are automatically controlled by the |
||
| 2333 | %ENC28J60_COMMENTS% // PIC24 SPI module, but Peripheral Pin Select must be configured correctly. |
||
| 2334 | %ENC28J60_COMMENTS% // MISO = RB0 (RP0); MOSI = RB1 (RP1); SCK = RD8 (RP2) |
||
| 2335 | %ENC28J60_COMMENTS% #define ENC_SPI_IF (IFS0bits.SPI1IF) |
||
| 2336 | %ENC28J60_COMMENTS% #define ENC_SSPBUF (SPI1BUF) |
||
| 2337 | %ENC28J60_COMMENTS% #define ENC_SPISTAT (SPI1STAT) |
||
| 2338 | %ENC28J60_COMMENTS% #define ENC_SPISTATbits (SPI1STATbits) |
||
| 2339 | %ENC28J60_COMMENTS% #define ENC_SPICON1 (SPI1CON1) |
||
| 2340 | %ENC28J60_COMMENTS% #define ENC_SPICON1bits (SPI1CON1bits) |
||
| 2341 | %ENC28J60_COMMENTS% #define ENC_SPICON2 (SPI1CON2) |
||
| 2342 | |||
| 2343 | |||
| 2344 | %ENC100_COMMENTS% // ENC624J600 Interface Configuration |
||
| 2345 | %ENC100_COMMENTS% // Comment out ENC100_INTERFACE_MODE if you don't have an ENC624J600 or |
||
| 2346 | %ENC100_COMMENTS% // ENC424J600. Otherwise, choose the correct setting for the interface you |
||
| 2347 | %ENC100_COMMENTS% // are using. Legal values are: |
||
| 2348 | %ENC100_COMMENTS% // - Commented out: No ENC424J600/624J600 present or used. All other |
||
| 2349 | %ENC100_COMMENTS% // ENC100_* macros are ignored. |
||
| 2350 | %ENC100_COMMENTS% // - 0: SPI mode using CS, SCK, SI, and SO pins |
||
| 2351 | %ENC100_COMMENTS% // - 1: 8-bit demultiplexed PSP Mode 1 with RD and WR pins |
||
| 2352 | %ENC100_COMMENTS% // - 2: 8-bit demultiplexed PSP Mode 2 with R/Wbar and EN pins |
||
| 2353 | %ENC100_COMMENTS% // - 3: 16-bit demultiplexed PSP Mode 3 with RD, WRL, and WRH pins |
||
| 2354 | %ENC100_COMMENTS% // - 4: 16-bit demultiplexed PSP Mode 4 with R/Wbar, B0SEL, and B1SEL pins |
||
| 2355 | %ENC100_COMMENTS% // - 5: 8-bit multiplexed PSP Mode 5 with RD and WR pins |
||
| 2356 | %ENC100_COMMENTS% // - 6: 8-bit multiplexed PSP Mode 6 with R/Wbar and EN pins |
||
| 2357 | %ENC100_COMMENTS% // - 9: 16-bit multiplexed PSP Mode 9 with AL, RD, WRL, and WRH pins |
||
| 2358 | %ENC100_COMMENTS% // - 10: 16-bit multiplexed PSP Mode 10 with AL, R/Wbar, B0SEL, and B1SEL |
||
| 2359 | %ENC100_COMMENTS% // pins |
||
| 2360 | %ENC100_COMMENTS% #define ENC100_INTERFACE_MODE %ENC100_INTERFACE_MODE% |
||
| 2361 | %ENC100_COMMENTS% |
||
| 2362 | %ENC100_COMMENTS% // If using a parallel interface, direct RAM addressing can be used (if all |
||
| 2363 | %ENC100_COMMENTS% // addresses wires are connected), or a reduced number of pins can be used |
||
| 2364 | %ENC100_COMMENTS% // for indirect addressing. If using an SPI interface or PSP Mode 9 or 10 |
||
| 2365 | %ENC100_COMMENTS% // (multiplexed 16-bit modes), which require all address lines to always be |
||
| 2366 | %ENC100_COMMENTS% // connected, then this option is ignored. Comment out or uncomment this |
||
| 2367 | %ENC100_COMMENTS% // macro to match your hardware connections. |
||
| 2368 | %ENC100_COMMENTS% #define ENC100_PSP_USE_INDIRECT_RAM_ADDRESSING |
||
| 2369 | %ENC100_COMMENTS% |
||
| 2370 | %ENC100_COMMENTS% // ENC424J600/624J600 parallel indirect address remapping macro function. |
||
| 2371 | %ENC100_COMMENTS% // This section translates SFR and RAM addresses presented to the |
||
| 2372 | %ENC100_COMMENTS% // ReadMemory() and WriteMemory() APIs in ENCX24J600.c to the actual |
||
| 2373 | %ENC100_COMMENTS% // addresses that must be presented on the parallel interface. This macro |
||
| 2374 | %ENC100_COMMENTS% // must be modified to match your hardware if you are using an indirect PSP |
||
| 2375 | %ENC100_COMMENTS% // addressing mode (ENC100_PSP_USE_INDIRECT_RAM_ADDRESSING is defined) and |
||
| 2376 | %ENC100_COMMENTS% // have some of your address lines tied off to Vdd. If you are using the |
||
| 2377 | %ENC100_COMMENTS% // SPI interface, then this section can be ignored or deleted. |
||
| 2378 | %ENC100_COMMENTS% #if (ENC100_INTERFACE_MODE == 1) || (ENC100_INTERFACE_MODE == 2) || (ENC100_INTERFACE_MODE == 5) || (ENC100_INTERFACE_MODE == 6) // 8-bit PSP |
||
| 2379 | %ENC100_COMMENTS% #define ENC100_TRANSLATE_TO_PIN_ADDR(a) ((((a)&0x0100)<<6) | ((a)&0x00FF)) |
||
| 2380 | %ENC100_COMMENTS% #elif (ENC100_INTERFACE_MODE == 3) || (ENC100_INTERFACE_MODE == 4) // 16-bit PSP |
||
| 2381 | %ENC100_COMMENTS% #define ENC100_TRANSLATE_TO_PIN_ADDR(a) (a) |
||
| 2382 | %ENC100_COMMENTS% #endif |
||
| 2383 | %ENC100_COMMENTS% |
||
| 2384 | %ENC100_COMMENTS% // Auto-crossover pins on Fast 100Mbps Ethernet PICtail/PICtail Plus. If |
||
| 2385 | %ENC100_COMMENTS% // your circuit doesn't have such a feature, delete these two defines. |
||
| 2386 | %ENC100_COMMENTS% #define ENC100_MDIX_TRIS (TRISBbits.TRISB5) |
||
| 2387 | %ENC100_COMMENTS% #define ENC100_MDIX_IO (LATBbits.LATB5) |
||
| 2388 | %ENC100_COMMENTS% |
||
| 2389 | %ENC100_COMMENTS% // ENC624J600 I/O control and status pins |
||
| 2390 | %ENC100_COMMENTS% // If a pin is not required for your selected ENC100_INTERFACE_MODE |
||
| 2391 | %ENC100_COMMENTS% // interface selection (ex: WRH/B1SEL for PSP modes 1, 2, 5, and 6), then |
||
| 2392 | %ENC100_COMMENTS% // you can ignore, delete, or put anything for the pin definition. Also, |
||
| 2393 | %ENC100_COMMENTS% // the INT and POR pins are entirely optional. If not connected, comment |
||
| 2394 | %ENC100_COMMENTS% // them out. |
||
| 2395 | %ENC100_COMMENTS% #define ENC100_INT_TRIS (TRISAbits.TRISA15) // INT signal is optional and currently unused in the Microchip TCP/IP Stack. Leave this pin disconnected and comment out this pin definition if you don't want it. |
||
| 2396 | %ENC100_COMMENTS% #define ENC100_INT_IO (PORTAbits.RA15) |
||
| 2397 | %ENC100_COMMENTS% #if (ENC100_INTERFACE_MODE >= 1) // Parallel mode |
||
| 2398 | %ENC100_COMMENTS% // PSP control signal pinout |
||
| 2399 | %ENC100_COMMENTS% #define ENC100_CS_TRIS (TRISGbits.TRISG8) // CS is optional in PSP mode. If you are not sharing the parallel bus with another device, tie CS to Vdd and comment out this pin definition. |
||
| 2400 | %ENC100_COMMENTS% #define ENC100_CS_IO (LATGbits.LATG8) |
||
| 2401 | %ENC100_COMMENTS% #define ENC100_POR_TRIS (TRISEbits.TRISE9) // POR signal is optional. If your application doesn't have a power disconnect feature, comment out this pin definition. |
||
| 2402 | %ENC100_COMMENTS% #define ENC100_POR_IO (LATEbits.LATE9) |
||
| 2403 | %ENC100_COMMENTS% #define ENC100_SO_WR_B0SEL_EN_TRIS (TRISDbits.TRISD4) |
||
| 2404 | %ENC100_COMMENTS% #define ENC100_SO_WR_B0SEL_EN_IO (LATDbits.LATD4) |
||
| 2405 | %ENC100_COMMENTS% #define ENC100_SI_RD_RW_TRIS (TRISDbits.TRISD5) |
||
| 2406 | %ENC100_COMMENTS% #define ENC100_SI_RD_RW_IO (LATDbits.LATD5) |
||
| 2407 | %ENC100_COMMENTS% #define ENC100_SCK_AL_TRIS (TRISBbits.TRISB15) |
||
| 2408 | %ENC100_COMMENTS% #define ENC100_SCK_AL_IO (LATBbits.LATB15) |
||
| 2409 | %ENC100_COMMENTS% #undef LED1_TRIS |
||
| 2410 | %ENC100_COMMENTS% #undef LED1_IO |
||
| 2411 | %ENC100_COMMENTS% #undef LED2_TRIS |
||
| 2412 | %ENC100_COMMENTS% #undef LED2_IO |
||
| 2413 | %ENC100_COMMENTS% #undef LED_GET |
||
| 2414 | %ENC100_COMMENTS% #undef LED_PUT |
||
| 2415 | %ENC100_COMMENTS% #define LED1_TRIS (((BYTE*)&NVMKEY)[1]) // No such LED, map to dummy register. This is required with the Fast 100Mbps Ethernet PICtail Plus in parallel mode because this RE9 signal also controls the POR (SHDN) signal. |
||
| 2416 | %ENC100_COMMENTS% #define LED1_IO (((BYTE*)&NVMKEY)[1]) |
||
| 2417 | %ENC100_COMMENTS% #define LED2_TRIS (((BYTE*)&NVMKEY)[1]) // No such LED, map to dummy register. This is required with the Fast 100Mbps Ethernet PICtail Plus in parallel mode because this RG8 signal also controls the CS signal. |
||
| 2418 | %ENC100_COMMENTS% #define LED2_IO (((BYTE*)&NVMKEY)[1]) |
||
| 2419 | %ENC100_COMMENTS% #define LED_GET() LED0_IO |
||
| 2420 | %ENC100_COMMENTS% #define LED_PUT(a) (LED0_IO = (a) & 0x1) |
||
| 2421 | %ENC100_COMMENTS% #else |
||
| 2422 | %ENC100_COMMENTS% // SPI pinout |
||
| 2423 | %ENC100_COMMENTS% #define ENC100_CS_TRIS (TRISGbits.TRISG6) // CS is mandatory when using the SPI interface |
||
| 2424 | %ENC100_COMMENTS% #define ENC100_CS_IO (LATGbits.LATG6) |
||
| 2425 | %ENC100_COMMENTS% #define ENC100_POR_TRIS (TRISCbits.TRISC13) // POR signal is optional. If your application doesn't have a power disconnect feature, comment out this pin definition. |
||
| 2426 | %ENC100_COMMENTS% #define ENC100_POR_IO (LATCbits.LATC13) |
||
| 2427 | %ENC100_COMMENTS% #define ENC100_SO_WR_B0SEL_EN_TRIS (TRISBbits.TRISB0) // SO is ENCX24J600 Serial Out, which needs to connect to the PIC SDI pin for SPI mode |
||
| 2428 | %ENC100_COMMENTS% #define ENC100_SO_WR_B0SEL_EN_IO (PORTBbits.RB0) |
||
| 2429 | %ENC100_COMMENTS% #define ENC100_SI_RD_RW_TRIS (TRISBbits.TRISB1) // SI is ENCX24J600 Serial In, which needs to connect to the PIC SDO pin for SPI mode |
||
| 2430 | %ENC100_COMMENTS% #define ENC100_SI_RD_RW_IO (LATBbits.LATB1) |
||
| 2431 | %ENC100_COMMENTS% #define ENC100_SCK_AL_TRIS (TRISDbits.TRISD8) |
||
| 2432 | %ENC100_COMMENTS% #endif |
||
| 2433 | %ENC100_COMMENTS% |
||
| 2434 | %ENC100_COMMENTS% |
||
| 2435 | %ENC100_COMMENTS% // ENC624J600 SPI SFR register selection (controls which SPI peripheral to |
||
| 2436 | %ENC100_COMMENTS% // use on PICs with multiple SPI peripherals). If a parallel interface is |
||
| 2437 | %ENC100_COMMENTS% // used (ENC100_INTERFACE_MODE is >= 1), then the SPI is not used and this |
||
| 2438 | %ENC100_COMMENTS% // section can be ignored or deleted. |
||
| 2439 | %ENC100_COMMENTS% #define ENC100_ISR_ENABLE (IEC1bits.INT2IE) |
||
| 2440 | %ENC100_COMMENTS% #define ENC100_ISR_FLAG (IFS1bits.INT2IF) |
||
| 2441 | %ENC100_COMMENTS% #define ENC100_ISR_POLARITY (INTCON2bits.INT2EP) |
||
| 2442 | %ENC100_COMMENTS% #define ENC100_ISR_PRIORITY (IPC7bits.INT2IP) |
||
| 2443 | %ENC100_COMMENTS% #define ENC100_SPI_ENABLE (ENC100_SPISTATbits.SPIEN) |
||
| 2444 | %ENC100_COMMENTS% #define ENC100_SPI_IF (IFS0bits.SPI1IF) |
||
| 2445 | %ENC100_COMMENTS% #define ENC100_SSPBUF (SPI1BUF) |
||
| 2446 | %ENC100_COMMENTS% #define ENC100_SPISTAT (SPI1STAT) |
||
| 2447 | %ENC100_COMMENTS% #define ENC100_SPISTATbits (SPI1STATbits) |
||
| 2448 | %ENC100_COMMENTS% #define ENC100_SPICON1 (SPI1CON1) |
||
| 2449 | %ENC100_COMMENTS% #define ENC100_SPICON1bits (SPI1CON1bits) |
||
| 2450 | %ENC100_COMMENTS% #define ENC100_SPICON2 (SPI1CON2) |
||
| 2451 | %ENC100_COMMENTS% |
||
| 2452 | %ENC100_COMMENTS% // ENC624J600 Bit Bang PSP I/O macros and pin configuration for address and |
||
| 2453 | %ENC100_COMMENTS% // data. If using the SPI interface (ENC100_INTERFACE_MODE is 0) then this |
||
| 2454 | %ENC100_COMMENTS% // section is not used and can be ignored or deleted. The Enhanced PMP |
||
| 2455 | %ENC100_COMMENTS% // module available on the PIC24FJ256DA210 family will not work with the |
||
| 2456 | %ENC100_COMMENTS% // ENC424J600/624J600, so bit bang mode must be used if parallel access is |
||
| 2457 | %ENC100_COMMENTS% // desired. |
||
| 2458 | %ENC100_COMMENTS% #define ENC100_BIT_BANG_PMP |
||
| 2459 | %ENC100_COMMENTS% #if defined(ENC100_BIT_BANG_PMP) |
||
| 2460 | %ENC100_COMMENTS% #if ENC100_INTERFACE_MODE == 1 || ENC100_INTERFACE_MODE == 2 // Dumultiplexed 8-bit address/data modes |
||
| 2461 | %ENC100_COMMENTS% #if defined(ENC100_PSP_USE_INDIRECT_RAM_ADDRESSING) // Only ENC624J600 address pins A0-A8 connected (A9-A14 tied to Vdd) |
||
| 2462 | %ENC100_COMMENTS% // AD0-AD7: "PMD0-PMD7" -> RE0-RE7 |
||
| 2463 | %ENC100_COMMENTS% // A0: "PMA0" -> RB15 |
||
| 2464 | %ENC100_COMMENTS% // A1: "PMA1" -> RB14 |
||
| 2465 | %ENC100_COMMENTS% // A2: "PMA2" -> RG9 |
||
| 2466 | %ENC100_COMMENTS% // A3: "PMA3" -> RA4 |
||
| 2467 | %ENC100_COMMENTS% // A4: "PMA4" -> RA3 |
||
| 2468 | %ENC100_COMMENTS% // A5: "PMA5" -> RF12 |
||
| 2469 | %ENC100_COMMENTS% // A6: "PMA6" -> RA10 |
||
| 2470 | %ENC100_COMMENTS% // A7: "PMA7" -> RA9 |
||
| 2471 | %ENC100_COMMENTS% // A8: "PMA14_TO_P104" "PMA14" -> RD11 |
||
| 2472 | %ENC100_COMMENTS% // RD: "PMRD/RD5" -> RD5 |
||
| 2473 | %ENC100_COMMENTS% // WR: "PMWR/RD4 -> RD4 |
||
| 2474 | %ENC100_COMMENTS% // CS: "AN19/RG8_TO_P72" "AN19/RG8" -> RG8 |
||
| 2475 | %ENC100_COMMENTS% #define ENC100_INIT_PSP_BIT_BANG() do{ANSA &= 0xF9E7; ANSB &= 0x3FFF; ANSG &= 0xFCFF;} while(0) // RE0-RE7, RF12, RD11, RD4, RD5 (AD0-AD7, A5, A8, WR, RD) pins are already digital only pins. |
||
| 2476 | %ENC100_COMMENTS% #define ENC100_SET_ADDR_TRIS_OUT() do{TRISA &= 0xF9E7; TRISB &= 0x3FFF; TRISFbits.TRISF12 = 0; TRISGbits.TRISG9 = 0; TRISDbits.TRISD11 = 0;}while(0) |
||
| 2477 | %ENC100_COMMENTS% #define ENC100_SET_ADDR_IO(a) do{WORD _SetMacro = (a); LATBbits.LATB15 = 0; LATBbits.LATB14 = 0; LATGbits.LATG9 = 0; LATA &= 0xF9E7; LATFbits.LATF12 = 0; LATDbits.LATD11 = 0; if(_SetMacro & 0x0001) LATBbits.LATB15 = 1; if(_SetMacro & 0x0002) LATBbits.LATB14 = 1; if(_SetMacro & 0x0004) LATGbits.LATG9 = 1; if(_SetMacro & 0x0008) LATAbits.LATA4 = 1; if(_SetMacro & 0x0010) LATAbits.LATA3 = 1; if(_SetMacro & 0x0020) LATFbits.LATF12 = 1; if(_SetMacro & 0x0040) LATAbits.LATA10 = 1; if(_SetMacro & 0x0080) LATAbits.LATA9 = 1; if(_SetMacro & 0x4000) LATDbits.LATD11 = 1;}while(0) |
||
| 2478 | %ENC100_COMMENTS% #define ENC100_SET_AD_TRIS_IN() (((volatile BYTE*)&TRISE)[0] = 0xFF) |
||
| 2479 | %ENC100_COMMENTS% #define ENC100_SET_AD_TRIS_OUT() (((volatile BYTE*)&TRISE)[0] = 0x00) |
||
| 2480 | %ENC100_COMMENTS% #define ENC100_GET_AD_IO() (((volatile BYTE*)&PORTE)[0]) |
||
| 2481 | %ENC100_COMMENTS% #define ENC100_SET_AD_IO(data) (((volatile BYTE*)&LATE)[0] = (BYTE)(data)) |
||
| 2482 | %ENC100_COMMENTS% #else // All ENC624J600 address pins A0-A14 connected |
||
| 2483 | %ENC100_COMMENTS% // AD0-AD7: "PMD0-PMD7" -> RE0-RE7 |
||
| 2484 | %ENC100_COMMENTS% // A0: "PMA0" -> RB15 |
||
| 2485 | %ENC100_COMMENTS% // A1: "PMA1" -> RB14 |
||
| 2486 | %ENC100_COMMENTS% // A2: "PMA2" -> RG9 |
||
| 2487 | %ENC100_COMMENTS% // A3: "PMA3" -> RA4 |
||
| 2488 | %ENC100_COMMENTS% // A4: "PMA4" -> RA3 |
||
| 2489 | %ENC100_COMMENTS% // A5: "PMA5" -> RF12 |
||
| 2490 | %ENC100_COMMENTS% // A6: "PMA6" -> RA10 |
||
| 2491 | %ENC100_COMMENTS% // A7: "PMA7" -> RA9 |
||
| 2492 | %ENC100_COMMENTS% // A8: "PMA8" -> RF5 |
||
| 2493 | %ENC100_COMMENTS% // A9: "PMA9" -> RF4 |
||
| 2494 | %ENC100_COMMENTS% // A10: "PMA10" -> RB13 |
||
| 2495 | %ENC100_COMMENTS% // A11: "PMA11" -> RB12 |
||
| 2496 | %ENC100_COMMENTS% // A12: "PMA12" -> RB11 |
||
| 2497 | %ENC100_COMMENTS% // A13: "PMA13" -> RB10 |
||
| 2498 | %ENC100_COMMENTS% // A14: "PMA14_TO_P104" "PMA14" -> RD11 |
||
| 2499 | %ENC100_COMMENTS% // RD: "PMRD/RD5" -> RD5 |
||
| 2500 | %ENC100_COMMENTS% // WR: "PMWR/RD4 -> RD4 |
||
| 2501 | %ENC100_COMMENTS% // CS: "AN19/RG8_TO_P72" "AN19/RG8" -> RG8 |
||
| 2502 | %ENC100_COMMENTS% #define ENC100_INIT_PSP_BIT_BANG() do{ANSA &= 0xF9E7; ANSB &= 0x03FF; ANSG &= 0xFCFF;} while(0) // RE0-RE7, RF12, RD11, RD4, RD5 (AD0-AD7, A5, A14, WR, RD) pins are already digital only pins. |
||
| 2503 | %ENC100_COMMENTS% #define ENC100_SET_ADDR_TRIS_OUT() do{TRISA &= 0xF9E7; TRISB &= 0x03FF; TRISF &= 0xEFCF; TRISGbits.TRISG9 = 0; TRISDbits.TRISD11 = 0;}while(0) |
||
| 2504 | %ENC100_COMMENTS% #define ENC100_SET_ADDR_IO(a) do{WORD _SetMacro = (a); LATA &= 0xF9E7; LATB &= 0x03FF; LATF &= 0xEFCF; LATGbits.LATG9 = 0; LATDbits.LATD11 = 0; if(_SetMacro & 0x0001) LATBbits.LATB15 = 1; if(_SetMacro & 0x0002) LATBbits.LATB14 = 1; if(_SetMacro & 0x0004) LATGbits.LATG9 = 1; if(_SetMacro & 0x0008) LATAbits.LATA4 = 1; if(_SetMacro & 0x0010) LATAbits.LATA3 = 1; if(_SetMacro & 0x0020) LATFbits.LATF12 = 1; if(_SetMacro & 0x0040) LATAbits.LATA10 = 1; if(_SetMacro & 0x0080) LATAbits.LATA9 = 1; if(_SetMacro & 0x0100) LATFbits.LATF5 = 1; if(_SetMacro & 0x0200) LATFbits.LATF4 = 1; if(_SetMacro & 0x0400) LATBbits.LATB13 = 1; if(_SetMacro & 0x0800) LATBbits.LATB12 = 1; if(_SetMacro & 0x1000) LATBbits.LATB11 = 1; if(_SetMacro & 0x2000) LATBbits.LATB10 = 1; if(_SetMacro & 0x4000) LATDbits.LATD11 = 1;}while(0) |
||
| 2505 | %ENC100_COMMENTS% #define ENC100_SET_AD_TRIS_IN() (((volatile BYTE*)&TRISE)[0] = 0xFF) |
||
| 2506 | %ENC100_COMMENTS% #define ENC100_SET_AD_TRIS_OUT() (((volatile BYTE*)&TRISE)[0] = 0x00) |
||
| 2507 | %ENC100_COMMENTS% #define ENC100_GET_AD_IO() (((volatile BYTE*)&PORTE)[0]) |
||
| 2508 | %ENC100_COMMENTS% #define ENC100_SET_AD_IO(data) (((volatile BYTE*)&LATE)[0] = (BYTE)(data)) |
||
| 2509 | %ENC100_COMMENTS% #endif |
||
| 2510 | %ENC100_COMMENTS% #elif ENC100_INTERFACE_MODE == 3 || ENC100_INTERFACE_MODE == 4 // Dumultiplexed 16-bit address/data modes |
||
| 2511 | %ENC100_COMMENTS% #if defined(ENC100_PSP_USE_INDIRECT_RAM_ADDRESSING) // Only ENC624J600 address pins A0-A7 connected (A8-A13 tied to Vdd) |
||
| 2512 | %ENC100_COMMENTS% // A0: "PMA0" -> RB15 |
||
| 2513 | %ENC100_COMMENTS% // A1: "PMA1" -> RB14 |
||
| 2514 | %ENC100_COMMENTS% // A2: "PMA2" -> RG9 |
||
| 2515 | %ENC100_COMMENTS% // A3: "PMA3" -> RA4 |
||
| 2516 | %ENC100_COMMENTS% // A4: "PMA4" -> RA3 |
||
| 2517 | %ENC100_COMMENTS% // A5: "PMA5" -> RF12 |
||
| 2518 | %ENC100_COMMENTS% // A6: "PMA6" -> RA10 |
||
| 2519 | %ENC100_COMMENTS% // A7: "PMA7" -> RA9 |
||
| 2520 | %ENC100_COMMENTS% // AD0-AD7: "PMD0-PMD7" -> RE0-RE7 |
||
| 2521 | %ENC100_COMMENTS% // AD8: "PMD8" -> RG0 |
||
| 2522 | %ENC100_COMMENTS% // AD9: "PMD9" -> RG1 |
||
| 2523 | %ENC100_COMMENTS% // AD10: "RC13_PMD10_TO_P30" "RC13" -> RC13 |
||
| 2524 | %ENC100_COMMENTS% // AD11: "PMBE1_PMD11_TO_P28" "PMBE1" -> RA15 |
||
| 2525 | %ENC100_COMMENTS% // AD12: "PMD12" -> RD12 |
||
| 2526 | %ENC100_COMMENTS% // AD13: "PMD13" -> RD13 |
||
| 2527 | %ENC100_COMMENTS% // AD14: "PMD14" -> RD6 |
||
| 2528 | %ENC100_COMMENTS% // AD15: "PMD15" -> RD7 |
||
| 2529 | %ENC100_COMMENTS% // RD: "PMRD/RD5" -> RD5 |
||
| 2530 | %ENC100_COMMENTS% // WRL & WRH: "PMWR/RD4 -> RD4 |
||
| 2531 | %ENC100_COMMENTS% // CS: "AN19/RG8_TO_P72" "AN19/RG8" -> RG8 |
||
| 2532 | %ENC100_COMMENTS% #define ENC100_INIT_PSP_BIT_BANG() do{ANSA &= 0x79E7; ANSB &= 0x3FFF; ANSD &= 0xCF0F; ANSG &= 0xFCFC;}while(0) |
||
| 2533 | %ENC100_COMMENTS% #define ENC100_SET_ADDR_TRIS_OUT() do{TRISA &= 0xF9E7; TRISBbits.TRISB15 = 0; TRISBbits.TRISB14 = 0; TRISFbits.TRISF12 = 0; TRISGbits.TRISG9 = 0;}while(0) |
||
| 2534 | %ENC100_COMMENTS% #define ENC100_SET_ADDR_IO(a) do{WORD _wSetMacro = (a); LATA &= 0xF9E7; LATBbits.LATB15 = 0; LATBbits.LATB14 = 0; LATFbits.LATF12 = 0; LATGbits.LATG9 = 0; if(_wSetMacro & 0x0001) LATBbits.LATB15 = 1; if(_wSetMacro & 0x0002) LATBbits.LATB14 = 1; if(_wSetMacro & 0x0004) LATGbits.LATG9 = 1; if(_wSetMacro & 0x0008) LATAbits.LATA4 = 1; if(_wSetMacro & 0x0010) LATAbits.LATA3 = 1; if(_wSetMacro & 0x0020) LATFbits.LATF12 = 1; if(_wSetMacro & 0x0040) LATAbits.LATA10 = 1; if(_wSetMacro & 0x0080) LATAbits.LATA9 = 1;}while(0) |
||
| 2535 | %ENC100_COMMENTS% #define ENC100_WRH_B1SEL_TRIS ENC100_SO_WR_B0SEL_EN_TRIS |
||
| 2536 | %ENC100_COMMENTS% #define ENC100_WRH_B1SEL_IO ENC100_SO_WR_B0SEL_EN_IO |
||
| 2537 | %ENC100_COMMENTS% #define ENC100_SET_AD_TRIS_IN() do{((volatile BYTE*)&TRISE)[0] = 0xFF; TRISAbits.TRISA15 = 1; TRISCbits.TRISC13 = 1; TRISD |= 0x30C0; TRISGbits.TRISG0 = 1; TRISGbits.TRISG1 = 1;}while(0) |
||
| 2538 | %ENC100_COMMENTS% #define ENC100_SET_AD_TRIS_OUT() do{((volatile BYTE*)&TRISE)[0] = 0x00; TRISAbits.TRISA15 = 0; TRISCbits.TRISC13 = 0; TRISD &= 0xCF3F; TRISGbits.TRISG0 = 0; TRISGbits.TRISG1 = 0;}while(0) |
||
| 2539 | %ENC100_COMMENTS% #define ENC100_GET_AD_IOH() (PORTGbits.RG0 | (PORTGbits.RG1<<1) | (PORTCbits.RC13<<2) | (PORTAbits.RA15<<3) | (PORTDbits.RD12<<4) | (PORTDbits.RD13<<5) | (PORTDbits.RD6<<6) | (PORTDbits.RD7<<7)) |
||
| 2540 | %ENC100_COMMENTS% #define ENC100_GET_AD_IOL() (((volatile BYTE*)&PORTE)[0]) |
||
| 2541 | %ENC100_COMMENTS% #define ENC100_SET_AD_IO(data) do{WORD _wSetMacro = (data); ((volatile BYTE*)&LATE)[0] = ((BYTE*)&_wSetMacro)[0]; LATG &= 0xFFFC; LATCbits.LATC13 = 0; LATAbits.LATA15 = 0; LATD &= 0xCF3F; if(_wSetMacro & 0x0100) LATGbits.LATG0 = 1; if(_wSetMacro & 0x0200) LATGbits.LATG1 = 1; if(_wSetMacro & 0x0400) LATCbits.LATC13 = 1; if(_wSetMacro & 0x0800) LATAbits.LATA15 = 1; if(_wSetMacro & 0x1000) LATDbits.LATD12 = 1; if(_wSetMacro & 0x2000) LATDbits.LATD13 = 1; if(_wSetMacro & 0x4000) LATDbits.LATD6 = 1; if(_wSetMacro & 0x8000) LATDbits.LATD7 = 1;}while(0) |
||
| 2542 | %ENC100_COMMENTS% #define ENC100_SET_AD_IOL(data) (((volatile BYTE*)&LATE)[0] = (BYTE)(data)) |
||
| 2543 | %ENC100_COMMENTS% #else // All ENC624J600 address pins A0-A13 connected |
||
| 2544 | %ENC100_COMMENTS% // A0: "PMA0" -> RB15 |
||
| 2545 | %ENC100_COMMENTS% // A1: "PMA1" -> RB14 |
||
| 2546 | %ENC100_COMMENTS% // A2: "PMA2" -> RG9 |
||
| 2547 | %ENC100_COMMENTS% // A3: "PMA3" -> RA4 |
||
| 2548 | %ENC100_COMMENTS% // A4: "PMA4" -> RA3 |
||
| 2549 | %ENC100_COMMENTS% // A5: "PMA5" -> RF12 |
||
| 2550 | %ENC100_COMMENTS% // A6: "PMA6" -> RA10 |
||
| 2551 | %ENC100_COMMENTS% // A7: "PMA7" -> RA9 |
||
| 2552 | %ENC100_COMMENTS% // A8: "PMA8" -> RF5 |
||
| 2553 | %ENC100_COMMENTS% // A9: "PMA9" -> RF4 |
||
| 2554 | %ENC100_COMMENTS% // A10: "PMA10" -> RB13 |
||
| 2555 | %ENC100_COMMENTS% // A11: "PMA11" -> RB12 |
||
| 2556 | %ENC100_COMMENTS% // A12: "PMA12" -> RB11 |
||
| 2557 | %ENC100_COMMENTS% // A13: "PMA13" -> RB10 |
||
| 2558 | %ENC100_COMMENTS% // AD0-AD7: "PMD0-PMD7" -> RE0-RE7 |
||
| 2559 | %ENC100_COMMENTS% // AD8: "PMD8" -> RG0 |
||
| 2560 | %ENC100_COMMENTS% // AD9: "PMD9" -> RG1 |
||
| 2561 | %ENC100_COMMENTS% // AD10: "RC13_PMD10_TO_P30" "RC13" -> RC13 |
||
| 2562 | %ENC100_COMMENTS% // AD11: "PMBE1_PMD11_TO_P28" "PMBE1" -> RA15 |
||
| 2563 | %ENC100_COMMENTS% // AD12: "PMD12" -> RD12 |
||
| 2564 | %ENC100_COMMENTS% // AD13: "PMD13" -> RD13 |
||
| 2565 | %ENC100_COMMENTS% // AD14: "PMD14" -> RD6 |
||
| 2566 | %ENC100_COMMENTS% // AD15: "PMD15" -> RD7 |
||
| 2567 | %ENC100_COMMENTS% // RD: "PMRD/RD5" -> RD5 |
||
| 2568 | %ENC100_COMMENTS% // WRL & WRH: "PMWR/RD4 -> RD4 |
||
| 2569 | %ENC100_COMMENTS% // CS: "AN19/RG8_TO_P72" "AN19/RG8" -> RG8 |
||
| 2570 | %ENC100_COMMENTS% #define ENC100_INIT_PSP_BIT_BANG() do{ANSA &= 0x79E7; ANSB &= 0x03FF; ANSD &= 0xCF0F; ANSG &= 0xFCFC;}while(0) |
||
| 2571 | %ENC100_COMMENTS% #define ENC100_SET_ADDR_TRIS_OUT() do{TRISA &= 0xF9E7; TRISB &= 0x03FF; TRISF &= 0xEFCF; TRISGbits.TRISG9 = 0;}while(0) |
||
| 2572 | %ENC100_COMMENTS% #define ENC100_SET_ADDR_IO(a) do{WORD _wSetMacro = (a); LATA &= 0xF9E7; LATB &= 0x03FF; LATF &= 0xEFCF; LATGbits.LATG9 = 0; if(_wSetMacro & 0x0001) LATBbits.LATB15 = 1; if(_wSetMacro & 0x0002) LATBbits.LATB14 = 1; if(_wSetMacro & 0x0004) LATGbits.LATG9 = 1; if(_wSetMacro & 0x0008) LATAbits.LATA4 = 1; if(_wSetMacro & 0x0010) LATAbits.LATA3 = 1; if(_wSetMacro & 0x0020) LATFbits.LATF12 = 1; if(_wSetMacro & 0x0040) LATAbits.LATA10 = 1; if(_wSetMacro & 0x0080) LATAbits.LATA9 = 1; if(_wSetMacro & 0x0100) LATFbits.LATF5 = 1; if(_wSetMacro & 0x0200) LATFbits.LATF4 = 1; if(_wSetMacro & 0x0400) LATBbits.LATB13 = 1; if(_wSetMacro & 0x0800) LATBbits.LATB12 = 1; if(_wSetMacro & 0x1000) LATBbits.LATB11 = 1; if(_wSetMacro & 0x2000) LATBbits.LATB10 = 1;}while(0) |
||
| 2573 | %ENC100_COMMENTS% #define ENC100_WRH_B1SEL_TRIS ENC100_SO_WR_B0SEL_EN_TRIS |
||
| 2574 | %ENC100_COMMENTS% #define ENC100_WRH_B1SEL_IO ENC100_SO_WR_B0SEL_EN_IO |
||
| 2575 | %ENC100_COMMENTS% #define ENC100_SET_AD_TRIS_IN() do{((volatile BYTE*)&TRISE)[0] = 0xFF; TRISAbits.TRISA15 = 1; TRISCbits.TRISC13 = 1; TRISD |= 0x30C0; TRISGbits.TRISG0 = 1; TRISGbits.TRISG1 = 1;}while(0) |
||
| 2576 | %ENC100_COMMENTS% #define ENC100_SET_AD_TRIS_OUT() do{((volatile BYTE*)&TRISE)[0] = 0x00; TRISAbits.TRISA15 = 0; TRISCbits.TRISC13 = 0; TRISD &= 0xCF3F; TRISGbits.TRISG0 = 0; TRISGbits.TRISG1 = 0;}while(0) |
||
| 2577 | %ENC100_COMMENTS% #define ENC100_GET_AD_IOH() (PORTGbits.RG0 | (PORTGbits.RG1<<1) | (PORTCbits.RC13<<2) | (PORTAbits.RA15<<3) | (PORTDbits.RD12<<4) | (PORTDbits.RD13<<5) | (PORTDbits.RD6<<6) | (PORTDbits.RD7<<7)) |
||
| 2578 | %ENC100_COMMENTS% #define ENC100_GET_AD_IOL() (((volatile BYTE*)&PORTE)[0]) |
||
| 2579 | %ENC100_COMMENTS% #define ENC100_SET_AD_IO(data) do{WORD _wSetMacro = (data); ((volatile BYTE*)&LATE)[0] = ((BYTE*)&_wSetMacro)[0]; LATG &= 0xFFFC; LATCbits.LATC13 = 0; LATAbits.LATA15 = 0; LATD &= 0xCF3F; if(_wSetMacro & 0x0100) LATGbits.LATG0 = 1; if(_wSetMacro & 0x0200) LATGbits.LATG1 = 1; if(_wSetMacro & 0x0400) LATCbits.LATC13 = 1; if(_wSetMacro & 0x0800) LATAbits.LATA15 = 1; if(_wSetMacro & 0x1000) LATDbits.LATD12 = 1; if(_wSetMacro & 0x2000) LATDbits.LATD13 = 1; if(_wSetMacro & 0x4000) LATDbits.LATD6 = 1; if(_wSetMacro & 0x8000) LATDbits.LATD7 = 1;}while(0) |
||
| 2580 | %ENC100_COMMENTS% #define ENC100_SET_AD_IOL(data) (((volatile BYTE*)&LATE)[0] = (BYTE)(data)) |
||
| 2581 | %ENC100_COMMENTS% #endif |
||
| 2582 | %ENC100_COMMENTS% #elif ENC100_INTERFACE_MODE == 5 || ENC100_INTERFACE_MODE == 6 // Mutliplexed 8-bit address/data modes |
||
| 2583 | %ENC100_COMMENTS% #if defined(ENC100_PSP_USE_INDIRECT_RAM_ADDRESSING) // Only ENCX24J600 address pins AD0-AD8 connected (AD9-AD14 tied to Vdd) |
||
| 2584 | %ENC100_COMMENTS% #define ENC100_INIT_PSP_BIT_BANG() do{ANSB &= 0x7FFF; ANSG &= 0xFEFF;} while(0) // RE0-RE7, RD11, RD4, RD5 (AD0-AD7, AD8, WR, RD) pins are already digital only pins. RB15, RG8 (AL, CS) needs to be made digital only. |
||
| 2585 | %ENC100_COMMENTS% #define ENC100_SET_AD_TRIS_IN() do{((volatile BYTE*)&TRISE)[0] = 0xFF;}while(0) |
||
| 2586 | %ENC100_COMMENTS% #define ENC100_SET_AD_TRIS_OUT() do{((volatile BYTE*)&TRISE)[0] = 0x00; TRISDbits.TRISD11 = 0;}while(0) |
||
| 2587 | %ENC100_COMMENTS% #define ENC100_GET_AD_IO() (((volatile BYTE*)&PORTE)[0]) |
||
| 2588 | %ENC100_COMMENTS% #define ENC100_SET_AD_IO(data) do{WORD _wSetMacro = (data); ((volatile BYTE*)&LATE)[0] = (BYTE)_wSetMacro; LATDbits.LATD11 = 0; if(_wSetMacro & 0x4000) LATDbits.LATD11 = 1;}while(0) |
||
| 2589 | %ENC100_COMMENTS% #define ENC100_SET_AD_IOL(data) (((volatile BYTE*)&LATE)[0] = (BYTE)(data)) |
||
| 2590 | %ENC100_COMMENTS% #else // All ENCX24J600 address pins AD0-AD14 connected |
||
| 2591 | %ENC100_COMMENTS% // AD0-AD7: "PMD0-PMD7" -> RE0-RE7 |
||
| 2592 | %ENC100_COMMENTS% // AD8: "PMA8" -> RF5 |
||
| 2593 | %ENC100_COMMENTS% // AD9: "PMA9" -> RF4 |
||
| 2594 | %ENC100_COMMENTS% // AD10: "PMA10" -> RB13 |
||
| 2595 | %ENC100_COMMENTS% // AD11: "PMA11" -> RB12 |
||
| 2596 | %ENC100_COMMENTS% // AD12: "PMA12" -> RB11 |
||
| 2597 | %ENC100_COMMENTS% // AD13: "PMA13" -> RB10 |
||
| 2598 | %ENC100_COMMENTS% // AD14: "PMA14_TO_P104" "PMA14" -> RD11 |
||
| 2599 | %ENC100_COMMENTS% // RD: "PMRD/RD5" -> RD5 |
||
| 2600 | %ENC100_COMMENTS% // WR: "PMWR/RD4 -> RD4 |
||
| 2601 | %ENC100_COMMENTS% // AL: "PMA0" -> RB15 |
||
| 2602 | %ENC100_COMMENTS% // CS: "AN19/RG8_TO_P72" "AN19/RG8" -> RG8 |
||
| 2603 | %ENC100_COMMENTS% #define ENC100_INIT_PSP_BIT_BANG() do{ANSB &= 0x43FF; ANSG &= 0xFEFF;} while(0) // Set pins as digital I/Os (not analog). RD11, RD5, RD4, RE0-RE7, RF4, RF5 are all digital-only pins and therefore no writes to ANSD, ANSE, or ANSF are needed. |
||
| 2604 | %ENC100_COMMENTS% #define ENC100_SET_AD_TRIS_IN() do{((volatile BYTE*)&TRISE)[0] = 0xFF;}while(0) |
||
| 2605 | %ENC100_COMMENTS% #define ENC100_SET_AD_TRIS_OUT() do{((volatile BYTE*)&TRISE)[0] = 0x00; TRISFbits.TRISF5 = 0; TRISFbits.TRISF4 = 0; TRISB &= 0x43FF; TRISDbits.TRISD11 = 0;}while(0) |
||
| 2606 | %ENC100_COMMENTS% #define ENC100_GET_AD_IO() (((volatile BYTE*)&PORTE)[0]) |
||
| 2607 | %ENC100_COMMENTS% #define ENC100_SET_AD_IO(data) do{WORD _wSetMacro = (data); ((volatile BYTE*)&LATE)[0] = (BYTE)_wSetMacro; LATFbits.LATF5 = 0; LATFbits.LATF4 = 0; LATB &= 0x43FF; LATDbits.LATD11 = 0; if(_wSetMacro & 0x0100) LATFbits.LATF5 = 1; if(_wSetMacro & 0x0200) LATFbits.LATF4 = 1; if(_wSetMacro & 0x0400) LATBbits.LATB13 = 1; if(_wSetMacro & 0x0800) LATBbits.LATB12 = 1; if(_wSetMacro & 0x1000) LATBbits.LATB11 = 1; if(_wSetMacro & 0x2000) LATBbits.LATB10 = 1; if(_wSetMacro & 0x4000) LATDbits.LATD11 = 1;}while(0) |
||
| 2608 | %ENC100_COMMENTS% #define ENC100_SET_AD_IOL(data) (((volatile BYTE*)&LATE)[0] = (BYTE)(data)) |
||
| 2609 | %ENC100_COMMENTS% #endif |
||
| 2610 | %ENC100_COMMENTS% #elif ENC100_INTERFACE_MODE == 9 || ENC100_INTERFACE_MODE == 10 // Mutliplexed 16-bit address/data modes |
||
| 2611 | %ENC100_COMMENTS% // All ENC624J600 adddress/data pins AD0-AD15 connected (required for 16-bit data, so there is no differentiation for indirect versus direct addressing mode) |
||
| 2612 | %ENC100_COMMENTS% // This pinout is awful for doing 16-bit bit-bang operations. The Fast 100Mbps Ethernet PICtail Plus hardware is wired for PMP hardware support, which requires this pinout. However, if you are designing a custom board, you can simplify these read/write operations dramatically if you wire things more logically by putting all 16 I/O pins, in order, on PORTB or PORTD. Such a change would enhance performance. |
||
| 2613 | %ENC100_COMMENTS% // AD0-AD7: "PMD0-PMD7" -> RE0-RE7 |
||
| 2614 | %ENC100_COMMENTS% // AD8: "PMD8" -> RG0 |
||
| 2615 | %ENC100_COMMENTS% // AD9: "PMD9" -> RG1 |
||
| 2616 | %ENC100_COMMENTS% // AD10: "RC13_PMD10_TO_P30" "RC13" -> RC13 |
||
| 2617 | %ENC100_COMMENTS% // AD11: "PMBE1_PMD11_TO_P28" "PMBE1" -> RA15 |
||
| 2618 | %ENC100_COMMENTS% // AD12: "PMD12" -> RD12 |
||
| 2619 | %ENC100_COMMENTS% // AD13: "PMD13" -> RD13 |
||
| 2620 | %ENC100_COMMENTS% // AD14: "PMD14" -> RD6 |
||
| 2621 | %ENC100_COMMENTS% // AD15: "PMD15" -> RD7 |
||
| 2622 | %ENC100_COMMENTS% // RD: "PMRD/RD5" -> RD5 |
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| 2623 | %ENC100_COMMENTS% // WRL & WRH: "PMWR/RD4 -> RD4 |
||
| 2624 | %ENC100_COMMENTS% // AL: "PMA0" -> RB15 |
||
| 2625 | %ENC100_COMMENTS% // CS: "AN19/RG8_TO_P72" "AN19/RG8" -> RG8 |
||
| 2626 | %ENC100_COMMENTS% #define ENC100_INIT_PSP_BIT_BANG() do{ANSBbits.ANSB15 = 0; ANSCbits.ANSC13 = 0; ANSD &= 0xCF0F; ANSGbits.ANSG8 = 0;}while(0) // Set pins as digital I/Os (not analog). RA15 and RE0-RE7 are all digital-only pins and therefore no writes to ANSA or ANSE are needed. |
||
| 2627 | %ENC100_COMMENTS% #define ENC100_WRH_B1SEL_TRIS ENC100_SO_WR_B0SEL_EN_TRIS |
||
| 2628 | %ENC100_COMMENTS% #define ENC100_WRH_B1SEL_IO ENC100_SO_WR_B0SEL_EN_IO |
||
| 2629 | %ENC100_COMMENTS% #define ENC100_SET_AD_TRIS_IN() do{((volatile BYTE*)&TRISE)[0] = 0xFF; TRISAbits.TRISA15 = 1; TRISCbits.TRISC13 = 1; TRISD |= 0x30C0; TRISGbits.TRISG0 = 1; TRISGbits.TRISG1 = 1;}while(0) |
||
| 2630 | %ENC100_COMMENTS% #define ENC100_SET_AD_TRIS_OUT() do{((volatile BYTE*)&TRISE)[0] = 0x00; TRISAbits.TRISA15 = 0; TRISCbits.TRISC13 = 0; TRISD &= 0xCF3F; TRISGbits.TRISG0 = 0; TRISGbits.TRISG1 = 0;}while(0) |
||
| 2631 | %ENC100_COMMENTS% #define ENC100_GET_AD_IOH() (PORTGbits.RG0 | (PORTGbits.RG1<<1) | (PORTCbits.RC13<<2) | (PORTAbits.RA15<<3) | (PORTDbits.RD12<<4) | (PORTDbits.RD13<<5) | (PORTDbits.RD6<<6) | (PORTDbits.RD7<<7)) |
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| 2632 | %ENC100_COMMENTS% #define ENC100_GET_AD_IOL() (((volatile BYTE*)&PORTE)[0]) |
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| 2633 | %ENC100_COMMENTS% #define ENC100_SET_AD_IO(data) do{WORD _wSetMacro = (data); ((volatile BYTE*)&LATE)[0] = ((BYTE*)&_wSetMacro)[0]; LATG &= 0xFFFC; LATCbits.LATC13 = 0; LATAbits.LATA15 = 0; LATD &= 0xCF3F; if(_wSetMacro & 0x0100) LATGbits.LATG0 = 1; if(_wSetMacro & 0x0200) LATGbits.LATG1 = 1; if(_wSetMacro & 0x0400) LATCbits.LATC13 = 1; if(_wSetMacro & 0x0800) LATAbits.LATA15 = 1; if(_wSetMacro & 0x1000) LATDbits.LATD12 = 1; if(_wSetMacro & 0x2000) LATDbits.LATD13 = 1; if(_wSetMacro & 0x4000) LATDbits.LATD6 = 1; if(_wSetMacro & 0x8000) LATDbits.LATD7 = 1;}while(0) |
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| 2634 | %ENC100_COMMENTS% #define ENC100_SET_AD_IOL(data) (((volatile BYTE*)&LATE)[0] = (BYTE)(data)) |
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| 2635 | %ENC100_COMMENTS% #endif |
||
| 2636 | %ENC100_COMMENTS% #endif |
||
| 2637 | |||
| 2638 | |||
| 2639 | %MRF24WB0M_COMMENTS% //---------------------------- |
||
| 2640 | %MRF24WB0M_COMMENTS% // MRF24WB0M WiFi I/O pins |
||
| 2641 | %MRF24WB0M_COMMENTS% //---------------------------- |
||
| 2642 | %MRF24WB0M_COMMENTS% #define WF_CS_TRIS (TRISGbits.TRISG8) // Comment this line out if you are using the ENC28J60, ENC424J600/624J600, or other network controller. |
||
| 2643 | %MRF24WB0M_COMMENTS% #define WF_CS_IO (LATGbits.LATG8) |
||
| 2644 | %MRF24WB0M_COMMENTS% #define WF_SDI_TRIS (TRISBbits.TRISB1) |
||
| 2645 | %MRF24WB0M_COMMENTS% #define WF_SCK_TRIS (TRISDbits.TRISD8) |
||
| 2646 | %MRF24WB0M_COMMENTS% #define WF_SDO_TRIS (TRISBbits.TRISB0) |
||
| 2647 | %MRF24WB0M_COMMENTS% #define WF_RESET_TRIS (TRISAbits.TRISA15) |
||
| 2648 | %MRF24WB0M_COMMENTS% #define WF_RESET_IO (LATAbits.LATA15) |
||
| 2649 | %MRF24WB0M_COMMENTS% #define WF_INT_TRIS (TRISEbits.TRISE9) // INT1 |
||
| 2650 | %MRF24WB0M_COMMENTS% #define WF_INT_IO (PORTEbits.RE9) |
||
| 2651 | %MRF24WB0M_COMMENTS% #define WF_HIBERNATE_TRIS (TRISAbits.TRISA7) |
||
| 2652 | %MRF24WB0M_COMMENTS% #define WF_HIBERNATE_IO (LATAbits.LATA7) |
||
| 2653 | %MRF24WB0M_COMMENTS% #define WF_INT_EDGE (INTCON2bits.INT1EP) |
||
| 2654 | %MRF24WB0M_COMMENTS% #define WF_INT_IE (IEC1bits.INT1IE) |
||
| 2655 | %MRF24WB0M_COMMENTS% #define WF_INT_IF (IFS1bits.INT1IF) |
||
| 2656 | %MRF24WB0M_COMMENTS% #define WF_SSPBUF (SPI1BUF) |
||
| 2657 | %MRF24WB0M_COMMENTS% #define WF_SPISTAT (SPI1STAT) |
||
| 2658 | %MRF24WB0M_COMMENTS% #define WF_SPISTATbits (SPI1STATbits) |
||
| 2659 | %MRF24WB0M_COMMENTS% #define WF_SPICON1 (SPI1CON1) |
||
| 2660 | %MRF24WB0M_COMMENTS% #define WF_SPICON1bits (SPI1CON1bits) |
||
| 2661 | %MRF24WB0M_COMMENTS% #define WF_SPICON2 (SPI1CON2) |
||
| 2662 | %MRF24WB0M_COMMENTS% #define WF_SPI_IE (IEC0bits.SPI1IE) |
||
| 2663 | %MRF24WB0M_COMMENTS% //#define WF_SPI_IP (IPC2bits.SPI1IP) |
||
| 2664 | %MRF24WB0M_COMMENTS% #define WF_SPI_IF (IFS0bits.SPI1IF) |
||
| 2665 | |||
| 2666 | |||
| 2667 | #elif defined(YOUR_BOARD) |
||
| 2668 | // Define your own board hardware profile here |
||
| 2669 | |||
| 2670 | #else |
||
| 2671 | #error "Hardware profile not defined. See available profiles in HardwareProfile.h and modify or create one." |
||
| 2672 | #endif |
||
| 2673 | |||
| 2674 | |||
| 2675 | #if defined(__18CXX) // PIC18 |
||
| 2676 | // UART mapping functions for consistent API names across 8-bit and 16 or |
||
| 2677 | // 32 bit compilers. For simplicity, everything will use "UART" instead |
||
| 2678 | // of USART/EUSART/etc. |
||
| 2679 | #define BusyUART() BusyUSART() |
||
| 2680 | #define CloseUART() CloseUSART() |
||
| 2681 | #define ConfigIntUART(a) ConfigIntUSART(a) |
||
| 2682 | #define DataRdyUART() DataRdyUSART() |
||
| 2683 | #define OpenUART(a,b,c) OpenUSART(a,b,c) |
||
| 2684 | #define ReadUART() ReadUSART() |
||
| 2685 | #define WriteUART(a) WriteUSART(a) |
||
| 2686 | #define getsUART(a,b,c) getsUSART(b,a) |
||
| 2687 | #define putsUART(a) putsUSART(a) |
||
| 2688 | #define getcUART() ReadUSART() |
||
| 2689 | #define putcUART(a) WriteUSART(a) |
||
| 2690 | #define putrsUART(a) putrsUSART((far rom char*)a) |
||
| 2691 | |||
| 2692 | #else // PIC24F, PIC24H, dsPIC30, dsPIC33, PIC32 |
||
| 2693 | // Some A/D converter registers on dsPIC30s are named slightly differently |
||
| 2694 | // on other procesors, so we need to rename them. |
||
| 2695 | #if defined(__dsPIC30F__) |
||
| 2696 | #define ADC1BUF0 ADCBUF0 |
||
| 2697 | #define AD1CHS ADCHS |
||
| 2698 | #define AD1CON1 ADCON1 |
||
| 2699 | #define AD1CON2 ADCON2 |
||
| 2700 | #define AD1CON3 ADCON3 |
||
| 2701 | #define AD1PCFGbits ADPCFGbits |
||
| 2702 | #define AD1CSSL ADCSSL |
||
| 2703 | #define AD1IF ADIF |
||
| 2704 | #define AD1IE ADIE |
||
| 2705 | #define _ADC1Interrupt _ADCInterrupt |
||
| 2706 | #endif |
||
| 2707 | |||
| 2708 | // Select which UART the STACK_USE_UART and STACK_USE_UART2TCP_BRIDGE |
||
| 2709 | // options will use. You can change these to U1BRG, U1MODE, etc. if you |
||
| 2710 | // want to use the UART1 module instead of UART2. |
||
| 2711 | #define UBRG U2BRG |
||
| 2712 | #define UMODE U2MODE |
||
| 2713 | #define USTA U2STA |
||
| 2714 | #define BusyUART() BusyUART2() |
||
| 2715 | #define CloseUART() CloseUART2() |
||
| 2716 | #define ConfigIntUART(a) ConfigIntUART2(a) |
||
| 2717 | #define DataRdyUART() DataRdyUART2() |
||
| 2718 | #define OpenUART(a,b,c) OpenUART2(a,b,c) |
||
| 2719 | #define ReadUART() ReadUART2() |
||
| 2720 | #define WriteUART(a) WriteUART2(a) |
||
| 2721 | #define getsUART(a,b,c) getsUART2(a,b,c) |
||
| 2722 | #if defined(__C32__) |
||
| 2723 | #define putsUART(a) putsUART2(a) |
||
| 2724 | #else |
||
| 2725 | #define putsUART(a) putsUART2((unsigned int*)a) |
||
| 2726 | #endif |
||
| 2727 | #define getcUART() getcUART2() |
||
| 2728 | #define putcUART(a) do{while(BusyUART()); WriteUART(a); while(BusyUART()); }while(0) |
||
| 2729 | #define putrsUART(a) putrsUART2(a) |
||
| 2730 | #endif |
||
| 2731 | |||
| 2732 | |||
| 2733 | #endif |
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