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library

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Blame information for rev 32

Line No. Rev Author Line
1 32 kaklik /******************************************************************************
2  
3 MRF24WB0M Driver Internal use
4 Module for Microchip TCP/IP Stack
5 -Provides access to MRF24WB0M WiFi controller
6 -Reference: MRF24WB0M Data sheet, IEEE 802.11 Standard
7  
8 *******************************************************************************
9 FileName: WFDriverPrv.h
10 Dependencies: TCP/IP Stack header files
11 Processor: PIC18, PIC24F, PIC24H, dsPIC30F, dsPIC33F, PIC32
12 Compiler: Microchip C32 v1.10b or higher
13 Microchip C30 v3.22 or higher
14 Microchip C18 v3.34 or higher
15 Company: Microchip Technology, Inc.
16  
17 Software License Agreement
18  
19 Copyright (C) 2002-2010 Microchip Technology Inc. All rights reserved.
20  
21 Microchip licenses to you the right to use, modify, copy, and distribute:
22 (i) the Software when embedded on a Microchip microcontroller or digital
23 signal controller product ("Device") which is integrated into
24 Licensee's product; or
25 (ii) ONLY the Software driver source files ENC28J60.c, ENC28J60.h,
26 ENCX24J600.c and ENCX24J600.h ported to a non-Microchip device used in
27 conjunction with a Microchip ethernet controller for the sole purpose
28 of interfacing with the ethernet controller.
29  
30 You should refer to the license agreement accompanying this Software for
31 additional information regarding your rights and obligations.
32  
33 THE SOFTWARE AND DOCUMENTATION ARE PROVIDED "AS IS" WITHOUT WARRANTY OF ANY
34 KIND, EITHER EXPRESS OR IMPLIED, INCLUDING WITHOUT LIMITATION, ANY WARRANTY
35 OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE AND
36 NON-INFRINGEMENT. IN NO EVENT SHALL MICROCHIP BE LIABLE FOR ANY INCIDENTAL,
37 SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES, LOST PROFITS OR LOST DATA, COST
38 OF PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS BY
39 THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF), ANY CLAIMS
40 FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS, WHETHER ASSERTED ON
41 THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE), BREACH OF WARRANTY, OR
42 OTHERWISE.
43  
44  
45 Author Date Comment
46 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
47 KO 31 Oct 2008 Port to PIC24F and PIC32 for TCP/IP stack v4.52
48 KH 27 Jan 2010 Updated for MRF24WB0M
49 ******************************************************************************/
50  
51 #ifndef _WFDRIVERPRV_H_
52 #define _WFDRIVERPRV_H_
53  
54 /*
55 *********************************************************************************************************
56 * DEFINES
57 *********************************************************************************************************
58 */
59  
60 /*--------------------*/
61 /* Endianness defines */
62 /*--------------------*/
63 #define WF_BIG_ENDIAN (0)
64 #define WF_LITTLE_ENDIAN (1)
65  
66 /* Indicate whether the Host CPU is big-endian or little-endian */
67 #define HOST_CPU_ENDIANNESS WF_LITTLE_ENDIAN /* WF_BIG_ENDIAN or WF_LITTLE_ENDIAN */
68  
69  
70 /*-------------------*/
71 /* Endianness Macros */
72 /*-------------------*/
73 /* if the Host CPU is Little Endian, which does not match the MRF24WB0M */
74 #if (HOST_CPU_ENDIANNESS == WF_LITTLE_ENDIAN)
75  
76 /* 32-bit data type conversion */
77 #define HTOWFL(a) (((a & 0x000000ff) << 24) | ((a & 0x0000ff00) << 8) | ((a & 0x00ff0000) >> 8) | ((a & 0xff000000) >> 24))
78 #define WFTOHL(a) HTOWFL(a)
79  
80 /* 16-bit data type conversion */
81 #define HSTOWFS(a) (((a) << 8) | ((a) >> 8))
82 #define WFSTOHS(a) HSTOWFS(a)
83  
84 /* else Host CPU is Big-Endian, which matches the MRF24WB0M */
85 #else
86 #define HTOWFL(a) (a)
87 #define WFTOHL(a) (a)
88 #define HSTOWFS(a) (a)
89 #define WFSTOHS(a) (a)
90 #endif
91  
92 /*------------*/
93 /* Endianness */
94 /*------------*/
95 /* ensure that endianness has been defined */
96 #if (HOST_CPU_ENDIANNESS != WF_LITTLE_ENDIAN) && (HOST_CPU_ENDIANNESS != WF_BIG_ENDIAN)
97 #error Must define HOST_CPU_ENDIANNESS to either WF_LITTLE_ENDIAN or WF_BIG_ENDIAN
98 #endif
99  
100  
101  
102 #define WF_SetCE_N(level) \
103 /* configure I/O as ouput */ \
104 WF_HIBERNATE_TRIS = 0; \
105 /* set pin to desired level */ \
106 WF_HIBERNATE_IO = level
107  
108 #define WF_SetRST_N(level) \
109 /* configure the I/O as an output */ \
110 WF_RESET_TRIS = 0; \
111 /* set pin to desired level */ \
112 WF_RESET_IO = level
113  
114  
115 /* SPI Tx Message Types */
116 #define WF_DATA_REQUEST_TYPE ((UINT8)1)
117 #define WF_MGMT_REQUEST_TYPE ((UINT8)2)
118  
119 /* SPI Rx Message Types */
120 #define WF_DATA_TX_CONFIRM_TYPE ((UINT8)1)
121 #define WF_MGMT_CONFIRM_TYPE ((UINT8)2)
122 #define WF_DATA_RX_INDICATE_TYPE ((UINT8)3)
123 #define WF_MGMT_INDICATE_TYPE ((UINT8)4)
124  
125 /* SPI Tx/Rx Data Message Subtypes */
126 #define WF_STD_DATA_MSG_SUBTYPE ((UINT8)1)
127 #define WF_NULL_DATA_MSG_SUBTYPE ((UINT8)2)
128 /* reserved value ((UINT8)3) */
129 #define WF_UNTAMPERED_DATA_MSG_SUBTYPE ((UINT8)4)
130  
131  
132 #define WF_TX_DATA_MSG_PREAMBLE_LENGTH ((UINT8)3)
133  
134 #define WF_READ_REGISTER_MASK ((UINT8)(0x40))
135 #define WF_WRITE_REGISTER_MASK ((UINT8)(0x00))
136  
137  
138 /*--------------------------------*/
139 /* MRF24WB0M 8-bit Host Registers */
140 /*--------------------------------*/
141 #define WF_HOST_INTR_REG ((UINT8)(0x01)) /* 8-bit register containing 1st level interrupt bits. */
142 #define WF_HOST_MASK_REG ((UINT8)(0x02)) /* 8-bit register containing 1st level interrupt mask. */
143  
144 /*---------------------------------*/
145 /* MRF24WB0M 16-bit Host Registers */
146 /*---------------------------------*/
147 #define WF_HOST_RAW0_CTRL1_REG ((UINT16)(0x26))
148 #define WF_HOST_RAW0_STATUS_REG ((UINT16)(0x28))
149 #define WF_HOST_RAW1_CTRL1_REG ((UINT16)(0x2a))
150 #define WF_HOST_INTR2_REG ((UINT16)(0x2d)) /* 16-bit register containing 2nd level interrupt bits */
151 #define WF_HOST_INTR2_MASK_REG ((UINT16)(0x2e))
152 #define WF_HOST_WFIFO_BCNT0_REG ((UINT16)(0x2f)) /* 16-bit register containing available write size for fifo 0 (data) */
153 /* (LS 12 bits contain the length) */
154  
155 #define WF_HOST_WFIFO_BCNT1_REG ((UINT16)(0x31)) /* 16-bit register containing available write size for fifo 1 (mgmt) */
156 /* (LS 12 bits contain the length) */
157  
158 #define WF_HOST_RFIFO_BCNT0_REG ((UINT16)(0x33)) /* 16-bit register containing number of bytes in read fifo 0 (data rx) */
159 /* (LS 12 bits contain the length) */
160  
161 #define WF_PSPOLL_H_REG ((UINT16)(0x3d)) /* 16-bit register used to control low power mode */
162 #define WF_INDEX_ADDR_REG ((UINT16)(0x3e)) /* 16-bit register to move the data window */
163 #define WF_INDEX_DATA_REG ((UINT16)(0x3f)) /* 16-bit register to read or write address-indexed register */
164  
165 /*----------------------------------------------------------------------------------------*/
166 /* MRF24WB0M registers accessed via the WF_INDEX_ADDR_REG and WF_INDEX_DATA_REG registers */
167 /*----------------------------------------------------------------------------------------*/
168 #define WF_HW_STATUS_REG ((UINT16)(0x2a)) /* 16-bit read only register providing hardware status bits */
169 #define WF_CONFIG_CTRL0_REG ((UINT16)(0x2e)) /* 16-bit register used to initiate Hard reset */
170 #define WF_LOW_POWER_STATUS_REG ((UINT16)(0x3e)) /* 16-bit register read to determine when low power is done */
171  
172 /* This bit mask is used in the HW_STATUS_REG to determine */
173 /* when the MRF24WB0M has completed its hardware reset. */
174 /* 0 : MRF24WB0M is in reset */
175 /* 1 : MRF24WB0M is not in reset */
176 #define WF_HW_STATUS_NOT_IN_RESET_MASK ((UINT16)(0x1000))
177  
178 /* Definitions represent individual interrupt bits for the 8-bit host interrupt registers */
179 /* WF_HOST_INTR_REG and WF_HOST_MASK_REG */
180 #define WF_HOST_INT_MASK_INT2 ((UINT8)(0x01))
181 #define WF_HOST_INT_MASK_FIFO_1_THRESHOLD ((UINT8)(0x80))
182 #define WF_HOST_INT_MASK_FIFO_0_THRESHOLD ((UINT8)(0x40))
183 #define WF_HOST_INT_MASK_RAW_1_INT_0 ((UINT8)(0x04))
184 #define WF_HOST_INT_MASK_RAW_0_INT_0 ((UINT8)(0x02))
185 #define WF_HOST_INT_MASK_ALL_INT ((UINT8)(0xff))
186  
187 /* Bit mask for all interrupts in the level 2 16-bit interrupt register */
188 #define WF_HOST_2_INT_MASK_ALL_INT ((UINT16)(0xffff))
189  
190 /* these definitions are used in calls to enable and
191 * disable interrupt bits. */
192 #define WF_INT_DISABLE ((UINT8)0)
193 #define WF_INT_ENABLE ((UINT8)1)
194  
195 #define WF_LOW_POWER_MODE_ON (1)
196 #define WF_LOW_POWER_MODE_OFF (0)
197  
198 #if defined(WF_USE_POWER_SAVE_FUNCTIONS)
199 void EnsureWFisAwake(void);
200 void WFConfigureLowPowerMode(UINT8 action);
201 BOOL WFisPsPollEnabled(void);
202 BOOL WFIsPsPollActive(void);
203 #else
204 #define EnsureWFisAwake()
205 #define WFConfigureLowPowerMode(action)
206 #endif
207  
208  
209  
210 #define WF_MAC_ADDRESS_LENGTH (6)
211  
212 /*
213 *********************************************************************************************************
214 * FUNCTION PROTOTYPES
215 *********************************************************************************************************
216 */
217  
218 /* tComContext - Used by the COM layer to manage State information */
219 typedef struct
220 {
221 volatile UINT8 rawInterrupt;
222 BOOL waitingForRawMoveCompleteInterrupt;
223 } tRawMoveState;
224  
225 extern tRawMoveState RawMoveState;
226  
227  
228 /*
229 *********************************************************************************************************
230 * FUNCTION PROTOTYPES
231 *********************************************************************************************************
232 */
233  
234 void WFHardwareInit(void);
235 UINT16 Read16BitWFRegister(UINT8 regId);
236 void Write16BitWFRegister(UINT8 regId, UINT16 value);
237 UINT8 Read8BitWFRegister(UINT8 regId);
238 void Write8BitWFRegister(UINT8 regId, UINT8 value);
239 void WriteWFArray(UINT8 regId, UINT8 *pBuf, UINT16 length);
240 void WriteWFROMArray(UINT8 regId, ROM UINT8 *pBuf, UINT16 length);
241 void ReadWFArray(UINT8 regId, UINT8 *pBuf, UINT16 length);
242  
243 BOOL WFisConnected(void);
244 void SetLogicalConnectionState(BOOL state);
245 UINT8 GetEventNotificationMask(void);
246  
247  
248  
249 #endif /*_WFDRIVERPRV_H_ */
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