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1 32 kaklik  
2 /*****************************************************************************
3 * FileName: mTouchCap_PIC18_CTMU_Physical.h
4 * Dependencies:
5 * Processor: PIC18
6 * Compiler: C18
7 * Linker: MPLINK
8 * Company: Microchip Technology Incorporated
9 *
10 * Software License Agreement
11 *
12 * Copyright © 2009 Microchip Technology Inc.
13 * Microchip licenses this software to you solely for use with Microchip products, according to the terms of the
14 * accompanying click-wrap software license. Microchip and its licensors retain all right, title and interest in
15 * and to the software. All rights reserved. This software and any accompanying information is for suggestion only.
16 * It shall not be deemed to modify Microchip’s standard warranty for its products. It is your responsibility to ensure
17 * that this software meets your requirements.
18  
19 * SOFTWARE IS PROVIDED “AS IS” WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED,
20 * INCLUDING WITHOUT LIMITATION, ANY WARRANTY OF MERCHANTABILITY, TITLE, NON-INFRINGEMENT
21 * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP OR ITS LICENSORS BE LIABLE
22 * FOR ANY DIRECT OR INDIRECT DAMAGES OR EXPENSES INCLUDING BUT NOT LIMITED TO INCIDENTAL,
23 * SPECIAL, INDIRECT, PUNITIVE OR CONSEQUENTIAL DAMAGES, LOST PROFITS OR LOST DATA,
24 * COST OF PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, OR ANY CLAIMS BY THIRD PARTIES
25 * (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF), OR OTHER SIMILAR COSTS.
26 * The aggregate and cumulative liability of Microchip and its licensors for damages related to the use of the software
27 * will in no event exceed $1000 or the amount you paid Microchip for the software, whichever is greater.
28  
29 * MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE OF THESE TERMS AND
30 * THE TERMS OF THE ACCOMPANYING CLICK-WRAP SOFTWARE LICENSE.
31 *
32 *
33 * Author Date Comment
34 *~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
35 * Naveen. M 14 Apr 2009 Version 0.1 Initial Draft
36 * Nithin Kumar. M 14 May 2009 Version 0.2 Updates
37 * Sasha. M / Naveen. M 4 June 2009 Version 0.3 Updates
38 * Sasha. M / Naveen. M 11 Nov 2009 Version 1.0 Release
39 * Sasha. M / Nithin. 10 April 2010 Version 1.20 Release
40 *****************************************************************************
41 *
42 *****************************************************************************/
43 #ifndef _MTOUCH_PIC18_CTMU_PHY_H
44 #define _MTOUCH_PIC18_CTMU_PHY_H
45  
46 /* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */
47 /* ~~~~~~~~~~~~~~~~~~~~~ Includes ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */
48 /* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */
49 #include "Config.h"
50 #include "HardwareProfile.h"
51 #include "mTouchCap_Timers.h"
52 #include "mTouchCap_Adc.h"
53  
54 #include "GenericTypeDefs.h"
55 #ifdef __18CXX
56  
57 /* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */
58 /* ~~~~~~~~~~~~~~~~~~~~~ Constants ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */
59 /* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */
60  
61  
62  
63  
64 /* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */
65 /* ~~~~~~~~~~~~~~~~~~~~~ Variables ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */
66 /* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */
67  
68  
69  
70 /* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */
71 /* ~~~~~~~~~~~~~~~~~~~~~ Variables ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */
72 /* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */
73  
74  
75 /* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */
76 /* ~~~~~~~~~~~~~~~~~~~~~ Externs ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */
77 /* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */
78 extern WORD curRawData [MAX_ADC_CHANNELS]; //Storage for CTMU channel values
79 extern WORD tripValue [MAX_ADC_CHANNELS]; //Storage for the trip point for each channel
80 extern WORD hystValue [MAX_ADC_CHANNELS]; //Storage for the hysterisis value for each channel
81 extern WORD pressedCount [MAX_ADC_CHANNELS]; //Storage for count of pressed value for each channel
82 extern WORD unpressedCount [MAX_ADC_CHANNELS]; //Storage for count of unpressed value for each channel
83 extern WORD avg_delay [MAX_ADC_CHANNELS];//Storage for count for average update for each channel
84 extern WORD averageData [MAX_ADC_CHANNELS]; // running average of CTMU channels
85 extern WORD smallAvg [MAX_ADC_CHANNELS]; // current button smallavg
86 extern WORD actualValue [MAX_ADC_CHANNELS]; // actual raw A/D counts for each channel
87 extern WORD channel_TRIM_value [MAX_ADC_CHANNELS];
88 extern WORD channel_IRNG_value [MAX_ADC_CHANNELS];
89 extern BYTE chFilterType [MAX_ADC_CHANNELS]; // Channel filter type
90 //extern BYTE chDecodeMethod [MAX_ADC_CHANNELS]; // decode method type
91 extern BYTE Press_State [MAX_ADC_CHANNELS];
92 extern SHORT startupCount; // variable to 'discard' first N samples
93 extern SHORT loopCount;
94 extern WORD immediateValue; // current button value
95 extern WORD scaledBigValue; // current button bigval
96  
97 extern WORD ScanChannels[MAX_ADC_CHANNELS];
98 extern BYTE Channel_Pressed_Status[MAX_ADC_CHANNELS];
99 /* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */
100 /* ~~~~~~~~~~~~~~~~~~~~~ Function Prototypes ~~~~~~~~~~~~~~~~~~~~~~~~~~ */
101 /* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */
102 void mTouchCapPhy_Init(void);
103 void mTouchCapPhy_InitCTMU(void);
104 void mTouchCapPhy_ChannelSetup(WORD ChannelNum);
105 void mTouchCapApp_PortSetup(void);
106 WORD mTouchCapPhy_Read_ADC(void);
107 void mTouchCapPhy_ReadCTMU(WORD ChannelNumber);
108 void mTouchCapPhy_CTMUSetup(void);
109 void mTouchCapPhy_AdcSetup(void);
110 void mTouchCapPhy_ChargeTimeInit(void);
111 void mTouchCapPhy_SetupCurrentSourceRange(WORD CurrentSourceRange);
112 void mTouchCapPhy_SetTrimValue( WORD TrimValue);
113 void mTouchCapPhy_Discharge_Current (void);
114 void mTouchCapPhy_Charge_Current (void);
115 WORD mTouchCapPhy_Read_ADC();
116 void mTouchCapPhy_StablizeChannelData(void);
117  
118 void CTMU_Current_trim_config(int channel_no);
119 void DynamicTripValueCalculation(WORD Index);
120 void mTouchCapPhy_AverageData(WORD Index);
121 /* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */
122 /* ~~~~~~~~~~~~~~~~~~~~~ Enums ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */
123 /* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */
124  
125  
126  
127 /* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */
128 /* ~~~~~~~~~~~~~~~~~~~~~ Constants / Macros ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */
129 /* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */
130  
131 #define PLL_ENABLED
132 #define PLL_EN_BIT OSCTUNEbits.PLLEN
133  
134  
135 //================pLIB=================================
136  
137 /***********************************************************************/
138 /********************ANALOG CHANNELS TRISBITS DEFINITION*****************************************/
139 /***********************************************************************/
140 #define DIGITAL 1
141 #define ANALOG 0
142  
143  
144 #define TRIS_CHANNEL_AN0 TRISAbits.TRISA0
145 #define TRIS_CHANNEL_AN1 TRISAbits.TRISA1
146 #define TRIS_CHANNEL_AN2 TRISAbits.TRISA2
147 #define TRIS_CHANNEL_AN3 TRISAbits.TRISA3
148 #define TRIS_CHANNEL_AN4 TRISAbits.TRISA5
149 #define TRIS_CHANNEL_AN5 TRISEbits.TRISE0
150 #define TRIS_CHANNEL_AN6 TRISEbits.TRISE1
151 #define TRIS_CHANNEL_AN7 TRISEbits.TRISE2
152 #define TRIS_CHANNEL_AN8 TRISBbits.TRISB2
153 #define TRIS_CHANNEL_AN9 TRISBbits.TRISB3
154 #define TRIS_CHANNEL_AN1O TRISBbits.TRISB1
155 #define TRIS_CHANNEL_AN11 TRISCbits.TRISC2
156 #define TRIS_CHANNEL_AN12 TRISBbits.TRISB0
157  
158 #define ADPCF_CHANNEL_AN0(Value) ANCON0bits.PCFG0 = Value;
159 #define ADPCF_CHANNEL_AN1(Value) ANCON0bits.PCFG1 = Value;
160 #define ADPCF_CHANNEL_AN2(Value) ANCON0bits.PCFG2 = Value;
161 #define ADPCF_CHANNEL_AN3(Value) ANCON0bits.PCFG3 = Value;
162 #define ADPCF_CHANNEL_AN4(Value) ANCON0bits.PCFG4 = Value;
163 #define ADPCF_CHANNEL_AN5(Value) ANCON0bits.PCFG5 = Value;
164 #define ADPCF_CHANNEL_AN6(Value) ANCON0bits.PCFG6 = Value;
165 #define ADPCF_CHANNEL_AN7(Value) ANCON0bits.PCFG7 = Value;
166 #define ADPCF_CHANNEL_AN8(Value) ANCON1bits.PCFG8 = Value;
167 #define ADPCF_CHANNEL_AN9(Value) ANCON1bits.PCFG9 = Value;
168 #define ADPCF_CHANNEL_AN10(Value) ANCON1bits.PCFG10 = Value;
169 #define ADPCF_CHANNEL_AN11(Value) ANCON1bits.PCFG11 = Value;
170 #define ADPCF_CHANNEL_AN12(Value) ANCON1bits.PCFG12 = Value;
171  
172 /***********************************************************************/
173 /********************A D C*****************************************/
174 /***********************************************************************/
175 /***********************************************************************/
176 #define INIT_AD1PCFGL_VALUE 0x0000
177 #define INIT_AD1CON1_VALUE 0x0000
178 #define INIT_AD1CHS_VALUE 0x0000 //select the analog channel 0
179  
180 /***********************************************************************
181 Macro : EnableIntADC1
182 Overview : This macro enables the ADC interrupt.
183 Parameters : None
184 Remarks : This macro sets ADC Interrupt Enable bit of Interrupt
185 Enable Control Register.
186 ************************************************************************/
187 #define EnableIntADC1 (PIE1bits.ADIE = 1)
188  
189 /***********************************************************************
190 Macro : DisableIntADC1
191 Overview : This macro disables the ADC interrupt.
192 Parameters : None
193 Remarks : This macro clears ADC Interrupt Enable bit of Interrupt
194 Enable Control register.
195 ************************************************************************/
196 #define DisableIntADC1 (PIE1bits.ADIE = 0)
197  
198 /***********************************************************************
199 Macro : SetPriorityIntADC1(priority)
200 Overview : This macro sets priority for ADC interrupt.
201 Parameters : priority - This input parameter is the level of interrupt priority
202 Remarks : This macro sets ADC Interrupt Priority bits of Interrupt
203 Priority Control register.
204 ************************************************************************/
205 #define SetPriorityIntADC1(priority) //STD: set prio (IPC3bits.AD1IP = priority)
206  
207 /*******************************************************************
208 Macro : ADC1_Clear_Intr_Status_Bit
209 Overview : Macro to Clear ADC Interrupt Status bit
210 Parameters : None
211 Remarks : None
212 *******************************************************************/
213 #define ADC1_Clear_Intr_Status_Bit ( PIR1bits.ADIF = 0) //PIC18
214  
215 /*******************************************************************
216 Macro : ADC1_IF_Bit
217 Overview : returns ADC1 Interrupt Flag
218 Parameters : None
219 Remarks : None
220 *******************************************************************/
221 #define ADC1_IF_Bit (PIR1bits.ADIF)
222  
223  
224 /************************************************************************
225 Macro : BusySampADC1
226 Overview : This function is identical to ConvertADC10
227 Parameters : None
228 Remarks : This macro clears the ADCON1<SAMP> bit and thus stops sampling
229 and starts conversion.
230 **************************************************************************/
231 #define BusySampADC1 !(AD1CON1bits.SAMP)
232  
233 /************************************************************************
234 Macro : EnableADC1
235 Overview : This function enables the ADC module
236 Parameters : None
237 Remarks : None.
238 **************************************************************************/
239 #define EnableADC1 (AD1CON1bits.ADON = 1)
240  
241 /************************************************************************
242 Macro : DisableADC1
243 Overview : This function disables the ADC module
244 Parameters : None
245 Remarks : None.
246 **************************************************************************/
247 #define DisableADC1 (ADCON0bits.ADON = 0)
248  
249 /************************************************************************
250 Macro : Set_Adc_Enable_State
251 Overview : This function enables or disable the ADC module depending upon the value.
252 Parameters : None
253 Remarks : None.
254 **************************************************************************/
255 #define Set_Adc_Enable_State(Value) (ADCON0bits.ADON = Value) //PIC18
256  
257  
258 /************************************************************************
259 Macro : Enable_ADC_Sampling
260 Overview : This function starts the A/D conversion.
261 Parameters : None
262 Remarks : None.
263 **************************************************************************/
264 #define Enable_ADC_Sampling (ADCON0bits.GO = 1) //PIC18
265  
266  
267 /************************************************************************
268 Macro : Disable_ADC_Sampling
269 Overview : This function starts the A/D conversion.
270 Parameters : None
271 Remarks : None.
272 **************************************************************************/
273 #define Disable_ADC_Sampling (ADCON0bits.GO = 0) //PIC18
274  
275  
276 /************************************************************************
277 Macro : ADC_GO_Bit
278 Overview : This function declares the AD1CON1bits.DONE.
279 Parameters : None
280 Remarks : None.
281 **************************************************************************/
282 #define ADC_GO_Bit (ADCON0bits.GO)
283  
284  
285 /************************************************************************
286 Macro : ADC_Done_Bit
287 Overview : This function declares the AD1CON1bits.DONE.
288 Parameters : None
289 Remarks : None.
290 **************************************************************************/
291 #define ADC_Done_Bit (ADCON0bits.DONE) //PIC18
292  
293 /************************************************************************
294 Macro : Adc_Port_Configuration1
295 Overview : Configure ADC Port pin as Analog or Digital for register0
296 Parameters : None
297 Remarks : None.
298 **************************************************************************/
299 #define Adc_Port_Configuration1(Value) (ANCON0 = Value) //PIC18
300  
301 /************************************************************************
302 Macro : Adc_Port_Configuration1
303 Overview : Configure ADC Port pin as Analog or Digital for register1
304 Parameters : None
305 Remarks : None.
306 **************************************************************************/
307 #define Adc_Port_Configuration2(Value) (ANCON1 = Value) //PIC18
308 /************************************************************************
309  
310 Redefining ADC Register
311  
312 **************************************************************************/
313 #define ADC_CHANNEL_SELECT ADCON0bits.CHS
314 #define ADCSSL //AD1CSSL PIC18
315 #define AD_CON_REG1 ADCON1
316 #define AD_CON_REG0 ADCON0
317 #define ADCBUF ADC1BUF0
318  
319  
320 /*Registers Defaults*/
321 #define ADCSSL_VAL 0x00
322 #define ADCON1_VAL 0x00
323 #define ADCON0_VAL 0x00
324 #define ADC_PRIORITY 0x00
325 #define ADC_PORT_CONFIG_DEFAULT_VALUE 0x00 // Default Value of ADC Port Configuration Register.
326  
327  
328 /*AD1CON0 register definition*/
329 //************** Voltage Reference Configuration ******************************
330 #define ADC_REF_VDD_VREFMINUS 0b00000010 // ADC voltage source VREF+ = VDD and VREF- = ext.source at VREF-
331 #define ADC_REF_VREFPLUS_VREFMINUS 0b00000011 // ADC voltage source VREF+ = ext.source at VREF+ and VREF- = ext.source at VREF-
332 #define ADC_REF_VREFPLUS_VSS 0b00000001 // ADC voltage source VREF+ = ext.source at VREF+ and VREF- = VSS
333 #define ADC_REF_VDD_VSS 0b00000000 // ADC voltage source VREF+ = VDD and VREF- = VSS
334  
335  
336 //**************** channel selection ******************************************
337 #define ADC_CH0 0b10000111 //Select Channel 0
338 #define ADC_CH1 0b10001111 //Select Channel 1
339 #define ADC_CH2 0b10010111 //Select Channel 2
340 #define ADC_CH3 0b10011111 //Select Channel 3
341 #define ADC_CH4 0b10100111 //Select Channel 4
342 #define ADC_CH5 0b10101111 //Select Channel 5
343 #define ADC_CH6 0b10110111 //Select Channel 6
344 #define ADC_CH7 0b10111111 //Select Channel 7
345 #define ADC_CH8 0b11000111 //Select Channel 8
346 #define ADC_CH9 0b11001111 //Select Channel 9
347 #define ADC_CH10 0b11010111 //Select Channel 10
348 #define ADC_CH11 0b11011111 //Select Channel 11
349 #define ADC_CH12 0b11100111 //Select Channel 12
350  
351  
352 /*AD1CON1 control register definition*/
353 //*************** A/D Conversion Clock Select *****************************
354 #define ADC_FOSC_2 0b00000000 //A/D conversion clock source is Fosc/2
355 #define ADC_FOSC_4 0b00000100 //A/D conversion clock source is Fosc/4
356 #define ADC_FOSC_8 0b00000001 //A/D conversion clock source is Fosc/8
357 #define ADC_FOSC_16 0b00000101 //A/D conversion clock source is Fosc/16
358 #define ADC_FOSC_32 0b00000010 //A/D conversion clock source is Fosc/32
359 #define ADC_FOSC_64 0b00000110 //A/D conversion clock source is Fosc/64
360 #define ADC_FOSC_RC 0b00000111 //A/D conversion clock source is Internal RC OSC
361  
362  
363 //************** A/D Acquisition Time Selection *******************************
364 #define ADC_0_TAD 0b00000000 //A/D Acquisition Time is 0 TAD
365 #define ADC_2_TAD 0b00001000 //A/D Acquisition Time is 2 TAD
366 #define ADC_4_TAD 0b00010000 //A/D Acquisition Time is 4 TAD
367 #define ADC_6_TAD 0b00011000 //A/D Acquisition Time is 6 TAD
368 #define ADC_8_TAD 0b00100000 //A/D Acquisition Time is 8 TAD
369 #define ADC_12_TAD 0b00101000 //A/D Acquisition Time is 12 TAD
370 #define ADC_16_TAD 0b00110000 //A/D Acquisition Time is 16 TAD
371 #define ADC_20_TAD 0b00111000 //A/D Acquisition Time is 20 TAD
372  
373  
374 //*************** A/D Result Format Select ***********************************
375 #define ADC_RIGHT_JUST 0b10000000 // Right justify A/D result
376 #define ADC_LEFT_JUST 0b00000000 // Left justify A/D result
377  
378 /***********************************************************************************
379 Macro : ADC_CALIB()
380 Overview : Macro performs the Calibration on next A/D conversion
381 Parameters : None
382 Remarks : None
383 ***********************************************************************************/
384 #define ADC_CALIB() (ADCON1bits.ADCAL=1)
385  
386 /***********************************************************************************
387 Macro : ADC_NO_CALIB()
388 Overview : Macro performs the Normal A/D converter operation with no Calibration
389 Parameters : None
390 Remarks : None
391 ***********************************************************************************/
392 #define ADC_NO_CALIB() (ADCON1bits.ADCAL=0)
393  
394 /*ADCON0 and ADCON1 register Values*/
395  
396 #define ADC_CONFIG_ADCON0 (ADCON0_VAL | ADC_REF_VDD_VSS)
397 #define ADC_CONFIG_ADCON1 (ADCON1_VAL | ADC_RIGHT_JUST | ADC_FOSC_4 | ADC_2_TAD)
398  
399  
400 /***********************************************************************/
401 /********************C O M P A R A T O R********************************/
402 /***********************************************************************/
403 /***********************************************************************/
404 /*Comparator register definition*/
405 #define CMP_CMCON CM2CON
406 #define CMP_CVRCON CVRCON
407  
408 /*CMCON control register bit definition*/
409 #define CMP_Enable_Disable_Bit CM2CONbits.CON
410 #define CMP_Output_Enable_Disable_Bit CM2CONbits.COE
411 #define CMP_Output_Polarity_Bit CM2CONbits.CPOL
412 #define CMP_Event_Bit CM2CONbits.CEVT
413 #define CMP_CMCON_Ouput_Bit CM2CONbits.COUT
414 #define CMP_Trigger_Select_HighBit CM2CONbits.EVPOL1
415 #define CMP_Trigger_Select_LowBit CM2CONbits.EVPOL0
416 #define CMP_Reference_Select_Bit CM2CONbits.CREF
417 #define CMP_Channel_Select_HighBit CM2CONbits.CCH1
418 #define CMP_Channel_Select_LowBit CM2CONbits.CCH0
419 #define CMP_Trigger_Select_Bits CM2CONbits.EVPOL
420 #define CMP_Channel_Select_Bits CM2CONbits.CCH
421  
422 /*CMSTAT register bit definition*/
423 #define CMP_Ouput_Bit CMSTATbits.C2OUT
424  
425 /*CMCON interrupt register bit definition*/
426  
427 #define CMP_Interrupt_Flag_Bit IFS1bits.CMIF
428 #define CMP_Interrupt_Enable_Bit IEC1bits.CMIE
429 #define CMP_Interrupt_Priority_Bits IPC4bits.CMIP
430  
431 /******************************************************************************
432 Macro : CMP_EnblDsbl(state)
433 Overview : Macro Enables/Disables the Comparator
434 Parameter : state - *1 Comparator is enabled
435 *0 Comparator is disabled
436 Remarks : None
437 *****************************************************************************/
438 #define CMP_EnblDsbl(state) (CMP_Enable_Disable_Bit = state)
439  
440 /******************************************************************************
441 Macro : CMP_Output_EnblDsbl(state)
442 Overview : Macro Enables/Disables Comparator output on the output pad
443 Parameter : state - *1 Comparator output driven on the output pad
444 *0 Comparator output is not driven on the output pad
445 Remarks : None
446 *****************************************************************************/
447 #define CMP_Output_EnblDsbl(state) (CMP_Output_Enable_Disable_Bit = state)
448  
449 /******************************************************************************
450 Macro : CMP_Output_Polarity(state)
451 Overview :
452 Parameter : state - *1
453 *0
454 Remarks : None
455 *****************************************************************************/
456 #define CMP_Output_Polarity(state) (CMP_Output_Polarity_Bit = state)
457  
458  
459 /******************************************************************************
460 Macro : CMP_Output_Polarity(state)
461 Overview :
462 Parameter : state - *1
463 *0
464 Remarks : None
465 *****************************************************************************/
466 #define CMP_Event(state) (CMP_Event_Bit = state)
467  
468  
469 /******************************************************************************
470 Macro : CMP_Trigger_Select(state)
471 Overview :
472 Parameter : state - *1
473 *0
474 Remarks : None
475 *****************************************************************************/
476 #define CMP_Trigger_Select(state) (CMP_Trigger_Select_Bits = state)
477  
478  
479 /******************************************************************************
480 Macro : CMP_Trigger_Select(state)
481 Overview :
482 Parameter : state - *1
483 *0
484 Remarks : None
485 *****************************************************************************/
486 #define CMP_Reference_Select(state) (CMP_Reference_Select_Bit = state)
487  
488  
489 /******************************************************************************
490 Macro : CMP_Channel_Select(state) //n1:
491 Overview :
492 Parameter : state - *1
493 *0
494 Remarks : None
495 *****************************************************************************/
496 #define CMP_Channel_Select(state) (CMP_Channel_Select_Bits = state)
497  
498 /******************************************************************************
499 Macro : CMP_Get_STATE()
500 Overview : Macro Returns state of Comparator output
501 When C2INV = 0:
502 1 = C2 VIN+ > C2 VIN-
503  
504 When C2INV = 1:
505  
506 1 = C2 VIN+ < C2 VIN-
507 Parameter : None
508 Remarks : State of Comparator depends on Inverse selection bit in
509 control register
510 *****************************************************************************/
511 #define CMP_Get_STATE() (CMP_Ouput_Bit)
512  
513 /***********************************************************************
514 Macro : EnableIntCMP
515 Overview : This macro enables the comparator interrupt.
516 Parameter : None
517 Remarks : This macro sets comparator Interrupt Enable bit of Interrupt
518 Enable Control Register.
519 ************************************************************************/
520 #define EnableIntCMP (CMP_Interrupt_Enable_Bit = 1)
521  
522 /***********************************************************************
523 Macro : DisableIntCMP
524 Overview : This macro disables the comparator interrupt.
525 Parameter : None
526 Remarks : This macro clears comparator Interrupt Enable bit of Interrupt
527 Enable Control register.
528 ************************************************************************/
529 #define DisableIntCMP (CMP_Interrupt_Enable_Bit = 0)
530  
531 /***********************************************************************
532 Macro : SetPriorityIntCMP (priority)
533 Overview : This macro sets priority for comparator interrupt.
534 Parameter : priority - This input parameter is the level of interrupt priority
535 Remarks : This macro sets comparator Interrupt Priority bits of Interrupt
536 Priority Control register.
537 ************************************************************************/
538 #define SetPriorityIntCMP(priority) (CMP_Interrupt_Priority_Bits = priority)
539  
540 /*******************************************************************
541 Macro : CMP_Clear_Intr_Status_Bit
542 Overview : Macro to Clear Comparator Interrupt Status bit
543 Parameter : None
544 Remarks : None
545 *******************************************************************/
546 #define CMP_Clear_Intr_Status_Bit (CMP_Interrupt_Flag_Bit = 0)
547  
548  
549 /*CMxCON register definition*/
550 #define CMP_ENABLE 0x8000 /* Comparator is enabled */
551 #define CMP_DISABLE 0x0000 /* Comparator is disabled */
552 #define CMP_ENBL_DSBL_MASK (~CMP_ENABLE)
553 #define CMP_OUTPUT_ENABLE 0x4000 /* Comparator output present on the CXOUT pin */
554 #define CMP_OUTPUT_DISABLE 0x0000 /* Comparator output is internal only */
555 #define CMP_OUTPUT_MASK (~CMP_OUTPUT_ENABLE)
556 #define CMP_OUTPUT_INVERT 0x2000 /* Comparator output inverted */
557 #define CMP_OUTPUT_NOT_INVERT 0x0000 /* Comparator output not inverted */
558 #define CMP_OUTPUT_INVERT_MASK (~CMP_OUTPUT_INVERT)
559 #define CMP_CHANGE_STATE 0x0200 /* Comparator output changed states */
560 #define CMP_NO_CHANGE 0x0000 /* Comparator output did not change states */
561 #define CMP_STATE_MASK (~CMP_CHANGE_STATE )
562 #define CMP_INTERRUPT_ON_ANY_EDGE 0X00C0 /* Comparator interrupt generated on any edge of the selected comparator output*/
563 #define CMP_INTERRUPT_ON_FALLING_EDGE 0X0080 /* Comparator interrupt generated only on falling edge of the selected comparator output*/
564 #define CMP_INTERRUPT_ON_RISING_EDGE 0X0040 /* Comparator interrupt generated only on rising edge of the selected comparator output*/
565 #define CMP_INTERRUPT_DISABLED 0X0000 /* Comparator interrupt generation is disabled */
566 #define CMP_INTERRUP_EDGE_MASK (~CMP_INTERRUPT_ON_ANY_EDGE)
567 #define CMP_POS_IP_CV_Ref 0x0010 /* Input is connected to internal CVref voltage */
568 #define CMP_POS_IP_CXINA 0x0000 /* Input is connected to CXINA pin */
569 #define CMP_POS_IP_MASK (~CMP_POS_IP_CV_Ref)
570 #define CMP_NEG_IP_CXINB 0X0000 /* Input is connected to CXINB pin */
571 #define CMP_NEG_IP_CXINC 0X0001 /* Input is connected to CXINC pin */
572 #define CMP_NEG_IP_CXIND 0X0002 /* Input is connected to CXIND pin */
573  
574 /*CVRCON register definition*/
575 #define CMP_VRef_Enable 0x0080 /* CVREF circuit powered on */
576 #define CMP_VRef_Disable 0x0000 /* CVREF circuit powered down */
577 #define CMP_VRef_MASK (~CMP_VRef_Enable)
578 #define CMP_VRef_OUTPUT_Enable 0x0040 /* CVREF voltage level is output on CVREF pin */
579 #define CMP_VRef_OUTPUT_Disable 0x0000 /* CVREF voltage level is disconnected from CVREF pin */
580 #define CMP_VRef_OUTPUT_MASK (~CMP_VRef_OUTPUT_Enable)
581 #define CMP_VRef_SELECT_24_STEPS 0x0020 /* 0 to 0.67 CVRSRC, with CVRSRC/24 step size */
582 #define CMP_VRef_SELECT_32_STEPS 0x0000 /* 0.25 CVRSRC to 0.75 CVRSRC, with CVRSRC/32 step size */
583 #define CMP_VRef_STEP_SELECT_MASK (~CMP_VRef_SELECT_24_STEPS)
584 #define CMP_Vrsrc_Vref_Vref 0x0010 /* Comparator reference source CVRSRC = VREF+ – VREF- */
585 #define CMP_Vrsrc_AVDD_AVSS 0x0000 /* Comparator reference source CVRSRC = AVDD – AVSS */
586 #define CMP_Vrsrc_MASK (~CMP_Vrsrc_Vref_Vref)
587 #define CMP_CVrsrc 0x000F /* 0 CVRSRC with CVRSRC/24 step size, 0.25 CVRSRC with CVRSRC/32 step size */
588  
589 /*Registers Defaults*/
590 #define CMP_CMCON_VAL 0x0000
591 #define CVREF_VAL 0x0000
592  
593  
594 #define CMP_CONFIG_CMCON (CMP_CMCON_VAL | CMP_ENABLE | CMP_OUTPUT_DISABLE | CMP_OUTPUT_NOT_INVERT \
595 | CMP_NO_CHANGE | CMP_INTERRUPT_DISABLED | CMP_POS_IP_CV_Ref | CMP_NEG_IP_CXINB)
596  
597 #define CMP_CONFIG_CVRCON (CVREF_VAL | CMP_VRef_Enable | CMP_VRef_OUTPUT_Enable | CMP_VRef_SELECT_32_STEPS \
598 | CMP_Vrsrc_AVDD_AVSS | CMP_CVrsrc)
599  
600  
601  
602 /***********************************************************************/
603 /********************C T M U********************************************/
604 /***********************************************************************/
605 /************************************************************************/
606 /*CTMUCON Control Register*/
607 #define CTMU_ENABLE 0x8000 /*CTMU is Enabled*/
608 #define CTMU_DISABLE 0x0000 /*CTMU is Disabled*/
609 #define CTMU_ENBL_DISBL_MASK (~CTMU_ENABLE)
610  
611 #define CTMU_IDLE_STOP 0x2000 /*CTMU discontinue module operation in Idle mode*/
612 #define CTMU_IDLE_CONTINUE 0x0000 /*CTMU Operate in Idle mode*/
613 #define CTMU_IDLE_MASK (~CTMU_IDLE_STOP)
614  
615 #define CTMU_TIME_GEN_ENABLE 0x1000 /*CTMU enables edge delay generation*/
616 #define CTMU_TIME_GEN_DISABLE 0x0000 /*CTMU disables edge delay generation*/
617 #define CTMU_TIME_GEN_MASK (~CTMU_TIME_GEN_ENABLE)
618  
619 #define CTMU_EDGE_ENABLE 0x0800 /*CTMU edges are not blocked*/
620 #define CTMU_EDGE_DISABLE 0x0000 /*CTMU edges are blocked*/
621 #define CTMU_EDGE_MASK (~CTMU_EDGE_ENABLE)
622  
623 #define CTMU_EDGE_SEQUENCE_ON 0x0400 /*Edge1 event must occur before edge2 event can occur*/
624 #define CTMU_EDGE_SEQUENCE_OFF 0x0000 /*No edge sequence os needed*/
625 #define CTMU_EDGE_SEQUENCE_MASK (~CTMU_EDGE_SEQUENCE)
626  
627 #define CTMU_ANA_CURR_SOURCE_GND 0x0200 /*CTMU Analog current source output is grounded*/
628 #define CTMU_ANA_CURR_SOURCE_NOT_GND 0x0000 /*CTMU Analog current source output is not grounded*/
629 #define CTMU_ANA_CURR_SOURCE_MASK (~CTMU_ANA_CURR_SOURCE_GND)
630  
631 #define CTMU_TRIG_OUTPUT_ENABLE 0x0100 /*Trigger output is enabled*/
632 #define CTMU_TRIG_OUTPUT_DISABLE 0x0000 /*Trigger output is disabled*/
633 #define CTMU_TRIG_OUTPUT_MASK (~CTMU_TRIG_OUTPUT)
634  
635 #define CTMU_EDGE1_POLARITY_POS 0x0010 /*Edge 1 programmed for a positive edge response*/
636 #define CTMU_EDGE1_POLARITY_NEG 0x0000 /*Edge 1 programmed for a negative edge response*/
637 #define CTMU_EDGE1_POLARITY_MASK (~CTMU_EDGE2_POS_POLARITY)
638  
639 #define CTMU_EDGE1_SOURCE_CTED1 0x000C /*CTED1 is a source select for Edge1*/
640 #define CTMU_EDGE1_SOURCE_CTED2 0x0008 /*CTED2 is a source select for Edge1*/
641 #define CTMU_EDGE1_SOURCE_OC1 0x0004 /*OC1 is a source select for Edge1*/
642 #define CTMU_EDGE1_SOURCE_TIMER1 0x0000 /*TIMER1 is a source select for Edge1*/
643 #define CTMU_EDGE1_SOURCE_MASK (~CTMU_EDGE2_SOURCE_CTED1)
644  
645 #define CTMU_EDGE2_POLARITY_POS 0x0080 /*Edge 2 programmed for a positive edge response*/
646 #define CTMU_EDGE2_POLARITY_NEG 0x0000 /*Edge 2 programmed for a negative edge response*/
647 #define CTMU_EDGE2_POLARITY_MASK (~CTMU_EDGE2_POS_POLARITY)
648  
649 #define CTMU_EDGE2_SOURCE_CTED1 0x0060 /*CTED1 is a source select for Edge2*/
650 #define CTMU_EDGE2_SOURCE_CTED2 0x0040 /*CTED2 is a source select for Edge2*/
651 #define CTMU_EDGE2_SOURCE_OC1 0x0020 /*OC1 is a source select for Edge2*/
652 #define CTMU_EDGE2_SOURCE_TIMER1 0x0000 /*TIMER1 is a source select for Edge2*/
653 #define CTMU_EDGE2_SOURCE_MASK (~CTMU_EDGE2_SOURCE_CTED1)
654  
655 /*CTMU1CON Current Control register*/
656 #define CTMU_POS_CURR_TRIM 0x0400 /*2% of Positive change from nominal current*/
657 #define CTMU_NEG_CURR_TRIM 0xFC00 /*2% of Negative change from nominal current*/
658 #define CTMU_NOMINAL_CURRENT 0x0000 /*Nominal Current output specified by IRNG1:IRNG0*/
659 #define CTMU_CURR_RANGE_100_BASE_CURR 0x0300 /*Current source Range is 100*Base current (55uA) */
660 #define CTMU_CURR_RANGE_10_BASE_CURR 0x0200 /*Current source Range is 10*Base current (5.5uA)*/
661 #define CTMU_CURR_RANGE_BASE_CURR 0x0100 /*Current source Range is Base current (0.55uA)*/
662 #define CTUM_CURR_SOURCE_DISABLE 0x0000 /*Current source disabled*/
663  
664  
665 #define CTMU_INT_PRI 0x0000 /*CTMU interrupt priority is 0*/
666  
667 #define CTMU_INT_ENABLE 0x0008 /* Enable CTMU interrupts */
668 #define CTMU_INT_DISABLE 0x0000 /* Disable CTMU interrupts */
669  
670  
671 /************************************************************************
672 Macro : Set_CTMU_ENABLE_Status
673 Overview : setting or clearing CTMU Enable Module Bit
674 Parameters : ENABLE '1' or DISABLE '0'
675 Remarks : None.
676 **************************************************************************/
677 #define Set_CTMU_ENABLE_Status(State) (CTMUCONHbits.CTMUEN = State)
678  
679 /************************************************************************
680 Macro : Idle_Mode_CTMU_Operation
681 Overview : CTMU Operation in Idle
682 Parameters : ENABLE '1' or DISABLE '0'
683 Remarks : None.
684 **************************************************************************/
685 #define Idle_Mode_CTMU_Operation(State) (CTMUCONHbits.CTMUSIDL = State)
686  
687 /************************************************************************
688 Macro : Set_CTMU_Time_Generation
689 Overview : setting or clearing CTMU TIME Generation Bit
690 Parameters : ENABLE '1' or DISABLE '0'
691 Remarks : None.
692 **************************************************************************/
693 #define Set_CTMU_Time_Generation(State) (CTMUCONHbits.TGEN = State)
694  
695  
696 /************************************************************************
697 Macro : Enable_Disable_CTMU_Time_Generation
698 Overview : setting or clearing CTMU TIME Generation Bit
699 Parameters : ENABLE '1' or DISABLE '0'
700 Remarks : None.
701 **************************************************************************/
702 #define Block_CTMU_Edge(State) (CTMUCONHbits.EDGEN = 0)
703  
704 /************************************************************************
705 Macro : Enable_Disable_CTMU_Time_Generation
706 Overview : setting or clearing CTMU TIME Generation Bit
707 Parameters : ENABLE '1' or DISABLE '0'
708 Remarks : None.
709 **************************************************************************/
710 #define Unblock_CTMU_Edge(State) (CTMUCONHbits.EDGEN = 1)
711  
712  
713 /************************************************************************
714 Macro : Set_CTMU_Edge_Sequence
715 Overview : setting or clearing CTMU Edge Sequence Bit
716 Parameters : ENABLE '1' or DISABLE '0'
717 Remarks : None.
718 **************************************************************************/
719 #define Set_Edge_Sequence(State) (CTMUCONHbits.EDGSEQEN = State)
720  
721  
722 /************************************************************************
723 Macro : Enable_CTMU_CurrentDischarge
724 Overview : setting the CTMU Current Discharge Bit
725 Parameters : None
726 Remarks : None.
727 **************************************************************************/
728 #define Enable_CTMU_CurrentDischarge (CTMUCONHbits.IDISSEN = 1)
729  
730 /************************************************************************
731 Macro : Disable_CTMU_CurrentDischarge
732 Overview : Clearing the CTMU Current Discharge Bit
733 Parameters : None
734 Remarks : None.
735 **************************************************************************/
736  
737 #define Disable_CTMU_CurrentDischarge (CTMUCONHbits.IDISSEN = 0)
738  
739  
740 /************************************************************************
741 Macro : Set_CTMU_Trigger_Control
742 Overview : setting or clearing CTMU Trigger Control Bit
743 Parameters : ENABLE '1' or DISABLE '0'
744 Remarks : None.
745 **************************************************************************/
746 #define Set_CTMU_Trigger_Control(State) (CTMUCONHbits.CTTRIG = State)
747  
748  
749  
750 /************************************************************************
751 Macro : Enable_CTMU_Positive_Edge2_Polarity
752 Overview : By setting Edge 2 Polarity Select bit
753 Parameters : None
754 Remarks : None.
755 **************************************************************************/
756 #define Enable_CTMU_Positive_Edge2_Polarity (CTMUCONLbits.EDG2POL = 1)
757  
758  
759 /************************************************************************
760 Macro : Enable_CTMU_Negative_Edge2_Polarity
761 Overview : By setting Edge 2 Polarity Select bit
762 Parameters : None
763 Remarks : None.
764 **************************************************************************/
765 #define Enable_CTMU_Negative_Edge2_Polarity (CTMUCONLbits.EDG2POL = 0)
766  
767  
768 /************************************************************************
769 Macro : Enable_CTMU_Positive_Edge1_Polarity
770 Overview : By setting Edge 1 Polarity Select bit
771 Parameters : None
772 Remarks : None.
773 **************************************************************************/
774 #define Enable_CTMU_Positive_Edge1_Polarity (CTMUCONLbits.EDG1POL = 1)
775  
776  
777 /************************************************************************
778 Macro : Enable_CTMU_Negative_Edge1_Polarity
779 Overview : By setting Edge 1 Polarity Select bit
780 Parameters : None
781 Remarks : None.
782 **************************************************************************/
783 #define Enable_CTMU_Negative_Edge1_Polarity (CTMUCONLbits.EDG1POL = 0)
784  
785  
786 /************************************************************************
787 Macro : CTMU_Edge1_Source_Select
788 Overview : Edge 1 Source Select bits
789 Parameters : State
790 Remarks : None.
791 **************************************************************************/
792 //PIC18
793 #define CTMU_Edge1_Source_Select(State) (CTMUCONLbits.EDG1SEL0 = (State&0x01) && (CTMUCONLbits.EDG1SEL1 = (State&0x02)>>1))
794  
795  
796 /************************************************************************
797 Macro : CTMU_Edge2_Source_Select
798 Overview : Edge 2 Source Select bits
799 Parameters :
800 Remarks : None.
801 **************************************************************************/
802 //PIC18
803 #define CTMU_Edge2_Source_Select(State) (CTMUCONLbits.EDG2SEL0 = (State&0x01) && (CTMUCONLbits.EDG2SEL1 = (State&0x02)>>1))
804  
805  
806 /************************************************************************
807 Macro : Enable_CTMUEdge1
808 Overview : By setting edge1 status bit current source enables
809 Parameters : None
810 Remarks : None.
811 **************************************************************************/
812 #define Enable_CTMUEdge1 (CTMUCONLbits.EDG1STAT = 1)
813  
814  
815 /************************************************************************
816 Macro : Enable_CTMUEdge2
817 Overview : By setting edge2 status bit current source enables
818 Parameters : None
819 Remarks : None.
820 **************************************************************************/
821 #define Enable_CTMUEdge2 (CTMUCONLbits.EDG2STAT = 1)
822  
823  
824 /************************************************************************
825 Macro :Disbl_CTMUEdge1
826 Overview : By clearing edge1 status bit disable the current source
827 Parameters : None
828 Remarks : None.
829 **************************************************************************/
830 #define Disbl_CTMUEdge1 (CTMUCONLbits.EDG1STAT = 0)
831  
832  
833 /************************************************************************
834 Macro :Disbl_CTMUEdge2
835 Overview : By clearing edge2 status bit disable the current source
836 Parameters : None
837 Remarks : None.
838 **************************************************************************/
839 #define Disbl_CTMUEdge2 (CTMUCONLbits.EDG2STAT = 0)
840  
841  
842 /************************************************************************
843 Macro : Disbl_Currentsource
844 Overview : By clearing EDGSTAT bit disable the source.
845 Parameters : None
846 Remarks : None.
847 **************************************************************************/
848 #define Disbl_CurrentSource ( CTMUCONLbits.EDG1STAT = 0 , CTMUCONLbits.EDG2STAT = 0 )
849  
850  
851 /************************************************************************
852 Macro : Enabl_Currentsource
853 Overview : By setting EDGSTAT bit disable the source.
854 Parameters : None
855 Remarks : None.
856 **************************************************************************/
857 #define Enable_CurrentSource (CTMUCONLbits.EDG1STAT = 1 , CTMUCONLbits.EDG2STAT = 1 )
858  
859  
860 /************************************************************************
861 Macro : CTMUEdge1_Status
862 Overview : Returns the status of CTMU edge1
863 Parameters : None
864 Remarks : None.
865 **************************************************************************/
866 #define CTMUEdge1_Status CTMUCONLbits.EDG1STAT
867  
868 /************************************************************************
869 Macro : CTMUEdge2_Status
870 Overview : Returns the status of CTMU edge2
871 Parameters : None
872 Remarks : None.
873 **************************************************************************/
874 #define CTMUEdge2_Status CTMUCONLbits.EDG2STAT
875  
876  
877 /************************************************************************
878 Macro : CTMU_Trim_Value
879 Overview : Sets the Trim Value for CTMU
880 Parameters : None
881 Remarks : None.
882 **************************************************************************/
883 #define CTMU_Trim_Value(Value) CTMUICONbits.ITRIM = (Value)
884  
885  
886  
887 /************************************************************************
888 Macro : CTMU_Select_Current_Source
889 Overview : Sets the current source range Value for CTMU
890 Parameters : CURRENT_RANGE_100XBASE_CURRENT //urrent source Range is 100*Base current (55uA)
891 * CURRENT_RANGE_10XBASE_CURRENT //Current source Range is 10*Base current (5.5uA)
892 * CURRENT_RANGE_BASE_CURRENT //Current source Range is Base current (0.55uA)
893 * CURRENT_SRC_DISABLED //Current source disabled
894 *
895 Remarks : None.
896 **************************************************************************/
897 #define CTMU_Select_Current_Source(Value) CTMUICONbits.IRNG = (Value)
898  
899  
900 /************************************************************************
901 Macro : CTMU_Get_Current_Source
902 Overview : Gets the Current Source range value
903 Parameters : None
904 Remarks : None.
905 **************************************************************************/
906 #define CTMU_Get_Current_Source CTMUICONbits.IRNG
907  
908  
909 /***********************************************************************
910 Macro : EnableIntCTMU
911 Overview : This macro enables the CTMU interrupt.
912 Parameters : None
913 Remarks : This macro sets CTMU Interrupt Enable bit of Interrupt
914 Enable Control Register.
915 ************************************************************************/
916 #define EnableIntCTMU (IEC4bits.CTMUIE = 1)
917  
918 /***********************************************************************
919 Macro : DisableIntCTMU
920 Overview : This macro disables the CTMU interrupt.
921 Parameters : None
922 Remarks : This macro clears CTMU Interrupt Enable bit of Interrupt
923 Enable Control register.
924 ************************************************************************/
925 #define DisableIntCTMU (IEC4bits.CTMUIE = 0)
926  
927 /***********************************************************************
928 Macro : SetPriorityIntCTMU(priority)
929 Overview : This macro sets priority for CTMU interrupt.
930 Parameters : priority - This input parameter is the level of interrupt priority
931 Remarks : This macro sets CTMU Interrupt Priority bits of Interrupt
932 Priority Control register.
933 ************************************************************************/
934 #define SetPriorityIntCTMU(priority) (IPC19bits.CTMUIP = priority)
935  
936 /*******************************************************************
937 Macro : CTMU_Clear_Intr_Status_Bit
938 Overview : Macro to Clear CTMU Interrupt Status bit
939 Parameters : None
940 Remarks : None
941 *******************************************************************/
942 #define CTMU_Clear_Intr_Status_Bit (IFS4bits.CTMUIF = 0)
943  
944  
945  
946 #endif //#ifdef __18CXX
947  
948  
949 #endif // _MTOUCH_PIC18_CTMU_PHY_H
950  
951  
952  
953  
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