| Line No. | Rev | Author | Line |
|---|---|---|---|
| 1 | 32 | kaklik | |
| 2 | /***************************************************************************** |
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| 3 | * FileName: mTouchCap_PIC24_CTMU_Physical.h |
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| 4 | * Dependencies: |
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| 5 | * Processor: PIC24 |
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| 6 | * Compiler: C30 |
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| 7 | * Linker: MPLAB LINK30 |
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| 8 | * Company: Microchip Technology Incorporated |
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| 9 | * |
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| 10 | * Software License Agreement |
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| 11 | * |
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| 12 | * Copyright © 2009 Microchip Technology Inc. |
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| 13 | * Microchip licenses this software to you solely for use with Microchip products, according to the terms of the |
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| 14 | * accompanying click-wrap software license. Microchip and its licensors retain all right, title and interest in |
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| 15 | * and to the software. All rights reserved. This software and any accompanying information is for suggestion only. |
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| 16 | * It shall not be deemed to modify Microchips standard warranty for its products. It is your responsibility to ensure |
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| 17 | * that this software meets your requirements. |
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| 18 | |||
| 19 | * SOFTWARE IS PROVIDED AS IS WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED, |
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| 20 | * INCLUDING WITHOUT LIMITATION, ANY WARRANTY OF MERCHANTABILITY, TITLE, NON-INFRINGEMENT |
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| 21 | * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP OR ITS LICENSORS BE LIABLE |
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| 22 | * FOR ANY DIRECT OR INDIRECT DAMAGES OR EXPENSES INCLUDING BUT NOT LIMITED TO INCIDENTAL, |
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| 23 | * SPECIAL, INDIRECT, PUNITIVE OR CONSEQUENTIAL DAMAGES, LOST PROFITS OR LOST DATA, |
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| 24 | * COST OF PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, OR ANY CLAIMS BY THIRD PARTIES |
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| 25 | * (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF), OR OTHER SIMILAR COSTS. |
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| 26 | * The aggregate and cumulative liability of Microchip and its licensors for damages related to the use of the software |
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| 27 | * will in no event exceed $1000 or the amount you paid Microchip for the software, whichever is greater. |
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| 28 | |||
| 29 | * MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE OF THESE TERMS AND |
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| 30 | * THE TERMS OF THE ACCOMPANYING CLICK-WRAP SOFTWARE LICENSE. |
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| 31 | * |
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| 32 | * |
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| 33 | * Author Date Comment |
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| 34 | *~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 35 | * Naveen. M 14 Apr 2009 Version 1.0 Initial Draft |
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| 36 | * Sasha. M / Naveen. M 4 May 2009 Version 1.0 Initial Draft |
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| 37 | * Sasha. M / Naveen. M 11 Nov 2009 Version 1.0 Release |
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| 38 | * Sasha. M / Nithin. 10 April 2010 Version 1.20 Release |
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| 39 | *****************************************************************************/ |
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| 40 | #ifndef _MTOUCH_PIC24_CTMU_PHYSICAL_H |
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| 41 | #define _MTOUCH_PIC24_CTMU_PHYSICAL_H |
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| 42 | |||
| 43 | /* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */ |
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| 44 | /* ~~~~~~~~~~~~~~~~~~~~~ Includes ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */ |
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| 45 | /* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */ |
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| 46 | #include "Config.h" |
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| 47 | #include "HardwareProfile.h" |
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| 48 | #include "mTouchCap_Timers.h" |
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| 49 | #include "mTouchCap_Adc.h" |
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| 50 | #include "GenericTypeDefs.h" |
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| 51 | |||
| 52 | #ifdef __PIC24F__ |
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| 53 | |||
| 54 | /* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */ |
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| 55 | /* ~~~~~~~~~~~~~~~~~~~~~ Constants ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */ |
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| 56 | /* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */ |
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| 57 | |||
| 58 | |||
| 59 | /***********************************************************************/ |
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| 60 | /* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */ |
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| 61 | /* ~~~~~~~~~~~~~~~~~~~~~ Variables ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */ |
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| 62 | /* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */ |
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| 63 | |||
| 64 | |||
| 65 | /* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */ |
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| 66 | /* ~~~~~~~~~~~~~~~~~~~~~ Externs ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */ |
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| 67 | /* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */ |
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| 68 | extern WORD curBigData [MAX_ADC_CHANNELS]; |
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| 69 | extern WORD curRawData [MAX_ADC_CHANNELS]; //Storage for CTMU channel values |
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| 70 | extern WORD tripValue [MAX_ADC_CHANNELS]; //Storage for the trip point for each channel |
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| 71 | extern WORD hystValue [MAX_ADC_CHANNELS]; //Storage for the hysterisis value for each channel |
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| 72 | extern WORD pressedCount [MAX_ADC_CHANNELS]; //Storage for count of pressed value for each channel |
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| 73 | extern WORD unpressedCount [MAX_ADC_CHANNELS]; //Storage for count of unpressed value for each channel |
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| 74 | extern WORD avg_delay [MAX_ADC_CHANNELS];//Storage for count for average update for each channel |
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| 75 | extern WORD averageData [MAX_ADC_CHANNELS]; // running average of CTMU channels |
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| 76 | extern WORD smallAvg [MAX_ADC_CHANNELS]; // current button smallavg |
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| 77 | extern WORD actualValue [MAX_ADC_CHANNELS]; // actual raw A/D counts for each channel |
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| 78 | extern WORD channel_TRIM_value [MAX_ADC_CHANNELS]; |
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| 79 | extern WORD channel_IRNG_value [MAX_ADC_CHANNELS]; |
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| 80 | extern BYTE chFilterType [MAX_ADC_CHANNELS]; // Channel filter type |
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| 81 | extern BYTE chDecodeMethod [MAX_ADC_CHANNELS]; // decode method type |
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| 82 | extern BYTE Press_State [MAX_ADC_CHANNELS]; |
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| 83 | extern SHORT startupCount; // variable to 'discard' first N samples |
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| 84 | extern SHORT loopCount; |
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| 85 | extern WORD immediateValue; // current button value |
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| 86 | extern WORD scaledBigValue; // current button bigval |
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| 87 | |||
| 88 | /* array for different analog channels */ |
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| 89 | extern WORD channelIndex[MAX_ADC_CHANNELS]; |
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| 90 | extern BYTE Channel_Pressed_Status[MAX_ADC_CHANNELS]; |
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| 91 | /* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */ |
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| 92 | /* ~~~~~~~~~~~~~~~~~~~~~ Function Prototypes ~~~~~~~~~~~~~~~~~~~~~~~~~~ */ |
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| 93 | /* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */ |
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| 94 | void mTouchCapPhy_Init(void); |
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| 95 | void mTouchCapApp_PortSetup(void); |
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| 96 | void mTouchCapPhy_CTMUSetup(void); |
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| 97 | void mTouchCapPhy_AdcSetup(void); |
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| 98 | void mTouchCapPhy_ReadCTMU(WORD Index); |
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| 99 | void mTouchCapPhy_ChannelSetup(WORD ChannelNum); |
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| 100 | void mTouchCapPhy_InitCTMU(void); |
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| 101 | void mTouchCapPhy_ChargeTimeInit(void); |
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| 102 | void mTouchCapPhy_Init(void); |
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| 103 | void mTouchCapPhy_SequenceChannels(void); |
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| 104 | void mTouchCapPhy_SetupCurrentSourceRange(WORD CurrentSourceRange); |
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| 105 | void mTouchCapPhy_SetTrimValue( WORD TrimValue); |
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| 106 | void mTouchCapPhy_Discharge_Current (void); |
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| 107 | void mTouchCapPhy_Charge_Current (void); |
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| 108 | WORD mTouchCapPhy_Read_ADC(); |
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| 109 | void CTMU_Current_trim_config(int channel_no); |
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| 110 | void DynamicTripValueCalculation(WORD Index); |
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| 111 | void mTouchCapPhy_AverageData(WORD Index); |
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| 112 | void mTouchCapPhy_StablizeChannelData(void); |
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| 113 | /* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */ |
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| 114 | /* ~~~~~~~~~~~~~~~~~~~~~ Enums ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */ |
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| 115 | /* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */ |
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| 116 | |||
| 117 | /***********************************************************************/ |
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| 118 | /******************** End of PORTS *****************************************/ |
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| 119 | /***********************************************************************/ |
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| 120 | /***********************************************************************/ |
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| 121 | |||
| 122 | |||
| 123 | /***********************************************************************/ |
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| 124 | /********************ANALOG CHANNELS TRISBITS DEFINITION*****************************************/ |
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| 125 | /***********************************************************************/ |
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| 126 | #ifdef ADC_LEGACY |
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| 127 | |||
| 128 | #define DIGITAL 1 |
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| 129 | #define ANALOG 0 |
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| 130 | |||
| 131 | #define TRIS_CHANNEL_AN0 TRISBbits.TRISB0 |
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| 132 | #define TRIS_CHANNEL_AN1 TRISBbits.TRISB1 |
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| 133 | #define TRIS_CHANNEL_AN2 TRISBbits.TRISB2 |
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| 134 | #define TRIS_CHANNEL_AN3 TRISBbits.TRISB3 |
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| 135 | #define TRIS_CHANNEL_AN4 TRISBbits.TRISB4 |
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| 136 | #define TRIS_CHANNEL_AN5 TRISBbits.TRISB5 |
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| 137 | #define TRIS_CHANNEL_AN6 TRISBbits.TRISB6 |
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| 138 | #define TRIS_CHANNEL_AN7 TRISBbits.TRISB7 |
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| 139 | #define TRIS_CHANNEL_AN8 TRISBbits.TRISB8 |
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| 140 | #define TRIS_CHANNEL_AN9 TRISBbits.TRISB9 |
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| 141 | #define TRIS_CHANNEL_AN1O TRISBbits.TRISB10 |
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| 142 | #define TRIS_CHANNEL_AN11 TRISBbits.TRISB11 |
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| 143 | #define TRIS_CHANNEL_AN12 TRISBbits.TRISB12 |
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| 144 | #define TRIS_CHANNEL_AN13 TRISBbits.TRISB13 |
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| 145 | #define TRIS_CHANNEL_AN14 TRISBbits.TRISB14 |
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| 146 | #define TRIS_CHANNEL_AN15 TRISBbits.TRISB15 |
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| 147 | |||
| 148 | |||
| 149 | #define ADPCF_CHANNEL_AN0(Value) AD1PCFGbits.PCFG0 = Value; |
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| 150 | #define ADPCF_CHANNEL_AN1(Value) AD1PCFGbits.PCFG1 = Value; |
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| 151 | #define ADPCF_CHANNEL_AN2(Value) AD1PCFGbits.PCFG2 = Value; |
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| 152 | #define ADPCF_CHANNEL_AN3(Value) AD1PCFGbits.PCFG3 = Value; |
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| 153 | #define ADPCF_CHANNEL_AN4(Value) AD1PCFGbits.PCFG4 = Value; |
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| 154 | #define ADPCF_CHANNEL_AN5(Value) AD1PCFGbits.PCFG5 = Value; |
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| 155 | #define ADPCF_CHANNEL_AN6(Value) AD1PCFGbits.PCFG6 = Value; |
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| 156 | #define ADPCF_CHANNEL_AN7(Value) AD1PCFGbits.PCFG7 = Value; |
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| 157 | #define ADPCF_CHANNEL_AN8(Value) AD1PCFGbits.PCFG8 = Value; |
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| 158 | #define ADPCF_CHANNEL_AN9(Value) AD1PCFGbits.PCFG9 = Value; |
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| 159 | #define ADPCF_CHANNEL_AN10(Value) AD1PCFGbits.PCFG10 = Value; |
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| 160 | #define ADPCF_CHANNEL_AN11(Value) AD1PCFGbits.PCFG11 = Value; |
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| 161 | #define ADPCF_CHANNEL_AN12(Value) AD1PCFGbits.PCFG12 = Value; |
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| 162 | #define ADPCF_CHANNEL_AN13(Value) AD1PCFGbits.PCFG13 = Value; |
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| 163 | #define ADPCF_CHANNEL_AN14(Value) AD1PCFGbits.PCFG14 = Value; |
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| 164 | #define ADPCF_CHANNEL_AN15(Value) AD1PCFGbits.PCFG15 = Value; |
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| 165 | |||
| 166 | #endif |
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| 167 | |||
| 168 | |||
| 169 | #ifdef ADC_NEW |
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| 170 | |||
| 171 | #define DIGITAL 0 |
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| 172 | #define ANALOG 1 |
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| 173 | |||
| 174 | #define TRIS_CHANNEL_AN0 TRISBbits.TRISB0 |
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| 175 | #define TRIS_CHANNEL_AN1 TRISBbits.TRISB1 |
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| 176 | #define TRIS_CHANNEL_AN2 TRISBbits.TRISB2 |
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| 177 | #define TRIS_CHANNEL_AN3 TRISBbits.TRISB3 |
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| 178 | #define TRIS_CHANNEL_AN4 TRISBbits.TRISB4 |
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| 179 | #define TRIS_CHANNEL_AN5 TRISBbits.TRISB5 |
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| 180 | #define TRIS_CHANNEL_AN6 TRISBbits.TRISB6 |
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| 181 | #define TRIS_CHANNEL_AN7 TRISBbits.TRISB7 |
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| 182 | #define TRIS_CHANNEL_AN8 TRISBbits.TRISB8 |
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| 183 | #define TRIS_CHANNEL_AN9 TRISBbits.TRISB9 |
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| 184 | #define TRIS_CHANNEL_AN1O TRISBbits.TRISB10 |
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| 185 | #define TRIS_CHANNEL_AN11 TRISBbits.TRISB11 |
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| 186 | #define TRIS_CHANNEL_AN12 TRISBbits.TRISB12 |
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| 187 | #define TRIS_CHANNEL_AN13 TRISBbits.TRISB13 |
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| 188 | #define TRIS_CHANNEL_AN14 TRISBbits.TRISB14 |
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| 189 | #define TRIS_CHANNEL_AN15 TRISBbits.TRISB15 |
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| 190 | #define TRIS_CHANNEL_AN16 TRISCbits.TRISC4 |
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| 191 | #define TRIS_CHANNEL_AN17 TRISGbits.TRISG6 |
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| 192 | #define TRIS_CHANNEL_AN18 TRISGbits.TRISG7 |
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| 193 | #define TRIS_CHANNEL_AN19 TRISGbits.TRISG8 |
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| 194 | #define TRIS_CHANNEL_AN20 TRISGbits.TRISG9 |
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| 195 | #define TRIS_CHANNEL_AN21 TRISEbits.TRISE9 |
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| 196 | #define TRIS_CHANNEL_AN22 TRISAbits.TRISA7 |
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| 197 | #define TRIS_CHANNEL_AN23 TRISAbits.TRISA6 |
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| 198 | |||
| 199 | |||
| 200 | |||
| 201 | #define ADPCF_CHANNEL_AN0(Value) ANSBbits.ANSB0 = Value; |
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| 202 | #define ADPCF_CHANNEL_AN1(Value) ANSBbits.ANSB1 = Value; |
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| 203 | #define ADPCF_CHANNEL_AN2(Value) ANSBbits.ANSB2 = Value; |
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| 204 | #define ADPCF_CHANNEL_AN3(Value) ANSBbits.ANSB3 = Value; |
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| 205 | #define ADPCF_CHANNEL_AN4(Value) ANSBbits.ANSB4 = Value; |
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| 206 | #define ADPCF_CHANNEL_AN5(Value) ANSBbits.ANSB5 = Value; |
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| 207 | #define ADPCF_CHANNEL_AN6(Value) ANSBbits.ANSB6 = Value; |
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| 208 | #define ADPCF_CHANNEL_AN7(Value) ANSBbits.ANSB7 = Value; |
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| 209 | #define ADPCF_CHANNEL_AN8(Value) ANSBbits.ANSB8 = Value; |
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| 210 | #define ADPCF_CHANNEL_AN9(Value) ANSBbits.ANSB9 = Value; |
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| 211 | #define ADPCF_CHANNEL_AN10(Value) ANSBbits.ANSB10 = Value; |
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| 212 | #define ADPCF_CHANNEL_AN11(Value) ANSBbits.ANSB11= Value; |
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| 213 | #define ADPCF_CHANNEL_AN12(Value) ANSBbits.ANSB12= Value; |
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| 214 | #define ADPCF_CHANNEL_AN13(Value) ANSBbits.ANSB13= Value; |
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| 215 | #define ADPCF_CHANNEL_AN14(Value) ANSBbits.ANSB14= Value; |
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| 216 | #define ADPCF_CHANNEL_AN15(Value) ANSBbits.ANSB15= Value; |
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| 217 | |||
| 218 | #define ADPCF_CHANNEL_AN16(Value) ANSCbits.ANSC4 = Value; |
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| 219 | #define ADPCF_CHANNEL_AN17(Value) ANSGbits.ANSG6 = Value; |
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| 220 | #define ADPCF_CHANNEL_AN18(Value) ANSGbits.ANSG7 = Value; |
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| 221 | #define ADPCF_CHANNEL_AN19(Value) ANSGbits.ANSG8 = Value; |
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| 222 | |||
| 223 | #define ADPCF_CHANNEL_AN20(Value) ANSGbits.ANSG9 = Value; |
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| 224 | #define ADPCF_CHANNEL_AN21(Value) ANSEbits.ANSE9 = Value; |
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| 225 | #define ADPCF_CHANNEL_AN22(Value) ANSAbits.ANSA7 = Value; |
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| 226 | #define ADPCF_CHANNEL_AN23(Value) ANSAbits.ANSA6 = Value; |
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| 227 | |||
| 228 | #endif |
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| 229 | |||
| 230 | |||
| 231 | /***********************************************************************/ |
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| 232 | /********************A D C*****************************************/ |
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| 233 | /***********************************************************************/ |
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| 234 | /***********************************************************************/ |
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| 235 | #define INIT_AD1PCFGL_VALUE 0x0000 |
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| 236 | #define INIT_AD1CON1_VALUE 0x0000 |
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| 237 | #define INIT_AD1CHS_VALUE 0x0000 //select the analog channel 0 |
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| 238 | |||
| 239 | /*********************************************************************** |
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| 240 | Macro : EnableIntADC1 |
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| 241 | Overview : This macro enables the ADC interrupt. |
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| 242 | Parameters : None |
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| 243 | Remarks : This macro sets ADC Interrupt Enable bit of Interrupt |
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| 244 | Enable Control Register. |
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| 245 | ************************************************************************/ |
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| 246 | #define EnableIntADC1 (IEC0bits.AD1IE = 1) |
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| 247 | |||
| 248 | /*********************************************************************** |
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| 249 | Macro : DisableIntADC1 |
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| 250 | Overview : This macro disables the ADC interrupt. |
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| 251 | Parameters : None |
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| 252 | Remarks : This macro clears ADC Interrupt Enable bit of Interrupt |
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| 253 | Enable Control register. |
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| 254 | ************************************************************************/ |
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| 255 | #define DisableIntADC1 (IEC0bits.AD1IE = 0) |
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| 256 | |||
| 257 | /*********************************************************************** |
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| 258 | Macro : SetPriorityIntADC1(priority) |
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| 259 | Overview : This macro sets priority for ADC interrupt. |
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| 260 | Parameters : priority - This input parameter is the level of interrupt priority |
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| 261 | Remarks : This macro sets ADC Interrupt Priority bits of Interrupt |
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| 262 | Priority Control register. |
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| 263 | ************************************************************************/ |
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| 264 | #define SetPriorityIntADC1(priority) (IPC3bits.AD1IP = priority) |
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| 265 | |||
| 266 | /******************************************************************* |
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| 267 | Macro : ADC1_Clear_Intr_Status_Bit |
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| 268 | Overview : Macro to Clear ADC Interrupt Status bit |
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| 269 | Parameters : None |
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| 270 | Remarks : None |
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| 271 | *******************************************************************/ |
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| 272 | #define ADC1_Clear_Intr_Status_Bit (IFS0bits.AD1IF = 0) |
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| 273 | |||
| 274 | /******************************************************************* |
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| 275 | Macro : ADC1_IF_Bit |
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| 276 | Overview : returns ADC1 Interrupt Flag |
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| 277 | Parameters : None |
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| 278 | Remarks : None |
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| 279 | *******************************************************************/ |
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| 280 | #define ADC1_IF_Bit (IFS0bits.AD1IF) |
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| 281 | |||
| 282 | |||
| 283 | /************************************************************************ |
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| 284 | Macro : BusySampADC1 |
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| 285 | Overview : This function is identical to ConvertADC10 |
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| 286 | Parameters : None |
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| 287 | Remarks : This macro clears the ADCON1<SAMP> bit and thus stops sampling |
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| 288 | and starts conversion. |
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| 289 | **************************************************************************/ |
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| 290 | #define BusySampADC1 !(AD1CON1bits.SAMP) |
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| 291 | |||
| 292 | /************************************************************************ |
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| 293 | Macro : EnableADC1 |
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| 294 | Overview : This function enables the ADC module |
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| 295 | Parameters : None |
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| 296 | Remarks : None. |
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| 297 | **************************************************************************/ |
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| 298 | #define EnableADC1 (AD1CON1bits.ADON = 1) |
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| 299 | |||
| 300 | /************************************************************************ |
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| 301 | Macro : DisableADC1 |
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| 302 | Overview : This function disables the ADC module |
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| 303 | Parameters : None |
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| 304 | Remarks : None. |
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| 305 | **************************************************************************/ |
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| 306 | #define DisableADC1 (AD1CON1bits.ADON = 0) |
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| 307 | |||
| 308 | /************************************************************************ |
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| 309 | Macro : Set_Adc_Enable_State |
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| 310 | Overview : This function enables or disable the ADC module depending upon the value. |
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| 311 | Parameters : None |
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| 312 | Remarks : None. |
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| 313 | **************************************************************************/ |
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| 314 | #define Set_Adc_Enable_State(Value) (AD1CON1bits.ADON = Value) |
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| 315 | |||
| 316 | |||
| 317 | /************************************************************************ |
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| 318 | Macro : Enable_ADC_Sampling |
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| 319 | Overview : This function starts the A/D conversion. |
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| 320 | Parameters : None |
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| 321 | Remarks : None. |
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| 322 | **************************************************************************/ |
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| 323 | #define Enable_ADC_Sampling (AD1CON1bits.SAMP = 1) |
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| 324 | |||
| 325 | |||
| 326 | /************************************************************************ |
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| 327 | Macro : Disable_ADC_Sampling |
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| 328 | Overview : This function starts the A/D conversion. |
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| 329 | Parameters : None |
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| 330 | Remarks : None. |
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| 331 | **************************************************************************/ |
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| 332 | #define Disable_ADC_Sampling (AD1CON1bits.SAMP = 0) |
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| 333 | |||
| 334 | /************************************************************************ |
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| 335 | Macro : ADC_Done_Bit |
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| 336 | Overview : This function declares the AD1CON1bits.DONE. |
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| 337 | Parameters : None |
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| 338 | Remarks : None. |
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| 339 | **************************************************************************/ |
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| 340 | #define ADC_Done_Bit (AD1CON1bits.DONE) |
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| 341 | |||
| 342 | /************************************************************************ |
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| 343 | Macro : Adc_Port_Configuration |
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| 344 | Overview : Configure ADC Port pin as Analog or Digital |
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| 345 | Parameters : None |
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| 346 | Remarks : None. |
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| 347 | **************************************************************************/ |
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| 348 | #ifdef ADC_LEGACY |
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| 349 | #define Adc_Port_Configuration(Value) (AD1PCFGL = Value) |
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| 350 | #endif |
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| 351 | |||
| 352 | #ifdef ADC_NEW |
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| 353 | #define Adc_PortA_Configuration(Value) (ANSA = Value) |
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| 354 | #define Adc_PortB_Configuration(Value) (ANSB = Value) |
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| 355 | #define Adc_PortC_Configuration(Value) (ANSC = Value) |
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| 356 | #define Adc_PortD_Configuration(Value) (ANSD = Value) |
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| 357 | #define Adc_PortE_Configuration(Value) (ANSE = Value) |
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| 358 | #define Adc_PortF_Configuration(Value) (ANSF = Value) |
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| 359 | #define Adc_PortG_Configuration(Value) (ANSG = Value) |
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| 360 | #endif |
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| 361 | |||
| 362 | /************************************************************************ |
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| 363 | |||
| 364 | Redefining ADC Register |
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| 365 | |||
| 366 | **************************************************************************/ |
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| 367 | #define ADC_CHANNEL_SELECT AD1CHS |
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| 368 | #define ADCSSL AD1CSSL |
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| 369 | #define ADCON3 AD1CON3 |
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| 370 | #define ADCON2 AD1CON2 |
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| 371 | #define ADCON1 AD1CON1 |
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| 372 | #define ADCBUF ADC1BUF0 |
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| 373 | |||
| 374 | |||
| 375 | /*Registers Defaults*/ |
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| 376 | #define ADCSSL_VAL 0x0000 |
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| 377 | #define ADCON3_VAL 0x0000 |
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| 378 | #define ADCON2_VAL 0x0000 |
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| 379 | #define ADCON1_VAL 0x0000 |
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| 380 | #define ADC_PRIORITY 0x00 |
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| 381 | #define ADC_PORT_CONFIG_DEFAULT_VALUE 0x0000 // Default Value of ADC Port Configuration Register. |
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| 382 | |||
| 383 | #define ADC_PORTA_CONFIG_DEFAULT_VALUE 0x00C0 // Default Value of ADC Port Configuration Register. |
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| 384 | #define ADC_PORTB_CONFIG_DEFAULT_VALUE 0xFFFF |
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| 385 | #define ADC_PORTC_CONFIG_DEFAULT_VALUE 0x0010 |
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| 386 | #define ADC_PORTE_CONFIG_DEFAULT_VALUE 0x0200 |
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| 387 | #define ADC_PORTG_CONFIG_DEFAULT_VALUE 0x03C0 |
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| 388 | |||
| 389 | |||
| 390 | /*AD1CON1 register definition*/ |
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| 391 | #define ADC_MODULE_ON 0x8000 /* A/D Converter on */ |
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| 392 | #define ADC_MODULE_OFF 0x0000 /* A/D Converter off */ |
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| 393 | #define ADC_MODULE_MASK (~ADC_MODULE_ON) /* A/D Converter mask*/ |
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| 394 | #define ADC_IDLE_CONTINUE 0x0000 /* A/D Operate in Idle mode */ |
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| 395 | #define ADC_IDLE_STOP 0x2000 /* A/D Stop in Idle mode */ |
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| 396 | #define ADC_IDLE_MASK (~ADC_IDLE_CONTINUE) /* A/D Idle mode mask */ |
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| 397 | #define ADC_FORMAT_SIGN_FRACT 0x0300 /* A/D data format signed fractional */ |
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| 398 | #define ADC_FORMAT_FRACT 0x0200 /* A/D data format fractional */ |
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| 399 | #define ADC_FORMAT_SIGN_INT 0x0100 /* A/D data format signed integer */ |
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| 400 | #define ADC_FORMAT_INTG 0x0000 /* A/D data format integer */ |
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| 401 | #define ADC_FORMAT_MASK (~ADC_FORMAT_SIGN_FRACT)/* A/D format mask */ |
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| 402 | #define ADC_CLK_AUTO 0x00E0 /* Internal counter ends sampling and starts conversion (Auto convert) */ |
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| 403 | #define ADC_CLK_CTMU 0x0080 /* CTMU event ends sampling and starts conversion */ |
||
| 404 | #define ADC_CLK_TMR5 0x0060 /* Timer5 compare ends sampling and starts conversion */ |
||
| 405 | #define ADC_CLK_TMR3 0x0040 /* Timer3 compare ends sampling and starts conversion */ |
||
| 406 | #define ADC_CLK_INT0 0x0020 /* Active transition on INT0 ends sampling and starts conversion */ |
||
| 407 | #define ADC_CLK_MANUAL 0x0000 /* Clearing sample (SAMP) bit ends sampling and starts conversion */ |
||
| 408 | #define ADC_CLK_MASK (~ADC_CLK_AUTO) /* A/D clock mask */ |
||
| 409 | #define ADC_AUTO_SAMPLING_ON 0x0004 /* Sampling begins immediately after last conversion */ |
||
| 410 | #define ADC_AUTO_SAMPLING_OFF 0x0000 /* Sampling begins when SAMP bit is set */ |
||
| 411 | #define ADC_AUTO_SAMPLING_MASK (~ADC_AUTO_SAMPLING_ON) /* A/D auto sampling mask */ |
||
| 412 | #define ADC_SAMP_ON 0x0002 /* sample / hold amplifiers are sampling */ |
||
| 413 | #define ADC_SAMP_OFF 0x0000 /* sample / hold amplifiers are holding */ |
||
| 414 | #define ADC_SAMP_MASK (~ADC_SAMP_ON) /* A/D sampling mask */ |
||
| 415 | |||
| 416 | /*AD1CON2 control register definition*/ |
||
| 417 | #define ADC_VREF_EXT_AVSS 0x2000 /* A/D Voltage reference configuration Vref+ external and Vref- is AVss */ |
||
| 418 | #define ADC_VREF_AVDD_EXT 0x4000 /* A/D Voltage reference configuration Vref+ AVdd and Vref- external */ |
||
| 419 | #define ADC_VREF_EXT_EXT 0x6000 /* A/D Voltage reference configuration both Vref+ and Vref- are external */ |
||
| 420 | #define ADC_VREF_AVDD_AVSS 0x8000 /* A/D Voltage reference configuration Vref+ is AVdd and Vref- is AVss */ |
||
| 421 | #define ADC_VREF_MASK (~(ADC_VREF_AVDD_AVSS | ADC_VREF_EXT_EXT)) /* A/D Vref mask */ |
||
| 422 | #define ADC_SCAN_ON 0x0400 /* A/D Scan Input Selections for CH0 during SAMPLE A */ |
||
| 423 | #define ADC_SCAN_OFF 0x0000 /* A/D Do notScan Input Selections for CH0+ during SAMPLE A */ |
||
| 424 | #define ADC_SCAN_ON_OFF_MASK (~ADC_SCAN_ON) /* A/D scan input mask */ |
||
| 425 | |||
| 426 | #define ADC_INTR_CONV 0x0000 /* Interrupts at the completion of conversion of 2 samples */ |
||
| 427 | |||
| 428 | #define ADC_ALT_BUF_ON 0x0002 /* Buffer configured as 2 8-word buffers */ |
||
| 429 | #define ADC_ALT_BUF_OFF 0x0000 /* Buffer configured as 1 16-word buffer */ |
||
| 430 | #define ADC_ALT_BUF_MASK (~ADC_ALT_BUF_ON) /* A/D alternate buffer mask */ |
||
| 431 | /* A/D Uses channel input selects for SAMPLE A on first sample and SAMPLE B on next sample */ |
||
| 432 | #define ADC_ALT_INPUT_ON 0x0001 /* alternate between MUXA and MUXB */ |
||
| 433 | /* A/D Always uses channel input selects for SAMPLE A */ |
||
| 434 | #define ADC_ALT_INPUT_OFF 0x0000 /* use MUXA only */ |
||
| 435 | #define ADC_ALT_MASK (~ADC_ALT_INPUT_ON) /* A/D alternate input mask */ |
||
| 436 | |||
| 437 | /*AD1CON3 register definition*/ |
||
| 438 | #define ADC_CONV_CLK_INTERNAL_RC 0x8000 /* A/D internal RC clock */ |
||
| 439 | #define ADC_CONV_CLK_SYSTEM 0x0000 /* Clock derived from system clock */ |
||
| 440 | #define ADC_CONV_CLK_SOURCE_MASK (~ADC_CONV_CLK_INTERNAL_RC) /* A/D conversion clock mask */ |
||
| 441 | |||
| 442 | #define ADC_SAMPLE_TIME 0x0000 /* A/D Auto Sample Time 0 Tad */ |
||
| 443 | #define ADC_CONV_CLK_Tcy 0x0000 /* A/D Conversion Clock is 1*Tcy */ |
||
| 444 | |||
| 445 | /*AD1CSSL control register definition*/ |
||
| 446 | #define ADC_SCAN_AN 0x0000 /*Enable Input Scan AN0 */ |
||
| 447 | |||
| 448 | |||
| 449 | #define ADC_CONFIG_ADCON1 (ADCON1_VAL | ADC_MODULE_OFF | ADC_IDLE_CONTINUE | ADC_FORMAT_INTG | ADC_CLK_MANUAL | ADC_AUTO_SAMPLING_OFF | ADC_SAMP_OFF) |
||
| 450 | #define ADC_CONFIG_ADCON2 (ADCON2_VAL | ADC_VREF_AVDD_AVSS | ADC_SCAN_OFF | ADC_INTR_CONV | ADC_ALT_BUF_OFF | ADC_ALT_INPUT_OFF) |
||
| 451 | #define ADC_CONFIG_ADCON3 (ADCON3_VAL | ADC_CONV_CLK_INTERNAL_RC | ADC_SAMPLE_TIME | ADC_CONV_CLK_Tcy) |
||
| 452 | #define ADC_CONFIG_ADCSSL (ADCSSL_VAL | ADC_SCAN_AN) |
||
| 453 | |||
| 454 | |||
| 455 | /***********************************************************************/ |
||
| 456 | /********************C O M P A R A T O R********************************/ |
||
| 457 | /***********************************************************************/ |
||
| 458 | /***********************************************************************/ |
||
| 459 | /*Comparator register definition*/ |
||
| 460 | #define CMP_CMCON CM2CON |
||
| 461 | #define CMP_CVRCON CVRCON |
||
| 462 | |||
| 463 | /*CMCON control register bit definition*/ |
||
| 464 | #define CMP_Enable_Disable_Bit CM2CONbits.CON |
||
| 465 | #define CMP_Output_Enable_Disable_Bit CM2CONbits.COE |
||
| 466 | #define CMP_Output_Polarity_Bit CM2CONbits.CPOL |
||
| 467 | #define CMP_Event_Bit CM2CONbits.CEVT |
||
| 468 | #define CMP_CMCON_Ouput_Bit CM2CONbits.COUT |
||
| 469 | #define CMP_Trigger_Select_HighBit CM2CONbits.EVPOL1 |
||
| 470 | #define CMP_Trigger_Select_LowBit CM2CONbits.EVPOL0 |
||
| 471 | #define CMP_Reference_Select_Bit CM2CONbits.CREF |
||
| 472 | #define CMP_Channel_Select_HighBit CM2CONbits.CCH1 |
||
| 473 | #define CMP_Channel_Select_LowBit CM2CONbits.CCH0 |
||
| 474 | #define CMP_Trigger_Select_Bits CM2CONbits.EVPOL |
||
| 475 | #define CMP_Channel_Select_Bits CM2CONbits.CCH |
||
| 476 | |||
| 477 | /*CMSTAT register bit definition*/ |
||
| 478 | #define CMP_Ouput_Bit CMSTATbits.C2OUT |
||
| 479 | |||
| 480 | /*CMCON interrupt register bit definition*/ |
||
| 481 | |||
| 482 | #define CMP_Interrupt_Flag_Bit IFS1bits.CMIF |
||
| 483 | #define CMP_Interrupt_Enable_Bit IEC1bits.CMIE |
||
| 484 | #define CMP_Interrupt_Priority_Bits IPC4bits.CMIP |
||
| 485 | |||
| 486 | /****************************************************************************** |
||
| 487 | Macro : CMP_EnblDsbl(state) |
||
| 488 | Overview : Macro Enables/Disables the Comparator |
||
| 489 | Parameter : state - *1 Comparator is enabled |
||
| 490 | *0 Comparator is disabled |
||
| 491 | Remarks : None |
||
| 492 | *****************************************************************************/ |
||
| 493 | #define CMP_EnblDsbl(state) (CMP_Enable_Disable_Bit = state) |
||
| 494 | |||
| 495 | /****************************************************************************** |
||
| 496 | Macro : CMP_Output_EnblDsbl(state) |
||
| 497 | Overview : Macro Enables/Disables Comparator output on the output pad |
||
| 498 | Parameter : state - *1 Comparator output driven on the output pad |
||
| 499 | *0 Comparator output is not driven on the output pad |
||
| 500 | Remarks : None |
||
| 501 | *****************************************************************************/ |
||
| 502 | #define CMP_Output_EnblDsbl(state) (CMP_Output_Enable_Disable_Bit = state) |
||
| 503 | |||
| 504 | /****************************************************************************** |
||
| 505 | Macro : CMP_Output_Polarity(state) |
||
| 506 | Overview : |
||
| 507 | Parameter : state - *1 |
||
| 508 | *0 |
||
| 509 | Remarks : None |
||
| 510 | *****************************************************************************/ |
||
| 511 | #define CMP_Output_Polarity(state) (CMP_Output_Polarity_Bit = state) |
||
| 512 | |||
| 513 | |||
| 514 | /****************************************************************************** |
||
| 515 | Macro : CMP_Output_Polarity(state) |
||
| 516 | Overview : |
||
| 517 | Parameter : state - *1 |
||
| 518 | *0 |
||
| 519 | Remarks : None |
||
| 520 | *****************************************************************************/ |
||
| 521 | #define CMP_Event(state) (CMP_Event_Bit = state) |
||
| 522 | |||
| 523 | |||
| 524 | /****************************************************************************** |
||
| 525 | Macro : CMP_Trigger_Select(state) |
||
| 526 | Overview : |
||
| 527 | Parameter : state - *1 |
||
| 528 | *0 |
||
| 529 | Remarks : None |
||
| 530 | *****************************************************************************/ |
||
| 531 | #define CMP_Trigger_Select(state) (CMP_Trigger_Select_Bits = state) |
||
| 532 | |||
| 533 | |||
| 534 | /****************************************************************************** |
||
| 535 | Macro : CMP_Trigger_Select(state) |
||
| 536 | Overview : |
||
| 537 | Parameter : state - *1 |
||
| 538 | *0 |
||
| 539 | Remarks : None |
||
| 540 | *****************************************************************************/ |
||
| 541 | #define CMP_Reference_Select(state) (CMP_Reference_Select_Bit = state) |
||
| 542 | |||
| 543 | |||
| 544 | /****************************************************************************** |
||
| 545 | Macro : CMP_Channel_Select(state) //n1: |
||
| 546 | Overview : |
||
| 547 | Parameter : state - *1 |
||
| 548 | *0 |
||
| 549 | Remarks : None |
||
| 550 | *****************************************************************************/ |
||
| 551 | #define CMP_Channel_Select(state) (CMP_Channel_Select_Bits = state) |
||
| 552 | |||
| 553 | /****************************************************************************** |
||
| 554 | Macro : CMP_Get_STATE() |
||
| 555 | Overview : Macro Returns state of Comparator output |
||
| 556 | When C2INV = 0: |
||
| 557 | 1 = C2 VIN+ > C2 VIN- |
||
| 558 | |||
| 559 | When C2INV = 1: |
||
| 560 | |||
| 561 | 1 = C2 VIN+ < C2 VIN- |
||
| 562 | Parameter : None |
||
| 563 | Remarks : State of Comparator depends on Inverse selection bit in |
||
| 564 | control register |
||
| 565 | *****************************************************************************/ |
||
| 566 | #define CMP_Get_STATE() (CMP_Ouput_Bit) |
||
| 567 | |||
| 568 | /*********************************************************************** |
||
| 569 | Macro : EnableIntCMP |
||
| 570 | Overview : This macro enables the comparator interrupt. |
||
| 571 | Parameter : None |
||
| 572 | Remarks : This macro sets comparator Interrupt Enable bit of Interrupt |
||
| 573 | Enable Control Register. |
||
| 574 | ************************************************************************/ |
||
| 575 | #define EnableIntCMP (CMP_Interrupt_Enable_Bit = 1) |
||
| 576 | |||
| 577 | /*********************************************************************** |
||
| 578 | Macro : DisableIntCMP |
||
| 579 | Overview : This macro disables the comparator interrupt. |
||
| 580 | Parameter : None |
||
| 581 | Remarks : This macro clears comparator Interrupt Enable bit of Interrupt |
||
| 582 | Enable Control register. |
||
| 583 | ************************************************************************/ |
||
| 584 | #define DisableIntCMP (CMP_Interrupt_Enable_Bit = 0) |
||
| 585 | |||
| 586 | /*********************************************************************** |
||
| 587 | Macro : SetPriorityIntCMP (priority) |
||
| 588 | Overview : This macro sets priority for comparator interrupt. |
||
| 589 | Parameter : priority - This input parameter is the level of interrupt priority |
||
| 590 | Remarks : This macro sets comparator Interrupt Priority bits of Interrupt |
||
| 591 | Priority Control register. |
||
| 592 | ************************************************************************/ |
||
| 593 | #define SetPriorityIntCMP(priority) (CMP_Interrupt_Priority_Bits = priority) |
||
| 594 | |||
| 595 | /******************************************************************* |
||
| 596 | Macro : CMP_Clear_Intr_Status_Bit |
||
| 597 | Overview : Macro to Clear Comparator Interrupt Status bit |
||
| 598 | Parameter : None |
||
| 599 | Remarks : None |
||
| 600 | *******************************************************************/ |
||
| 601 | #define CMP_Clear_Intr_Status_Bit (CMP_Interrupt_Flag_Bit = 0) |
||
| 602 | |||
| 603 | |||
| 604 | /*CMxCON register definition*/ |
||
| 605 | #define CMP_ENABLE 0x8000 /* Comparator is enabled */ |
||
| 606 | #define CMP_DISABLE 0x0000 /* Comparator is disabled */ |
||
| 607 | #define CMP_ENBL_DSBL_MASK (~CMP_ENABLE) |
||
| 608 | #define CMP_OUTPUT_ENABLE 0x4000 /* Comparator output present on the CXOUT pin */ |
||
| 609 | #define CMP_OUTPUT_DISABLE 0x0000 /* Comparator output is internal only */ |
||
| 610 | #define CMP_OUTPUT_MASK (~CMP_OUTPUT_ENABLE) |
||
| 611 | #define CMP_OUTPUT_INVERT 0x2000 /* Comparator output inverted */ |
||
| 612 | #define CMP_OUTPUT_NOT_INVERT 0x0000 /* Comparator output not inverted */ |
||
| 613 | #define CMP_OUTPUT_INVERT_MASK (~CMP_OUTPUT_INVERT) |
||
| 614 | #define CMP_CHANGE_STATE 0x0200 /* Comparator output changed states */ |
||
| 615 | #define CMP_NO_CHANGE 0x0000 /* Comparator output did not change states */ |
||
| 616 | #define CMP_STATE_MASK (~CMP_CHANGE_STATE ) |
||
| 617 | #define CMP_INTERRUPT_ON_ANY_EDGE 0X00C0 /* Comparator interrupt generated on any edge of the selected comparator output*/ |
||
| 618 | #define CMP_INTERRUPT_ON_FALLING_EDGE 0X0080 /* Comparator interrupt generated only on falling edge of the selected comparator output*/ |
||
| 619 | #define CMP_INTERRUPT_ON_RISING_EDGE 0X0040 /* Comparator interrupt generated only on rising edge of the selected comparator output*/ |
||
| 620 | #define CMP_INTERRUPT_DISABLED 0X0000 /* Comparator interrupt generation is disabled */ |
||
| 621 | #define CMP_INTERRUP_EDGE_MASK (~CMP_INTERRUPT_ON_ANY_EDGE) |
||
| 622 | #define CMP_POS_IP_CV_Ref 0x0010 /* Input is connected to internal CVref voltage */ |
||
| 623 | #define CMP_POS_IP_CXINA 0x0000 /* Input is connected to CXINA pin */ |
||
| 624 | #define CMP_POS_IP_MASK (~CMP_POS_IP_CV_Ref) |
||
| 625 | #define CMP_NEG_IP_CXINB 0X0000 /* Input is connected to CXINB pin */ |
||
| 626 | #define CMP_NEG_IP_CXINC 0X0001 /* Input is connected to CXINC pin */ |
||
| 627 | #define CMP_NEG_IP_CXIND 0X0002 /* Input is connected to CXIND pin */ |
||
| 628 | |||
| 629 | /*CVRCON register definition*/ |
||
| 630 | #define CMP_VRef_Enable 0x0080 /* CVREF circuit powered on */ |
||
| 631 | #define CMP_VRef_Disable 0x0000 /* CVREF circuit powered down */ |
||
| 632 | #define CMP_VRef_MASK (~CMP_VRef_Enable) |
||
| 633 | #define CMP_VRef_OUTPUT_Enable 0x0040 /* CVREF voltage level is output on CVREF pin */ |
||
| 634 | #define CMP_VRef_OUTPUT_Disable 0x0000 /* CVREF voltage level is disconnected from CVREF pin */ |
||
| 635 | #define CMP_VRef_OUTPUT_MASK (~CMP_VRef_OUTPUT_Enable) |
||
| 636 | #define CMP_VRef_SELECT_24_STEPS 0x0020 /* 0 to 0.67 CVRSRC, with CVRSRC/24 step size */ |
||
| 637 | #define CMP_VRef_SELECT_32_STEPS 0x0000 /* 0.25 CVRSRC to 0.75 CVRSRC, with CVRSRC/32 step size */ |
||
| 638 | #define CMP_VRef_STEP_SELECT_MASK (~CMP_VRef_SELECT_24_STEPS) |
||
| 639 | #define CMP_Vrsrc_Vref_Vref 0x0010 /* Comparator reference source CVRSRC = VREF+ VREF- */ |
||
| 640 | #define CMP_Vrsrc_AVDD_AVSS 0x0000 /* Comparator reference source CVRSRC = AVDD AVSS */ |
||
| 641 | #define CMP_Vrsrc_MASK (~CMP_Vrsrc_Vref_Vref) |
||
| 642 | #define CMP_CVrsrc 0x000F /* 0 CVRSRC with CVRSRC/24 step size, 0.25 CVRSRC with CVRSRC/32 step size */ |
||
| 643 | |||
| 644 | /*Registers Defaults*/ |
||
| 645 | #define CMP_CMCON_VAL 0x0000 |
||
| 646 | #define CVREF_VAL 0x0000 |
||
| 647 | |||
| 648 | |||
| 649 | #define CMP_CONFIG_CMCON (CMP_CMCON_VAL | CMP_ENABLE | CMP_OUTPUT_DISABLE | CMP_OUTPUT_NOT_INVERT \ |
||
| 650 | | CMP_NO_CHANGE | CMP_INTERRUPT_DISABLED | CMP_POS_IP_CV_Ref | CMP_NEG_IP_CXINB) |
||
| 651 | |||
| 652 | #define CMP_CONFIG_CVRCON (CVREF_VAL | CMP_VRef_Enable | CMP_VRef_OUTPUT_Enable | CMP_VRef_SELECT_32_STEPS \ |
||
| 653 | | CMP_Vrsrc_AVDD_AVSS | CMP_CVrsrc) |
||
| 654 | |||
| 655 | |||
| 656 | |||
| 657 | /***********************************************************************/ |
||
| 658 | /********************C T M U********************************************/ |
||
| 659 | /***********************************************************************/ |
||
| 660 | /************************************************************************/ |
||
| 661 | /*CTMUCON Control Register*/ |
||
| 662 | #define CTMU_ENABLE 0x8000 /*CTMU is Enabled*/ |
||
| 663 | #define CTMU_DISABLE 0x0000 /*CTMU is Disabled*/ |
||
| 664 | #define CTMU_ENBL_DISBL_MASK (~CTMU_ENABLE) |
||
| 665 | |||
| 666 | #define CTMU_IDLE_STOP 0x2000 /*CTMU discontinue module operation in Idle mode*/ |
||
| 667 | #define CTMU_IDLE_CONTINUE 0x0000 /*CTMU Operate in Idle mode*/ |
||
| 668 | #define CTMU_IDLE_MASK (~CTMU_IDLE_STOP) |
||
| 669 | |||
| 670 | #define CTMU_TIME_GEN_ENABLE 0x1000 /*CTMU enables edge delay generation*/ |
||
| 671 | #define CTMU_TIME_GEN_DISABLE 0x0000 /*CTMU disables edge delay generation*/ |
||
| 672 | #define CTMU_TIME_GEN_MASK (~CTMU_TIME_GEN_ENABLE) |
||
| 673 | |||
| 674 | #define CTMU_EDGE_ENABLE 0x0800 /*CTMU edges are not blocked*/ |
||
| 675 | #define CTMU_EDGE_DISABLE 0x0000 /*CTMU edges are blocked*/ |
||
| 676 | #define CTMU_EDGE_MASK (~CTMU_EDGE_ENABLE) |
||
| 677 | |||
| 678 | #define CTMU_EDGE_SEQUENCE_ON 0x0400 /*Edge1 event must occur before edge2 event can occur*/ |
||
| 679 | #define CTMU_EDGE_SEQUENCE_OFF 0x0000 /*No edge sequence os needed*/ |
||
| 680 | #define CTMU_EDGE_SEQUENCE_MASK (~CTMU_EDGE_SEQUENCE) |
||
| 681 | |||
| 682 | #define CTMU_ANA_CURR_SOURCE_GND 0x0200 /*CTMU Analog current source output is grounded*/ |
||
| 683 | #define CTMU_ANA_CURR_SOURCE_NOT_GND 0x0000 /*CTMU Analog current source output is not grounded*/ |
||
| 684 | #define CTMU_ANA_CURR_SOURCE_MASK (~CTMU_ANA_CURR_SOURCE_GND) |
||
| 685 | |||
| 686 | #define CTMU_TRIG_OUTPUT_ENABLE 0x0100 /*Trigger output is enabled*/ |
||
| 687 | #define CTMU_TRIG_OUTPUT_DISABLE 0x0000 /*Trigger output is disabled*/ |
||
| 688 | #define CTMU_TRIG_OUTPUT_MASK (~CTMU_TRIG_OUTPUT) |
||
| 689 | |||
| 690 | #define CTMU_EDGE1_POLARITY_POS 0x0010 /*Edge 1 programmed for a positive edge response*/ |
||
| 691 | #define CTMU_EDGE1_POLARITY_NEG 0x0000 /*Edge 1 programmed for a negative edge response*/ |
||
| 692 | #define CTMU_EDGE1_POLARITY_MASK (~CTMU_EDGE2_POS_POLARITY) |
||
| 693 | |||
| 694 | #define CTMU_EDGE1_SOURCE_CTED1 0x000C /*CTED1 is a source select for Edge1*/ |
||
| 695 | #define CTMU_EDGE1_SOURCE_CTED2 0x0008 /*CTED2 is a source select for Edge1*/ |
||
| 696 | #define CTMU_EDGE1_SOURCE_OC1 0x0004 /*OC1 is a source select for Edge1*/ |
||
| 697 | #define CTMU_EDGE1_SOURCE_TIMER1 0x0000 /*TIMER1 is a source select for Edge1*/ |
||
| 698 | #define CTMU_EDGE1_SOURCE_MASK (~CTMU_EDGE2_SOURCE_CTED1) |
||
| 699 | |||
| 700 | #define CTMU_EDGE2_POLARITY_POS 0x0080 /*Edge 2 programmed for a positive edge response*/ |
||
| 701 | #define CTMU_EDGE2_POLARITY_NEG 0x0000 /*Edge 2 programmed for a negative edge response*/ |
||
| 702 | #define CTMU_EDGE2_POLARITY_MASK (~CTMU_EDGE2_POS_POLARITY) |
||
| 703 | |||
| 704 | #define CTMU_EDGE2_SOURCE_CTED1 0x0060 /*CTED1 is a source select for Edge2*/ |
||
| 705 | #define CTMU_EDGE2_SOURCE_CTED2 0x0040 /*CTED2 is a source select for Edge2*/ |
||
| 706 | #define CTMU_EDGE2_SOURCE_OC1 0x0020 /*OC1 is a source select for Edge2*/ |
||
| 707 | #define CTMU_EDGE2_SOURCE_TIMER1 0x0000 /*TIMER1 is a source select for Edge2*/ |
||
| 708 | #define CTMU_EDGE2_SOURCE_MASK (~CTMU_EDGE2_SOURCE_CTED1) |
||
| 709 | |||
| 710 | /*CTMU1CON Current Control register*/ |
||
| 711 | #define CTMU_POS_CURR_TRIM 0x0400 /*2% of Positive change from nominal current*/ |
||
| 712 | #define CTMU_NEG_CURR_TRIM 0xFC00 /*2% of Negative change from nominal current*/ |
||
| 713 | #define CTMU_NOMINAL_CURRENT 0x0000 /*Nominal Current output specified by IRNG1:IRNG0*/ |
||
| 714 | |||
| 715 | #define CTMU_INT_PRI 0x0000 /*CTMU interrupt priority is 0*/ |
||
| 716 | |||
| 717 | #define CTMU_INT_ENABLE 0x0008 /* Enable CTMU interrupts */ |
||
| 718 | #define CTMU_INT_DISABLE 0x0000 /* Disable CTMU interrupts */ |
||
| 719 | |||
| 720 | |||
| 721 | /************************************************************************ |
||
| 722 | Macro : Set_CTMU_ENABLE_Status |
||
| 723 | Overview : setting or clearing CTMU Enable Module Bit |
||
| 724 | Parameters : ENABLE '1' or DISABLE '0' |
||
| 725 | Remarks : None. |
||
| 726 | **************************************************************************/ |
||
| 727 | #define Set_CTMU_ENABLE_Status(State) (CTMUCONbits.CTMUEN = State) |
||
| 728 | |||
| 729 | /************************************************************************ |
||
| 730 | Macro : Idle_Mode_CTMU_Operation |
||
| 731 | Overview : CTMU Operation in Idle |
||
| 732 | Parameters : ENABLE '1' or DISABLE '0' |
||
| 733 | Remarks : None. |
||
| 734 | **************************************************************************/ |
||
| 735 | #define Idle_Mode_CTMU_Operation(State) (CTMUCONbits.CTMUSIDL = State) |
||
| 736 | |||
| 737 | /************************************************************************ |
||
| 738 | Macro : Set_CTMU_Time_Generation |
||
| 739 | Overview : setting or clearing CTMU TIME Generation Bit |
||
| 740 | Parameters : ENABLE '1' or DISABLE '0' |
||
| 741 | Remarks : None. |
||
| 742 | **************************************************************************/ |
||
| 743 | #define Set_CTMU_Time_Generation(State) (CTMUCONbits.TGEN = State) |
||
| 744 | |||
| 745 | |||
| 746 | /************************************************************************ |
||
| 747 | Macro : Enable_Disable_CTMU_Time_Generation |
||
| 748 | Overview : setting or clearing CTMU TIME Generation Bit |
||
| 749 | Parameters : ENABLE '1' or DISABLE '0' |
||
| 750 | Remarks : None. |
||
| 751 | **************************************************************************/ |
||
| 752 | #define Block_CTMU_Edge(State) (CTMUCONbits.EDGEN = 0) |
||
| 753 | |||
| 754 | /************************************************************************ |
||
| 755 | Macro : Enable_Disable_CTMU_Time_Generation |
||
| 756 | Overview : setting or clearing CTMU TIME Generation Bit |
||
| 757 | Parameters : ENABLE '1' or DISABLE '0' |
||
| 758 | Remarks : None. |
||
| 759 | **************************************************************************/ |
||
| 760 | #define Unblock_CTMU_Edge(State) (CTMUCONbits.EDGEN = 1) |
||
| 761 | |||
| 762 | |||
| 763 | /************************************************************************ |
||
| 764 | Macro : Set_CTMU_Edge_Sequence |
||
| 765 | Overview : setting or clearing CTMU Edge Sequence Bit |
||
| 766 | Parameters : ENABLE '1' or DISABLE '0' |
||
| 767 | Remarks : None. |
||
| 768 | **************************************************************************/ |
||
| 769 | #define Set_Edge_Sequence(State) (CTMUCONbits.EDGSEQEN = State) |
||
| 770 | |||
| 771 | |||
| 772 | /************************************************************************ |
||
| 773 | Macro : Enable_CTMU_CurrentDischarge |
||
| 774 | Overview : setting the CTMU Current Discharge Bit |
||
| 775 | Parameters : None |
||
| 776 | Remarks : None. |
||
| 777 | **************************************************************************/ |
||
| 778 | #define Enble_CTMU_CurrentDischarge (CTMUCONbits.IDISSEN = 1) |
||
| 779 | |||
| 780 | /************************************************************************ |
||
| 781 | Macro : Disable_CTMU_CurrentDischarge |
||
| 782 | Overview : Clearing the CTMU Current Discharge Bit |
||
| 783 | Parameters : None |
||
| 784 | Remarks : None. |
||
| 785 | **************************************************************************/ |
||
| 786 | #define Disble_CTMU_CurrentDischarge (CTMUCONbits.IDISSEN = 0) |
||
| 787 | |||
| 788 | |||
| 789 | |||
| 790 | /************************************************************************ |
||
| 791 | Macro : Set_CTMU_Trigger_Control |
||
| 792 | Overview : setting or clearing CTMU Trigger Control Bit |
||
| 793 | Parameters : ENABLE '1' or DISABLE '0' |
||
| 794 | Remarks : None. |
||
| 795 | **************************************************************************/ |
||
| 796 | #define Set_CTMU_Trigger_Control(State) (CTMUCONbits.CTTRIG = State) |
||
| 797 | |||
| 798 | |||
| 799 | |||
| 800 | /************************************************************************ |
||
| 801 | Macro : Enble_CTMU_Positive_Edge2_Polarity |
||
| 802 | Overview : By setting Edge 2 Polarity Select bit |
||
| 803 | Parameters : None |
||
| 804 | Remarks : None. |
||
| 805 | **************************************************************************/ |
||
| 806 | #define Enble_CTMU_Positive_Edge2_Polarity (CTMUCONbits.EDG2POL = 1) |
||
| 807 | |||
| 808 | |||
| 809 | /************************************************************************ |
||
| 810 | Macro : Enble_CTMU_Negative_Edge2_Polarity |
||
| 811 | Overview : By setting Edge 2 Polarity Select bit |
||
| 812 | Parameters : None |
||
| 813 | Remarks : None. |
||
| 814 | **************************************************************************/ |
||
| 815 | #define Enble_CTMU_Negative_Edge2_Polarity (CTMUCONbits.EDG2POL = 0) |
||
| 816 | |||
| 817 | |||
| 818 | /************************************************************************ |
||
| 819 | Macro : Enble_CTMU_Positive_Edge1_Polarity |
||
| 820 | Overview : By setting Edge 1 Polarity Select bit |
||
| 821 | Parameters : None |
||
| 822 | Remarks : None. |
||
| 823 | **************************************************************************/ |
||
| 824 | #define Enble_CTMU_Positive_Edge1_Polarity (CTMUCONbits.EDG1POL = 1) |
||
| 825 | |||
| 826 | |||
| 827 | /************************************************************************ |
||
| 828 | Macro : Enble_CTMU_Negative_Edge1_Polarity |
||
| 829 | Overview : By setting Edge 1 Polarity Select bit |
||
| 830 | Parameters : None |
||
| 831 | Remarks : None. |
||
| 832 | **************************************************************************/ |
||
| 833 | #define Enble_CTMU_Negative_Edge1_Polarity (CTMUCONbits.EDG1POL = 0) |
||
| 834 | |||
| 835 | |||
| 836 | /************************************************************************ |
||
| 837 | Macro : CTMU_Edge1_Source_Select |
||
| 838 | Overview : Edge 1 Source Select bits |
||
| 839 | Parameters : State |
||
| 840 | Remarks : None. |
||
| 841 | **************************************************************************/ |
||
| 842 | #define CTMU_Edge1_Source_Select(State) (CTMUCONbits.EDG1SEL = State) |
||
| 843 | |||
| 844 | |||
| 845 | /************************************************************************ |
||
| 846 | Macro : CTMU_Edge2_Source_Select |
||
| 847 | Overview : Edge 2 Source Select bits |
||
| 848 | Parameters : TRIGGER_SOURCE_TIMER1=0, |
||
| 849 | TRIGGER_SOURCE_OC, |
||
| 850 | TRIGGER_SOURCE_EXTERNAL2, |
||
| 851 | TRIGGER_SOURCE_EXTERNAL1 |
||
| 852 | Remarks : None. |
||
| 853 | **************************************************************************/ |
||
| 854 | #define CTMU_Edge2_Source_Select(State) (CTMUCONbits.EDG2SEL = State) |
||
| 855 | |||
| 856 | |||
| 857 | /************************************************************************ |
||
| 858 | Macro : Enble_CTMUEdge1 |
||
| 859 | Overview : By setting edge1 status bit current source enables |
||
| 860 | Parameters : None |
||
| 861 | Remarks : None. |
||
| 862 | **************************************************************************/ |
||
| 863 | #define Enble_CTMUEdge1 (CTMUCONbits.EDG1STAT = 1) |
||
| 864 | |||
| 865 | |||
| 866 | /************************************************************************ |
||
| 867 | Macro : Enble_CTMUEdge2 |
||
| 868 | Overview : By setting edge2 status bit current source enables |
||
| 869 | Parameters : None |
||
| 870 | Remarks : None. |
||
| 871 | **************************************************************************/ |
||
| 872 | #define Enble_CTMUEdge2 (CTMUCONbits.EDG2STAT = 1) |
||
| 873 | |||
| 874 | |||
| 875 | /************************************************************************ |
||
| 876 | Macro :Disbl_CTMUEdge1 |
||
| 877 | Overview : By clearing edge1 status bit disable the current source |
||
| 878 | Parameters : None |
||
| 879 | Remarks : None. |
||
| 880 | **************************************************************************/ |
||
| 881 | #define Disbl_CTMUEdge1 (CTMUCONbits.EDG1STAT = 0) |
||
| 882 | |||
| 883 | |||
| 884 | /************************************************************************ |
||
| 885 | Macro :Disbl_CTMUEdge2 |
||
| 886 | Overview : By clearing edge2 status bit disable the current source |
||
| 887 | Parameters : None |
||
| 888 | Remarks : None. |
||
| 889 | **************************************************************************/ |
||
| 890 | #define Disbl_CTMUEdge2 (CTMUCONbits.EDG2STAT = 0) |
||
| 891 | |||
| 892 | |||
| 893 | /************************************************************************ |
||
| 894 | Macro : Disbl_Currentsource |
||
| 895 | Overview : By clearing EDGSTAT bit disable the source. |
||
| 896 | Parameters : None |
||
| 897 | Remarks : None. |
||
| 898 | **************************************************************************/ |
||
| 899 | #define Disbl_CurrentSource ( CTMUCONbits.EDG1STAT = 0 , CTMUCONbits.EDG2STAT = 0 ) |
||
| 900 | |||
| 901 | |||
| 902 | /************************************************************************ |
||
| 903 | Macro : Enabl_Currentsource |
||
| 904 | Overview : By setting EDGSTAT bit disable the source. |
||
| 905 | Parameters : None |
||
| 906 | Remarks : None. |
||
| 907 | **************************************************************************/ |
||
| 908 | #define Enble_CurrentSource (CTMUCONbits.EDG1STAT = 1 , CTMUCONbits.EDG2STAT = 1 ) |
||
| 909 | |||
| 910 | |||
| 911 | /************************************************************************ |
||
| 912 | Macro : CTMUEdge1_Status |
||
| 913 | Overview : Returns the status of CTMU edge1 |
||
| 914 | Parameters : None |
||
| 915 | Remarks : None. |
||
| 916 | **************************************************************************/ |
||
| 917 | #define CTMUEdge1_Status CTMUCONbits.EDG1STAT |
||
| 918 | |||
| 919 | /************************************************************************ |
||
| 920 | Macro : CTMUEdge2_Status |
||
| 921 | Overview : Returns the status of CTMU edge2 |
||
| 922 | Parameters : None |
||
| 923 | Remarks : None. |
||
| 924 | **************************************************************************/ |
||
| 925 | #define CTMUEdge2_Status CTMUCONbits.EDG2STAT |
||
| 926 | |||
| 927 | |||
| 928 | /************************************************************************ |
||
| 929 | Macro : CTMU_Trim_Value |
||
| 930 | Overview : Sets the Trim Value for CTMU |
||
| 931 | Parameters : Singed data Range (011111) i.e +31 to (100001) i.e -1 |
||
| 932 | Remarks : None. |
||
| 933 | **************************************************************************/ |
||
| 934 | #define CTMU_Trim_Value(Value) CTMUICONbits.ITRIM = (Value) |
||
| 935 | |||
| 936 | |||
| 937 | |||
| 938 | /************************************************************************ |
||
| 939 | Macro : CTMU_Select_Current_Source |
||
| 940 | Overview : Sets the current source range Value for CTMU |
||
| 941 | Parameters : CURRENT_RANGE_100XBASE_CURRENT //urrent source Range is 100*Base current (55uA) |
||
| 942 | * CURRENT_RANGE_10XBASE_CURRENT //Current source Range is 10*Base current (5.5uA) |
||
| 943 | * CURRENT_RANGE_BASE_CURRENT //Current source Range is Base current (0.55uA) |
||
| 944 | * CURRENT_SRC_DISABLED //Current source disabled |
||
| 945 | * |
||
| 946 | Remarks : None. |
||
| 947 | **************************************************************************/ |
||
| 948 | #define CTMU_Select_Current_Source(Value) CTMUICONbits.IRNG = (Value) |
||
| 949 | |||
| 950 | |||
| 951 | /************************************************************************ |
||
| 952 | Macro : CTMU_Get_Current_Source |
||
| 953 | Overview : Gets the Current Source range value |
||
| 954 | Parameters : None |
||
| 955 | Remarks : None. |
||
| 956 | **************************************************************************/ |
||
| 957 | #define CTMU_Get_Current_Source CTMUICONbits.IRNG |
||
| 958 | |||
| 959 | |||
| 960 | /*********************************************************************** |
||
| 961 | Macro : EnableIntCTMU |
||
| 962 | Overview : This macro enables the CTMU interrupt. |
||
| 963 | Parameters : None |
||
| 964 | Remarks : This macro sets CTMU Interrupt Enable bit of Interrupt |
||
| 965 | Enable Control Register. |
||
| 966 | ************************************************************************/ |
||
| 967 | #define EnableIntCTMU (IEC4bits.CTMUIE = 1) |
||
| 968 | |||
| 969 | /*********************************************************************** |
||
| 970 | Macro : DisableIntCTMU |
||
| 971 | Overview : This macro disables the CTMU interrupt. |
||
| 972 | Parameters : None |
||
| 973 | Remarks : This macro clears CTMU Interrupt Enable bit of Interrupt |
||
| 974 | Enable Control register. |
||
| 975 | ************************************************************************/ |
||
| 976 | #define DisableIntCTMU (IEC4bits.CTMUIE = 0) |
||
| 977 | |||
| 978 | /*********************************************************************** |
||
| 979 | Macro : SetPriorityIntCTMU(priority) |
||
| 980 | Overview : This macro sets priority for CTMU interrupt. |
||
| 981 | Parameters : priority - This input parameter is the level of interrupt priority |
||
| 982 | Remarks : This macro sets CTMU Interrupt Priority bits of Interrupt |
||
| 983 | Priority Control register. |
||
| 984 | ************************************************************************/ |
||
| 985 | #define SetPriorityIntCTMU(priority) (IPC19bits.CTMUIP = priority) |
||
| 986 | |||
| 987 | /******************************************************************* |
||
| 988 | Macro : CTMU_Clear_Intr_Status_Bit |
||
| 989 | Overview : Macro to Clear CTMU Interrupt Status bit |
||
| 990 | Parameters : None |
||
| 991 | Remarks : None |
||
| 992 | *******************************************************************/ |
||
| 993 | #define CTMU_Clear_Intr_Status_Bit (IFS4bits.CTMUIF = 0) |
||
| 994 | |||
| 995 | |||
| 996 | #endif //#ifdef __PIC24F__ |
||
| 997 | |||
| 998 | #endif // _MTOUCH_PIC24_CTMU_PHYSICAL_H |
||
| 999 | |||
| 1000 |
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