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1 32 kaklik /*********************************************************************
2 *
3 * National DP83640 PHY API for Microchip TCP/IP Stack
4 *
5 *********************************************************************
6 * FileName: ETHPIC32ExtPhyDP83640.c
7 * Dependencies:
8 * Processor: PIC32
9 *
10 * Complier: MPLAB C32
11 * MPLAB IDE
12 * Company: Microchip Technology, Inc.
13 *
14 * Software License Agreement
15 *
16 * Copyright © 2009 Microchip Technology Inc. All rights reserved.
17 *
18 * Microchip licenses the Software for your use with Microchip microcontrollers
19 * and Microchip digital signal controllers pursuant to the terms of the
20 * Non-Exclusive Software License Agreement accompanying this Software.
21 *
22 * SOFTWARE AND DOCUMENTATION ARE PROVIDED “AS IS” WITHOUT WARRANTY
23 * OF ANY KIND, EITHER EXPRESS OR IMPLIED, INCLUDING WITHOUT LIMITATION,
24 * ANY WARRANTY OF MERCHANTABILITY, TITLE, NON-INFRINGEMENT AND FITNESS
25 * FOR A PARTICULAR PURPOSE.
26 * MICROCHIP AND ITS LICENSORS ASSUME NO RESPONSIBILITY FOR THE ACCURACY,
27 * RELIABILITY OR APPLICATION OF THE SOFTWARE AND DOCUMENTATION.
28 * IN NO EVENT SHALL MICROCHIP OR ITS LICENSORS BE LIABLE OR OBLIGATED
29 * UNDER CONTRACT, NEGLIGENCE, STRICT LIABILITY, CONTRIBUTION, BREACH
30 * OF WARRANTY, OR OTHER LEGAL EQUITABLE THEORY ANY DIRECT OR INDIRECT
31 * DAMAGES OR EXPENSES INCLUDING BUT NOT LIMITED TO ANY INCIDENTAL,
32 * SPECIAL, INDIRECT, PUNITIVE OR CONSEQUENTIAL DAMAGES, LOST PROFITS
33 * OR LOST DATA, COST OF PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY,
34 * SERVICES, OR ANY CLAIMS BY THIRD PARTIES (INCLUDING BUT NOT LIMITED
35 * TO ANY DEFENSE THEREOF), OR OTHER SIMILAR COSTS.
36 *
37 * $Id: $
38 ********************************************************************/
39  
40  
41 #include <plib.h>
42  
43  
44 // Compile only for PIC32MX with Ethernet MAC interface (must not have external ENCX24J600, ENC28J60, or ZG2100M hardware defined)
45 #if defined(__PIC32MX__) && defined(_ETH) && !defined(ENC100_INTERFACE_MODE) && !defined(ENC_CS_TRIS) && !defined(ZG_CS_TRIS)
46  
47 #include "TCPIP Stack/ETHPIC32ExtPhy.h"
48  
49 #include "HardwareProfile.h"
50  
51 #include "TCPIP Stack/ETHPIC32ExtPhyDP83640.h"
52  
53  
54  
55 /****************************************************************************
56 * interface functions
57 ****************************************************************************/
58  
59  
60 /****************************************************************************
61 * Function: EthPhyConfigureMII
62 *
63 * PreCondition: - Communication to the PHY should have been established.
64 *
65 * Input: cFlags - the requested open flags: ETH_PHY_CFG_RMII/ETH_PHY_CFG_MII
66 *
67 * Output: ETH_RES_OK - success,
68 * an error code otherwise
69 *
70 *
71 * Side Effects: None
72 *
73 * Overview: This function configures the PHY in one of MII/RMII operation modes.
74 *
75 * Note: None
76 *****************************************************************************/
77 eEthRes EthPhyConfigureMII(eEthPhyCfgFlags cFlags)
78 {
79 unsigned short phyReg;
80  
81 // RMII_BYPASS is in page 0
82 EthMIIMWriteReg(PHY_REG_PAGESEL, PHY_ADDRESS, 0);
83  
84 phyReg=EthMIIMReadReg(PHY_REG_RMII_BYPASS, PHY_ADDRESS);
85  
86 if(cFlags&ETH_PHY_CFG_RMII)
87 {
88 phyReg|=_RMIIBYPASS_RMII_MODE_MASK;
89 phyReg&=~_RMIIBYPASS_RMII_REV1_0_MASK; // use RMII 1.2
90 }
91 else
92 {
93 phyReg&=~(_RMIIBYPASS_RMII_MODE_MASK); // MII
94 }
95  
96 EthMIIMWriteReg(PHY_REG_RMII_BYPASS, PHY_ADDRESS, phyReg); // update the RMII and Bypass Register
97  
98  
99 return ETH_RES_OK;
100  
101 }
102  
103  
104 /****************************************************************************
105 * Function: EthPhyConfigureMdix
106 *
107 * PreCondition: - Communication to the PHY should have been established.
108 *
109 * Input: oFlags - the requested open flags: ETH_OPEN_MDIX_AUTO, ETH_OPEN_MDIX_NORM/ETH_OPEN_MDIX_SWAP
110 *
111 * Output: ETH_RES_OK - success,
112 * an error code otherwise
113 *
114 *
115 * Side Effects: None
116 *
117 * Overview: This function configures the MDIX mode for the PHY.
118 *
119 * Note: None
120 *****************************************************************************/
121 eEthRes EthPhyConfigureMdix(eEthOpenFlags oFlags)
122 {
123 unsigned short phyReg;
124  
125 // PHY_CTRL is in page 0
126 EthMIIMWriteReg(PHY_REG_PAGESEL, PHY_ADDRESS, 0);
127  
128 phyReg=EthMIIMReadReg(PHY_REG_PHY_CTRL, PHY_ADDRESS);
129  
130 if(oFlags&ETH_OPEN_MDIX_AUTO)
131 { // enable Auto-MDIX
132 phyReg|=_PHYCTRL_MDIX_EN_MASK;
133 }
134 else
135 { // no Auto-MDIX
136 phyReg&=~(_PHYCTRL_MDIX_EN_MASK); // disable Auto-MDIX
137 if(oFlags&ETH_OPEN_MDIX_SWAP)
138 {
139 phyReg|=_PHYCTRL_FORCE_MDIX_MASK; // swap
140 }
141 else
142 {
143 phyReg&=~(_PHYCTRL_FORCE_MDIX_MASK); // normal
144 }
145 }
146  
147 EthMIIMWriteReg(PHY_REG_PHY_CTRL, PHY_ADDRESS, phyReg);
148  
149 return ETH_RES_OK;
150  
151 }
152  
153 /****************************************************************************
154 * Function: EthPhyMIIMAddress
155 *
156 * PreCondition: None
157 *
158 * Input: None
159 *
160 * Output: PHY MIIM address
161 *
162 *
163 * Side Effects: None
164 *
165 * Overview: This function returns the address the PHY uses for MIIM transactions
166 *
167 * Note: None
168 *****************************************************************************/
169 unsigned int EthPhyMIIMAddress(void)
170 {
171 return PHY_ADDRESS;
172 }
173  
174  
175 /****************************************************************************
176 * Function: EthPhyMIIMClock
177 *
178 * PreCondition: None
179 *
180 * Input: None
181 *
182 * Output: PHY MIIM clock, Hz
183 *
184 *
185 * Side Effects: None
186 *
187 * Overview: This function returns the maximum clock frequency that the PHY can use for the MIIM transactions
188 *
189 * Note: None
190 *****************************************************************************/
191 unsigned int EthPhyMIIMClock(void)
192 {
193 return 25000000; // 25 MHz max clock supported
194 }
195  
196  
197 #endif // defined(__PIC32MX__) && defined(_ETH)
198  
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