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1 32 kaklik /*********************************************************************
2 *
3 * National DP83848 PHY API for Microchip TCP/IP Stack
4 *
5 *********************************************************************
6 * FileName: ETHPIC32ExtPhyDP83848.c
7 * Dependencies:
8 * Processor: PIC32
9 *
10 * Complier: MPLAB C32
11 * MPLAB IDE
12 * Company: Microchip Technology, Inc.
13 *
14 * Software License Agreement
15 *
16 * Copyright © 2009 Microchip Technology Inc. All rights reserved.
17 *
18 * Microchip licenses the Software for your use with Microchip microcontrollers
19 * and Microchip digital signal controllers pursuant to the terms of the
20 * Non-Exclusive Software License Agreement accompanying this Software.
21 *
22 * SOFTWARE AND DOCUMENTATION ARE PROVIDED “AS IS” WITHOUT WARRANTY
23 * OF ANY KIND, EITHER EXPRESS OR IMPLIED, INCLUDING WITHOUT LIMITATION,
24 * ANY WARRANTY OF MERCHANTABILITY, TITLE, NON-INFRINGEMENT AND FITNESS
25 * FOR A PARTICULAR PURPOSE.
26 * MICROCHIP AND ITS LICENSORS ASSUME NO RESPONSIBILITY FOR THE ACCURACY,
27 * RELIABILITY OR APPLICATION OF THE SOFTWARE AND DOCUMENTATION.
28 * IN NO EVENT SHALL MICROCHIP OR ITS LICENSORS BE LIABLE OR OBLIGATED
29 * UNDER CONTRACT, NEGLIGENCE, STRICT LIABILITY, CONTRIBUTION, BREACH
30 * OF WARRANTY, OR OTHER LEGAL EQUITABLE THEORY ANY DIRECT OR INDIRECT
31 * DAMAGES OR EXPENSES INCLUDING BUT NOT LIMITED TO ANY INCIDENTAL,
32 * SPECIAL, INDIRECT, PUNITIVE OR CONSEQUENTIAL DAMAGES, LOST PROFITS
33 * OR LOST DATA, COST OF PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY,
34 * SERVICES, OR ANY CLAIMS BY THIRD PARTIES (INCLUDING BUT NOT LIMITED
35 * TO ANY DEFENSE THEREOF), OR OTHER SIMILAR COSTS.
36 *
37 * $Id: $
38 ********************************************************************/
39  
40  
41 #include <plib.h>
42  
43  
44 // Compile only for PIC32MX with Ethernet MAC interface (must not have external ENCX24J600, ENC28J60, or ZG2100M hardware defined)
45 #if defined(__PIC32MX__) && defined(_ETH) && !defined(ENC100_INTERFACE_MODE) && !defined(ENC_CS_TRIS) && !defined(ZG_CS_TRIS)
46  
47 #include "TCPIP Stack/ETHPIC32ExtPhy.h"
48  
49 #include "HardwareProfile.h"
50  
51 #include "TCPIP Stack/ETHPIC32ExtPhyDP83848.h"
52  
53  
54  
55 /****************************************************************************
56 * interface functions
57 ****************************************************************************/
58  
59  
60 /****************************************************************************
61 * Function: EthPhyConfigureMII
62 *
63 * PreCondition: - Communication to the PHY should have been established.
64 *
65 * Input: cFlags - the requested open flags: ETH_PHY_CFG_RMII/ETH_PHY_CFG_MII
66 *
67 * Output: ETH_RES_OK - success,
68 * an error code otherwise
69 *
70 *
71 * Side Effects: None
72 *
73 * Overview: This function configures the PHY in one of MII/RMII operation modes.
74 *
75 * Note: None
76 *****************************************************************************/
77 eEthRes EthPhyConfigureMII(eEthPhyCfgFlags cFlags)
78 {
79 unsigned short phyReg;
80  
81  
82 phyReg=EthMIIMReadReg(PHY_REG_RMII_BYPASS, PHY_ADDRESS);
83  
84 if(cFlags&ETH_PHY_CFG_RMII)
85 {
86 phyReg|=_RMIIBYPASS_RMII_MODE_MASK;
87 phyReg&=~_RMIIBYPASS_RMII_REV1_0_MASK; // use RMII 1.2
88 }
89 else
90 {
91 phyReg&=~(_RMIIBYPASS_RMII_MODE_MASK); // MII
92 }
93  
94 EthMIIMWriteReg(PHY_REG_RMII_BYPASS, PHY_ADDRESS, phyReg); // update the RMII and Bypass Register
95  
96  
97 return ETH_RES_OK;
98  
99 }
100  
101  
102 /****************************************************************************
103 * Function: EthPhyConfigureMdix
104 *
105 * PreCondition: - Communication to the PHY should have been established.
106 *
107 * Input: oFlags - the requested open flags: ETH_OPEN_MDIX_AUTO, ETH_OPEN_MDIX_NORM/ETH_OPEN_MDIX_SWAP
108 *
109 * Output: ETH_RES_OK - success,
110 * an error code otherwise
111 *
112 *
113 * Side Effects: None
114 *
115 * Overview: This function configures the MDIX mode for the PHY.
116 *
117 * Note: None
118 *****************************************************************************/
119 eEthRes EthPhyConfigureMdix(eEthOpenFlags oFlags)
120 {
121 unsigned short phyReg;
122  
123 phyReg=EthMIIMReadReg(PHY_REG_PHY_CTRL, PHY_ADDRESS);
124  
125 if(oFlags&ETH_OPEN_MDIX_AUTO)
126 { // enable Auto-MDIX
127 phyReg|=_PHYCTRL_MDIX_EN_MASK;
128 }
129 else
130 { // no Auto-MDIX
131 phyReg&=~(_PHYCTRL_MDIX_EN_MASK); // disable Auto-MDIX
132 if(oFlags&ETH_OPEN_MDIX_SWAP)
133 {
134 phyReg|=_PHYCTRL_FORCE_MDIX_MASK; // swap
135 }
136 else
137 {
138 phyReg&=~(_PHYCTRL_FORCE_MDIX_MASK); // normal
139 }
140 }
141  
142 EthMIIMWriteReg(PHY_REG_PHY_CTRL, PHY_ADDRESS, phyReg);
143  
144 return ETH_RES_OK;
145  
146 }
147  
148 /****************************************************************************
149 * Function: EthPhyMIIMAddress
150 *
151 * PreCondition: None
152 *
153 * Input: None
154 *
155 * Output: PHY MIIM address
156 *
157 *
158 * Side Effects: None
159 *
160 * Overview: This function returns the address the PHY uses for MIIM transactions
161 *
162 * Note: None
163 *****************************************************************************/
164 unsigned int EthPhyMIIMAddress(void)
165 {
166 return PHY_ADDRESS;
167 }
168  
169  
170 /****************************************************************************
171 * Function: EthPhyMIIMClock
172 *
173 * PreCondition: None
174 *
175 * Input: None
176 *
177 * Output: PHY MIIM clock, Hz
178 *
179 *
180 * Side Effects: None
181 *
182 * Overview: This function returns the maximum clock frequency that the PHY can use for the MIIM transactions
183 *
184 * Note: None
185 *****************************************************************************/
186 unsigned int EthPhyMIIMClock(void)
187 {
188 return 25000000; // 25 MHz max clock supported
189 }
190  
191  
192 #endif // defined(__PIC32MX__) && defined(_ETH)
193  
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