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1 32 kaklik /*********************************************************************
2 *
3 * SMSC LAN8700 PHY API for Microchip TCP/IP Stack
4 *
5 *********************************************************************
6 * FileName: ETHPIC32ExtPhySMSC8700.c
7 * Dependencies:
8 * Processor: PIC32
9 *
10 * Complier: MPLAB C32
11 * MPLAB IDE
12 * Company: Microchip Technology, Inc.
13 *
14 * Software License Agreement
15 * Microchip Audio Library – PIC32 Software.
16 * Copyright © 2008 Microchip Technology Inc. All rights reserved.
17 *
18 * Microchip licenses the Software for your use with Microchip microcontrollers
19 * and Microchip digital signal controllers pursuant to the terms of the
20 * Non-Exclusive Software License Agreement accompanying this Software.
21 *
22 * SOFTWARE AND DOCUMENTATION ARE PROVIDED “AS IS” WITHOUT WARRANTY
23 * OF ANY KIND, EITHER EXPRESS OR IMPLIED, INCLUDING WITHOUT LIMITATION,
24 * ANY WARRANTY OF MERCHANTABILITY, TITLE, NON-INFRINGEMENT AND FITNESS
25 * FOR A PARTICULAR PURPOSE.
26 * MICROCHIP AND ITS LICENSORS ASSUME NO RESPONSIBILITY FOR THE ACCURACY,
27 * RELIABILITY OR APPLICATION OF THE SOFTWARE AND DOCUMENTATION.
28 * IN NO EVENT SHALL MICROCHIP OR ITS LICENSORS BE LIABLE OR OBLIGATED
29 * UNDER CONTRACT, NEGLIGENCE, STRICT LIABILITY, CONTRIBUTION, BREACH
30 * OF WARRANTY, OR OTHER LEGAL EQUITABLE THEORY ANY DIRECT OR INDIRECT
31 * DAMAGES OR EXPENSES INCLUDING BUT NOT LIMITED TO ANY INCIDENTAL,
32 * SPECIAL, INDIRECT, PUNITIVE OR CONSEQUENTIAL DAMAGES, LOST PROFITS
33 * OR LOST DATA, COST OF PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY,
34 * SERVICES, OR ANY CLAIMS BY THIRD PARTIES (INCLUDING BUT NOT LIMITED
35 * TO ANY DEFENSE THEREOF), OR OTHER SIMILAR COSTS.
36 *
37 ********************************************************************/
38 #include <plib.h>
39  
40  
41 // Compile only for PIC32MX with Ethernet MAC interface (must not have external ENCX24J600, ENC28J60, or ZG2100M hardware defined)
42 #if defined(__PIC32MX__) && defined(_ETH) && !defined(ENC100_INTERFACE_MODE) && !defined(ENC_CS_TRIS) && !defined(ZG_CS_TRIS)
43  
44 #include "TCPIP Stack/ETHPIC32ExtPhy.h"
45  
46 #include "HardwareProfile.h"
47  
48 #include "TCPIP Stack/ETHPIC32ExtPhySMSC8700.h"
49  
50  
51  
52 /****************************************************************************
53 * interface functions
54 ****************************************************************************/
55  
56  
57 /****************************************************************************
58 * Function: EthPhyConfigureMII
59 *
60 * PreCondition: - Communication to the PHY should have been established.
61 *
62 * Input: cFlags - the requested configuration flags: ETH_PHY_CFG_RMII/ETH_PHY_CFG_MII
63 *
64 * Output: ETH_RES_OK - success,
65 * an error code otherwise
66 *
67 *
68 * Side Effects: None
69 *
70 * Overview: This function configures the PHY in one of MII/RMII operation modes.
71 *
72 * Note: None
73 *****************************************************************************/
74 eEthRes EthPhyConfigureMII(eEthPhyCfgFlags cFlags)
75 {
76 unsigned short phyReg;
77  
78  
79 phyReg=EthMIIMReadReg(PHY_REG_SPECIAL_MODE, PHY_ADDRESS)&(_SPECIALMODE_PHYAD_MASK|_SPECIALMODE_MODE_MASK); // not used bits should be 0
80 if(cFlags&ETH_PHY_CFG_RMII)
81 {
82 phyReg|=_SPECIALMODE_MIIMODE_MASK;
83 }
84 else
85 {
86 phyReg&=~_SPECIALMODE_MIIMODE_MASK;
87 }
88 EthMIIMWriteReg(PHY_REG_SPECIAL_MODE, PHY_ADDRESS, phyReg); // update the Special Modes reg
89  
90  
91 return ETH_RES_OK;
92  
93 }
94  
95  
96 /****************************************************************************
97 * Function: EthPhyConfigureMdix
98 *
99 * PreCondition: - Communication to the PHY should have been established.
100 *
101 * Input: oFlags - the requested open flags: ETH_OPEN_MDIX_AUTO, ETH_OPEN_MDIX_NORM/ETH_OPEN_MDIX_SWAP
102 *
103 * Output: ETH_RES_OK - success,
104 * an error code otherwise
105 *
106 *
107 * Side Effects: None
108 *
109 * Overview: This function configures the MDIX mode for the PHY.
110 *
111 * Note: None
112 *****************************************************************************/
113 eEthRes EthPhyConfigureMdix(eEthOpenFlags oFlags)
114 {
115 unsigned short phyReg;
116  
117 phyReg=EthMIIMReadReg(PHY_REG_SPECIAL_CTRL, PHY_ADDRESS)&(_SPECIALCTRL_SQEOFF_MASK|_SPECIALCTRL_XPOL_MASK); // not used bits should be 0
118  
119 if(oFlags&ETH_OPEN_MDIX_AUTO)
120 { // enable Auto-MDIX
121 phyReg&=~_SPECIALCTRL_AMDIXCTRL_MASK;
122 }
123 else
124 { // no Auto-MDIX
125 phyReg|=_SPECIALCTRL_AMDIXCTRL_MASK; // disable Auto-MDIX
126 if(oFlags&ETH_OPEN_MDIX_SWAP)
127 {
128 phyReg|=_SPECIALCTRL_CH_SELECT_MASK; // swap
129 }
130 else
131 {
132 phyReg&=~_SPECIALCTRL_CH_SELECT_MASK; // normal
133 }
134 }
135  
136 EthMIIMWriteReg(PHY_REG_SPECIAL_CTRL, PHY_ADDRESS, phyReg);
137  
138 return ETH_RES_OK;
139  
140 }
141  
142 /****************************************************************************
143 * Function: EthPhyMIIMAddress
144 *
145 * PreCondition: None
146 *
147 * Input: None
148 *
149 * Output: PHY MIIM address
150 *
151 *
152 * Side Effects: None
153 *
154 * Overview: This function returns the address the PHY uses for MIIM transactions
155 *
156 * Note: None
157 *****************************************************************************/
158 unsigned int EthPhyMIIMAddress(void)
159 {
160 return PHY_ADDRESS;
161 }
162  
163  
164 /****************************************************************************
165 * Function: EthPhyMIIMClock
166 *
167 * PreCondition: None
168 *
169 * Input: None
170 *
171 * Output: PHY MIIM clock, Hz
172 *
173 *
174 * Side Effects: None
175 *
176 * Overview: This function returns the maximum clock frequency that the PHY can use for the MIIM transactions
177 *
178 * Note: None
179 *****************************************************************************/
180 unsigned int EthPhyMIIMClock(void)
181 {
182 return 2500000; // 2.5 MHz max clock supported
183 }
184  
185 #endif // defined(__PIC32MX__) && defined(_ETH)
186  
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