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1 | 32 | kaklik | /********************************************************************* |
2 | * |
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3 | * SMSC LAN8700 PHY API for Microchip TCP/IP Stack |
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4 | * |
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5 | ********************************************************************* |
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6 | * FileName: ETHPIC32ExtPhySMSC8700.c |
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7 | * Dependencies: |
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8 | * Processor: PIC32 |
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9 | * |
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10 | * Complier: MPLAB C32 |
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11 | * MPLAB IDE |
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12 | * Company: Microchip Technology, Inc. |
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13 | * |
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14 | * Software License Agreement |
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15 | * Microchip Audio Library PIC32 Software. |
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16 | * Copyright © 2008 Microchip Technology Inc. All rights reserved. |
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17 | * |
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18 | * Microchip licenses the Software for your use with Microchip microcontrollers |
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19 | * and Microchip digital signal controllers pursuant to the terms of the |
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20 | * Non-Exclusive Software License Agreement accompanying this Software. |
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21 | * |
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22 | * SOFTWARE AND DOCUMENTATION ARE PROVIDED AS IS WITHOUT WARRANTY |
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23 | * OF ANY KIND, EITHER EXPRESS OR IMPLIED, INCLUDING WITHOUT LIMITATION, |
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24 | * ANY WARRANTY OF MERCHANTABILITY, TITLE, NON-INFRINGEMENT AND FITNESS |
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25 | * FOR A PARTICULAR PURPOSE. |
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26 | * MICROCHIP AND ITS LICENSORS ASSUME NO RESPONSIBILITY FOR THE ACCURACY, |
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27 | * RELIABILITY OR APPLICATION OF THE SOFTWARE AND DOCUMENTATION. |
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28 | * IN NO EVENT SHALL MICROCHIP OR ITS LICENSORS BE LIABLE OR OBLIGATED |
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29 | * UNDER CONTRACT, NEGLIGENCE, STRICT LIABILITY, CONTRIBUTION, BREACH |
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30 | * OF WARRANTY, OR OTHER LEGAL EQUITABLE THEORY ANY DIRECT OR INDIRECT |
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31 | * DAMAGES OR EXPENSES INCLUDING BUT NOT LIMITED TO ANY INCIDENTAL, |
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32 | * SPECIAL, INDIRECT, PUNITIVE OR CONSEQUENTIAL DAMAGES, LOST PROFITS |
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33 | * OR LOST DATA, COST OF PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY, |
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34 | * SERVICES, OR ANY CLAIMS BY THIRD PARTIES (INCLUDING BUT NOT LIMITED |
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35 | * TO ANY DEFENSE THEREOF), OR OTHER SIMILAR COSTS. |
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36 | * |
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37 | ********************************************************************/ |
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38 | #include <plib.h> |
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39 | |||
40 | |||
41 | // Compile only for PIC32MX with Ethernet MAC interface (must not have external ENCX24J600, ENC28J60, or ZG2100M hardware defined) |
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42 | #if defined(__PIC32MX__) && defined(_ETH) && !defined(ENC100_INTERFACE_MODE) && !defined(ENC_CS_TRIS) && !defined(ZG_CS_TRIS) |
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43 | |||
44 | #include "TCPIP Stack/ETHPIC32ExtPhy.h" |
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45 | |||
46 | #include "HardwareProfile.h" |
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47 | |||
48 | #include "TCPIP Stack/ETHPIC32ExtPhySMSC8700.h" |
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49 | |||
50 | |||
51 | |||
52 | /**************************************************************************** |
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53 | * interface functions |
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54 | ****************************************************************************/ |
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55 | |||
56 | |||
57 | /**************************************************************************** |
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58 | * Function: EthPhyConfigureMII |
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59 | * |
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60 | * PreCondition: - Communication to the PHY should have been established. |
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61 | * |
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62 | * Input: cFlags - the requested configuration flags: ETH_PHY_CFG_RMII/ETH_PHY_CFG_MII |
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63 | * |
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64 | * Output: ETH_RES_OK - success, |
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65 | * an error code otherwise |
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66 | * |
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67 | * |
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68 | * Side Effects: None |
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69 | * |
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70 | * Overview: This function configures the PHY in one of MII/RMII operation modes. |
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71 | * |
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72 | * Note: None |
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73 | *****************************************************************************/ |
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74 | eEthRes EthPhyConfigureMII(eEthPhyCfgFlags cFlags) |
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75 | { |
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76 | unsigned short phyReg; |
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77 | |||
78 | |||
79 | phyReg=EthMIIMReadReg(PHY_REG_SPECIAL_MODE, PHY_ADDRESS)&(_SPECIALMODE_PHYAD_MASK|_SPECIALMODE_MODE_MASK); // not used bits should be 0 |
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80 | if(cFlagsÐ_PHY_CFG_RMII) |
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81 | { |
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82 | phyReg|=_SPECIALMODE_MIIMODE_MASK; |
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83 | } |
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84 | else |
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85 | { |
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86 | phyReg&=~_SPECIALMODE_MIIMODE_MASK; |
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87 | } |
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88 | EthMIIMWriteReg(PHY_REG_SPECIAL_MODE, PHY_ADDRESS, phyReg); // update the Special Modes reg |
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89 | |||
90 | |||
91 | return ETH_RES_OK; |
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92 | |||
93 | } |
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94 | |||
95 | |||
96 | /**************************************************************************** |
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97 | * Function: EthPhyConfigureMdix |
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98 | * |
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99 | * PreCondition: - Communication to the PHY should have been established. |
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100 | * |
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101 | * Input: oFlags - the requested open flags: ETH_OPEN_MDIX_AUTO, ETH_OPEN_MDIX_NORM/ETH_OPEN_MDIX_SWAP |
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102 | * |
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103 | * Output: ETH_RES_OK - success, |
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104 | * an error code otherwise |
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105 | * |
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106 | * |
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107 | * Side Effects: None |
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108 | * |
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109 | * Overview: This function configures the MDIX mode for the PHY. |
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110 | * |
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111 | * Note: None |
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112 | *****************************************************************************/ |
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113 | eEthRes EthPhyConfigureMdix(eEthOpenFlags oFlags) |
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114 | { |
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115 | unsigned short phyReg; |
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116 | |||
117 | phyReg=EthMIIMReadReg(PHY_REG_SPECIAL_CTRL, PHY_ADDRESS)&(_SPECIALCTRL_SQEOFF_MASK|_SPECIALCTRL_XPOL_MASK); // not used bits should be 0 |
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118 | |||
119 | if(oFlagsÐ_OPEN_MDIX_AUTO) |
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120 | { // enable Auto-MDIX |
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121 | phyReg&=~_SPECIALCTRL_AMDIXCTRL_MASK; |
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122 | } |
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123 | else |
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124 | { // no Auto-MDIX |
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125 | phyReg|=_SPECIALCTRL_AMDIXCTRL_MASK; // disable Auto-MDIX |
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126 | if(oFlagsÐ_OPEN_MDIX_SWAP) |
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127 | { |
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128 | phyReg|=_SPECIALCTRL_CH_SELECT_MASK; // swap |
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129 | } |
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130 | else |
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131 | { |
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132 | phyReg&=~_SPECIALCTRL_CH_SELECT_MASK; // normal |
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133 | } |
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134 | } |
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135 | |||
136 | EthMIIMWriteReg(PHY_REG_SPECIAL_CTRL, PHY_ADDRESS, phyReg); |
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137 | |||
138 | return ETH_RES_OK; |
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139 | |||
140 | } |
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141 | |||
142 | /**************************************************************************** |
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143 | * Function: EthPhyMIIMAddress |
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144 | * |
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145 | * PreCondition: None |
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146 | * |
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147 | * Input: None |
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148 | * |
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149 | * Output: PHY MIIM address |
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150 | * |
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151 | * |
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152 | * Side Effects: None |
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153 | * |
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154 | * Overview: This function returns the address the PHY uses for MIIM transactions |
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155 | * |
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156 | * Note: None |
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157 | *****************************************************************************/ |
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158 | unsigned int EthPhyMIIMAddress(void) |
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159 | { |
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160 | return PHY_ADDRESS; |
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161 | } |
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162 | |||
163 | |||
164 | /**************************************************************************** |
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165 | * Function: EthPhyMIIMClock |
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166 | * |
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167 | * PreCondition: None |
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168 | * |
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169 | * Input: None |
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170 | * |
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171 | * Output: PHY MIIM clock, Hz |
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172 | * |
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173 | * |
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174 | * Side Effects: None |
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175 | * |
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176 | * Overview: This function returns the maximum clock frequency that the PHY can use for the MIIM transactions |
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177 | * |
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178 | * Note: None |
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179 | *****************************************************************************/ |
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180 | unsigned int EthPhyMIIMClock(void) |
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181 | { |
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182 | return 2500000; // 2.5 MHz max clock supported |
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183 | } |
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184 | |||
185 | #endif // defined(__PIC32MX__) && defined(_ETH) |
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186 |
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