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1 32 kaklik /*********************************************************************
2 *
3 * SMSC LAN8720 PHY API for Microchip TCP/IP Stack
4 *
5 *********************************************************************
6 * FileName: ETHPIC32ExtPhySMSC8720.c
7 * Dependencies:
8 * Processor: PIC32
9 *
10 * Complier: MPLAB C32
11 * MPLAB IDE
12 * Company: Microchip Technology, Inc.
13 *
14 * Software License Agreement
15 * Microchip Audio Library – PIC32 Software.
16 * Copyright © 2008 Microchip Technology Inc. All rights reserved.
17 *
18 * Microchip licenses the Software for your use with Microchip microcontrollers
19 * and Microchip digital signal controllers pursuant to the terms of the
20 * Non-Exclusive Software License Agreement accompanying this Software.
21 *
22 * SOFTWARE AND DOCUMENTATION ARE PROVIDED “AS IS” WITHOUT WARRANTY
23 * OF ANY KIND, EITHER EXPRESS OR IMPLIED, INCLUDING WITHOUT LIMITATION,
24 * ANY WARRANTY OF MERCHANTABILITY, TITLE, NON-INFRINGEMENT AND FITNESS
25 * FOR A PARTICULAR PURPOSE.
26 * MICROCHIP AND ITS LICENSORS ASSUME NO RESPONSIBILITY FOR THE ACCURACY,
27 * RELIABILITY OR APPLICATION OF THE SOFTWARE AND DOCUMENTATION.
28 * IN NO EVENT SHALL MICROCHIP OR ITS LICENSORS BE LIABLE OR OBLIGATED
29 * UNDER CONTRACT, NEGLIGENCE, STRICT LIABILITY, CONTRIBUTION, BREACH
30 * OF WARRANTY, OR OTHER LEGAL EQUITABLE THEORY ANY DIRECT OR INDIRECT
31 * DAMAGES OR EXPENSES INCLUDING BUT NOT LIMITED TO ANY INCIDENTAL,
32 * SPECIAL, INDIRECT, PUNITIVE OR CONSEQUENTIAL DAMAGES, LOST PROFITS
33 * OR LOST DATA, COST OF PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY,
34 * SERVICES, OR ANY CLAIMS BY THIRD PARTIES (INCLUDING BUT NOT LIMITED
35 * TO ANY DEFENSE THEREOF), OR OTHER SIMILAR COSTS.
36 *
37 ********************************************************************/
38 #include <plib.h>
39  
40  
41 // Compile only for PIC32MX with Ethernet MAC interface (must not have external ENCX24J600, ENC28J60, or MRF24WB0M hardware defined)
42 #if defined(__PIC32MX__) && defined(_ETH) && !defined(ENC100_INTERFACE_MODE) && !defined(ENC_CS_TRIS) && !defined(WF_CS_TRIS)
43  
44 #include "TCPIP Stack/ETHPIC32ExtPhy.h"
45  
46 #include "HardwareProfile.h"
47  
48 #include "TCPIP Stack/ETHPIC32ExtPhySMSC8720.h"
49  
50  
51  
52 /****************************************************************************
53 * interface functions
54 ****************************************************************************/
55  
56  
57 /****************************************************************************
58 * Function: EthPhyConfigureMII
59 *
60 * PreCondition: - Communication to the PHY should have been established.
61 *
62 * Input: cFlags - the requested configuration flags: ETH_PHY_CFG_RMII/ETH_PHY_CFG_MII
63 *
64 * Output: ETH_RES_OK - success,
65 * an error code otherwise
66 *
67 *
68 * Side Effects: None
69 *
70 * Overview: This function configures the PHY in one of MII/RMII operation modes.
71 *
72 * Note: SMSC 8720 supports RMII mode only!
73 *****************************************************************************/
74 eEthRes EthPhyConfigureMII(eEthPhyCfgFlags cFlags)
75 {
76 return (cFlags&ETH_PHY_CFG_RMII)?ETH_RES_OK:ETH_RES_CFG_ERR;
77 }
78  
79  
80 /****************************************************************************
81 * Function: EthPhyConfigureMdix
82 *
83 * PreCondition: - Communication to the PHY should have been established.
84 *
85 * Input: oFlags - the requested open flags: ETH_OPEN_MDIX_AUTO, ETH_OPEN_MDIX_NORM/ETH_OPEN_MDIX_SWAP
86 *
87 * Output: ETH_RES_OK - success,
88 * an error code otherwise
89 *
90 *
91 * Side Effects: None
92 *
93 * Overview: This function configures the MDIX mode for the PHY.
94 *
95 * Note: None
96 *****************************************************************************/
97 eEthRes EthPhyConfigureMdix(eEthOpenFlags oFlags)
98 {
99 unsigned short phyReg;
100  
101 phyReg=EthMIIMReadReg(PHY_REG_SPECIAL_CTRL, PHY_ADDRESS)&(_SPECIALCTRL_XPOL_MASK); // mask off not used bits
102  
103 if(oFlags&ETH_OPEN_MDIX_AUTO)
104 { // enable Auto-MDIX
105 phyReg&=~_SPECIALCTRL_AMDIXCTRL_MASK;
106 }
107 else
108 { // no Auto-MDIX
109 phyReg|=_SPECIALCTRL_AMDIXCTRL_MASK; // disable Auto-MDIX
110 if(oFlags&ETH_OPEN_MDIX_SWAP)
111 {
112 phyReg|=_SPECIALCTRL_CH_SELECT_MASK; // swap
113 }
114 else
115 {
116 phyReg&=~_SPECIALCTRL_CH_SELECT_MASK; // normal
117 }
118 }
119  
120 EthMIIMWriteReg(PHY_REG_SPECIAL_CTRL, PHY_ADDRESS, phyReg);
121  
122 return ETH_RES_OK;
123  
124 }
125  
126 /****************************************************************************
127 * Function: EthPhyMIIMAddress
128 *
129 * PreCondition: None
130 *
131 * Input: None
132 *
133 * Output: PHY MIIM address
134 *
135 *
136 * Side Effects: None
137 *
138 * Overview: This function returns the address the PHY uses for MIIM transactions
139 *
140 * Note: None
141 *****************************************************************************/
142 unsigned int EthPhyMIIMAddress(void)
143 {
144 return PHY_ADDRESS;
145 }
146  
147  
148 /****************************************************************************
149 * Function: EthPhyMIIMClock
150 *
151 * PreCondition: None
152 *
153 * Input: None
154 *
155 * Output: PHY MIIM clock, Hz
156 *
157 *
158 * Side Effects: None
159 *
160 * Overview: This function returns the maximum clock frequency that the PHY can use for the MIIM transactions
161 *
162 * Note: None
163 *****************************************************************************/
164 unsigned int EthPhyMIIMClock(void)
165 {
166 return 2500000; // 2.5 MHz max clock supported
167 }
168  
169 #endif // defined(__PIC32MX__) && defined(_ETH)
170  
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