Line No. | Rev | Author | Line |
---|---|---|---|
1 | 32 | kaklik | /****************************************************************************** |
2 | |||
3 | MRF24WB0M Driver Com Layer |
||
4 | Module for Microchip TCP/IP Stack |
||
5 | -Provides access to MRF24WB0M WiFi controller |
||
6 | -Reference: MRF24WB0M Data sheet, IEEE 802.11 Standard |
||
7 | |||
8 | ******************************************************************************* |
||
9 | FileName: WFDriverCom.c |
||
10 | Dependencies: TCP/IP Stack header files |
||
11 | Processor: PIC18, PIC24F, PIC24H, dsPIC30F, dsPIC33F, PIC32 |
||
12 | Compiler: Microchip C32 v1.10b or higher |
||
13 | Microchip C30 v3.22 or higher |
||
14 | Microchip C18 v3.34 or higher |
||
15 | Company: Microchip Technology, Inc. |
||
16 | |||
17 | Software License Agreement |
||
18 | |||
19 | Copyright (C) 2002-2010 Microchip Technology Inc. All rights reserved. |
||
20 | |||
21 | Microchip licenses to you the right to use, modify, copy, and distribute: |
||
22 | (i) the Software when embedded on a Microchip microcontroller or digital |
||
23 | signal controller product ("Device") which is integrated into |
||
24 | Licensee's product; or |
||
25 | (ii) ONLY the Software driver source files ENC28J60.c, ENC28J60.h, |
||
26 | ENCX24J600.c and ENCX24J600.h ported to a non-Microchip device used in |
||
27 | conjunction with a Microchip ethernet controller for the sole purpose |
||
28 | of interfacing with the ethernet controller. |
||
29 | |||
30 | You should refer to the license agreement accompanying this Software for |
||
31 | additional information regarding your rights and obligations. |
||
32 | |||
33 | THE SOFTWARE AND DOCUMENTATION ARE PROVIDED "AS IS" WITHOUT WARRANTY OF ANY |
||
34 | KIND, EITHER EXPRESS OR IMPLIED, INCLUDING WITHOUT LIMITATION, ANY WARRANTY |
||
35 | OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE AND |
||
36 | NON-INFRINGEMENT. IN NO EVENT SHALL MICROCHIP BE LIABLE FOR ANY INCIDENTAL, |
||
37 | SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES, LOST PROFITS OR LOST DATA, COST |
||
38 | OF PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS BY |
||
39 | THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF), ANY CLAIMS |
||
40 | FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS, WHETHER ASSERTED ON |
||
41 | THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE), BREACH OF WARRANTY, OR |
||
42 | OTHERWISE. |
||
43 | |||
44 | |||
45 | Author Date Comment |
||
46 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
||
47 | KH 27 Jan 2010 Updated for MRF24WB0M |
||
48 | ******************************************************************************/ |
||
49 | |||
50 | /* |
||
51 | ********************************************************************************************************* |
||
52 | * INCLUDES |
||
53 | ********************************************************************************************************* |
||
54 | */ |
||
55 | |||
56 | #include "TCPIP Stack/WFMac.h" |
||
57 | #if defined(WF_CS_TRIS) |
||
58 | |||
59 | /* |
||
60 | ********************************************************************************************************* |
||
61 | * DEFINES |
||
62 | ********************************************************************************************************* |
||
63 | */ |
||
64 | |||
65 | /* used for assertions */ |
||
66 | #ifdef WF_DEBUG |
||
67 | #define WF_MODULE_NUMBER WF_MODULE_WF_DRIVER_COM |
||
68 | #endif |
||
69 | |||
70 | /* |
||
71 | ********************************************************************************************************* |
||
72 | * LOCAL GLOBAL VARIABLES |
||
73 | ********************************************************************************************************* |
||
74 | */ |
||
75 | |||
76 | /* Functions that are called from the External Interrupt routine use these global */ |
||
77 | /* variables instead of local variables to avoid stack corruption on CPU's that */ |
||
78 | /* that use overlay memory. See note in WFEintHandler() function. */ |
||
79 | static UINT8 g_txBuf[3]; |
||
80 | static UINT8 g_rxBuf[3]; |
||
81 | |||
82 | static UINT8 g_HostIntSaved = 0; |
||
83 | |||
84 | // Keep these as static globals instead of local variables in the Eint Handler. |
||
85 | // If declared as local variables, causes stack corruption in PIC18 |
||
86 | static UINT8 g_EintHostIntRegValue; |
||
87 | static UINT8 g_EintHostIntMaskRegValue; |
||
88 | static UINT8 g_EintHostInt; |
||
89 | |||
90 | static BOOL g_MgmtReadMsgReady; /* TRUE if rx mgmt msg to process, else FALSE */ |
||
91 | static volatile BOOL g_ExIntNeedsServicing; /* TRUE if external interrupt needs processing, else FALSE */ |
||
92 | |||
93 | tRawMoveState RawMoveState; |
||
94 | |||
95 | /* |
||
96 | ********************************************************************************************************* |
||
97 | * LOCAL FUNCTION PROTOTYPES |
||
98 | ********************************************************************************************************* |
||
99 | */ |
||
100 | |||
101 | static void ProcessMgmtRxMsg(void); |
||
102 | static void ChipReset(void); |
||
103 | static void ProcessInterruptServiceResult(void); |
||
104 | |||
105 | /***************************************************************************** |
||
106 | * FUNCTION: WFProcess |
||
107 | * |
||
108 | * RETURNS: None |
||
109 | * |
||
110 | * PARAMS: None |
||
111 | * |
||
112 | * NOTES: This function is called from WFProcess. It does the following: |
||
113 | * 1) checks for and processes MRF24WB0M external interrupt events |
||
114 | * 2) checks for and processes received management messages from the MRF24WB0M |
||
115 | * 3) maintains the PS-Poll state (if applicable) |
||
116 | * |
||
117 | *****************************************************************************/ |
||
118 | void WFProcess(void) |
||
119 | { |
||
120 | UINT16 len; |
||
121 | |||
122 | //---------------------------------------------------------- |
||
123 | // if there is a MRF24WB0M External interrupt (EINT) to process |
||
124 | //---------------------------------------------------------- |
||
125 | if (g_ExIntNeedsServicing == TRUE) |
||
126 | { |
||
127 | g_ExIntNeedsServicing = FALSE; |
||
128 | ProcessInterruptServiceResult(); |
||
129 | } |
||
130 | //---------------------------------------- |
||
131 | // else if there is management msg to read |
||
132 | //---------------------------------------- |
||
133 | else if (g_MgmtReadMsgReady == TRUE) |
||
134 | { |
||
135 | /* Ensure the MRF24WB0M is awake (only applies if PS-Poll was enabled) */ |
||
136 | EnsureWFisAwake(); |
||
137 | |||
138 | //----------------------------- |
||
139 | // process management read |
||
140 | //----------------------------- |
||
141 | // if the Raw Rx buffer is available, or only has the scratch mounted, then mount it so |
||
142 | // we can process received Mgmt message. Otherwise, stay in this state and keep checking |
||
143 | // until we can mount the Raw Rx buffer and get the management message. Once the Raw Rx |
||
144 | // is acquired, rx data packets are held off until we finish processing mgmt message. |
||
145 | if ( RawGetMgmtRxBuffer(&len) ) |
||
146 | { |
||
147 | // handle received managment message |
||
148 | g_MgmtReadMsgReady = FALSE; |
||
149 | ProcessMgmtRxMsg(); |
||
150 | |||
151 | // reenable interrupts |
||
152 | WF_EintEnable(); |
||
153 | } |
||
154 | } |
||
155 | //----------------------------------- |
||
156 | // else no EINT or Mgmt Rx to process |
||
157 | //----------------------------------- |
||
158 | else |
||
159 | { |
||
160 | #if defined (WF_USE_POWER_SAVE_FUNCTIONS) |
||
161 | /* if PS-Poll mode was enabled by application and was previously deactivated by WF driver */ |
||
162 | if (WFisPsPollEnabled() && !WFIsPsPollActive() ) |
||
163 | { |
||
164 | /* reactivate PS-Poll mode on MRF24WB0M (allow MRF24WB0M to sleep) */ |
||
165 | WFConfigureLowPowerMode(WF_LOW_POWER_MODE_ON); |
||
166 | } |
||
167 | #endif |
||
168 | } |
||
169 | } |
||
170 | |||
171 | |||
172 | /***************************************************************************** |
||
173 | * FUNCTION: ProcessInterruptServiceResult |
||
174 | * |
||
175 | * RETURNS: N/A |
||
176 | * |
||
177 | * PARAMS: |
||
178 | * N/A |
||
179 | * |
||
180 | * |
||
181 | * NOTES: Processes EXINT from MRF24WB0M. Called by WFProcess(). |
||
182 | *****************************************************************************/ |
||
183 | static void ProcessInterruptServiceResult(void) |
||
184 | { |
||
185 | UINT8 hostIntRegValue; |
||
186 | UINT8 hostIntMaskRegValue; |
||
187 | UINT8 hostInt; |
||
188 | |||
189 | /* Ensure the MRF24WB0M stays awake (only applies if PS-Poll was enabled) */ |
||
190 | EnsureWFisAwake(); |
||
191 | |||
192 | /* read hostInt register to determine cause of interrupt */ |
||
193 | hostIntRegValue = Read8BitWFRegister(WF_HOST_INTR_REG); |
||
194 | |||
195 | // or in the saved interrupts during the time when we were waiting for raw complete, set by WFEintHandler() |
||
196 | hostIntRegValue |= g_HostIntSaved; |
||
197 | |||
198 | // done with the saved interrupts, clear variable |
||
199 | g_HostIntSaved = 0; |
||
200 | |||
201 | |||
202 | hostIntMaskRegValue = Read8BitWFRegister(WF_HOST_MASK_REG); |
||
203 | |||
204 | // AND the two registers together to determine which active, enabled interrupt has occurred |
||
205 | hostInt = hostIntRegValue & hostIntMaskRegValue; |
||
206 | |||
207 | // if received a level 2 interrupt (should not happen!) |
||
208 | if((hostInt & WF_HOST_INT_MASK_INT2) == WF_HOST_INT_MASK_INT2) |
||
209 | { |
||
210 | /* read the 16 bit interrupt register */ |
||
211 | /* CURRENTLY unhandled interrupt */ |
||
212 | WF_ASSERT(FALSE); |
||
213 | WF_EintEnable(); |
||
214 | } |
||
215 | // else if got a FIFO 1 Threshold interrupt (Management Fifo) |
||
216 | else if((hostInt & WF_HOST_INT_MASK_FIFO_1_THRESHOLD) == WF_HOST_INT_MASK_FIFO_1_THRESHOLD) |
||
217 | { |
||
218 | /* clear this interrupt */ |
||
219 | Write8BitWFRegister(WF_HOST_INTR_REG, WF_HOST_INT_MASK_FIFO_1_THRESHOLD); |
||
220 | // notify MAC state machine that management message needs to be processed |
||
221 | g_MgmtReadMsgReady = TRUE; |
||
222 | } |
||
223 | // else if got a FIFO 0 Threshold Interrupt (Data Fifo) |
||
224 | else if((hostInt & WF_HOST_INT_MASK_FIFO_0_THRESHOLD) == WF_HOST_INT_MASK_FIFO_0_THRESHOLD) |
||
225 | { |
||
226 | /* clear this interrupt */ |
||
227 | Write8BitWFRegister(WF_HOST_INTR_REG, WF_HOST_INT_MASK_FIFO_0_THRESHOLD); |
||
228 | |||
229 | g_HostRAWDataPacketReceived = TRUE; /* this global flag is used in MACGetHeader() to determine a received data packet */ |
||
230 | #if defined(WF_USE_DATA_TX_RX_FUNCTIONS) |
||
231 | { |
||
232 | UINT16 rxDataPacketLength; |
||
233 | /* determine length of packet and signal the rx data packet event */ |
||
234 | rxDataPacketLength = Read16BitWFRegister(WF_HOST_RFIFO_BCNT0_REG) & 0x0fff; /* LS 12 bits are the data length */ |
||
235 | WF_ProcessEvent(WF_EVENT_RX_PACKET_RECEIVED, rxDataPacketLength); |
||
236 | } |
||
237 | #endif |
||
238 | } |
||
239 | // else got a Host interrupt that we don't handle |
||
240 | else if(hostInt) |
||
241 | { |
||
242 | /* unhandled interrupt */ |
||
243 | /* clear this interrupt */ |
||
244 | Write8BitWFRegister(WF_HOST_INTR_REG, hostInt); |
||
245 | WF_EintEnable(); |
||
246 | } |
||
247 | // we got a spurious interrupt (no bits set in register) |
||
248 | else |
||
249 | { |
||
250 | /* spurious interrupt */ |
||
251 | WF_EintEnable(); |
||
252 | } |
||
253 | } |
||
254 | |||
255 | |||
256 | /***************************************************************************** |
||
257 | * FUNCTION: Read8BitWFRegister |
||
258 | * |
||
259 | * RETURNS: register value |
||
260 | * |
||
261 | * PARAMS: |
||
262 | * regId -- ID of 8-bit register being read |
||
263 | * |
||
264 | * NOTES: Reads WF 8-bit register |
||
265 | *****************************************************************************/ |
||
266 | UINT8 Read8BitWFRegister(UINT8 regId) |
||
267 | { |
||
268 | g_txBuf[0] = regId | WF_READ_REGISTER_MASK; |
||
269 | WF_SpiEnableChipSelect(); |
||
270 | |||
271 | WFSpiTxRx(g_txBuf, |
||
272 | 1, |
||
273 | g_rxBuf, |
||
274 | 2); |
||
275 | |||
276 | WF_SpiDisableChipSelect(); |
||
277 | |||
278 | return g_rxBuf[1]; /* register value returned in the second byte clocking */ |
||
279 | } |
||
280 | |||
281 | /***************************************************************************** |
||
282 | * FUNCTION: Write8BitWFRegister |
||
283 | * |
||
284 | * RETURNS: None |
||
285 | * |
||
286 | * PARAMS: |
||
287 | * regId -- ID of 8-bit register being written to |
||
288 | * value -- value to write |
||
289 | * |
||
290 | * NOTES: Writes WF 8-bit register |
||
291 | *****************************************************************************/ |
||
292 | void Write8BitWFRegister(UINT8 regId, UINT8 value) |
||
293 | { |
||
294 | g_txBuf[0] = regId | WF_WRITE_REGISTER_MASK; |
||
295 | g_txBuf[1] = value; |
||
296 | |||
297 | WF_SpiEnableChipSelect(); |
||
298 | |||
299 | WFSpiTxRx(g_txBuf, |
||
300 | 2, |
||
301 | g_rxBuf, |
||
302 | 1); |
||
303 | |||
304 | WF_SpiDisableChipSelect(); |
||
305 | } |
||
306 | |||
307 | /***************************************************************************** |
||
308 | * FUNCTION: Read16BitWFRegister |
||
309 | * |
||
310 | * RETURNS: register value |
||
311 | * |
||
312 | * PARAMS: |
||
313 | * regId -- ID of 16-bit register being read |
||
314 | * |
||
315 | * NOTES: Reads WF 16-bit register |
||
316 | *****************************************************************************/ |
||
317 | UINT16 Read16BitWFRegister(UINT8 regId) |
||
318 | { |
||
319 | g_txBuf[0] = regId | WF_READ_REGISTER_MASK; |
||
320 | WF_SpiEnableChipSelect(); |
||
321 | |||
322 | WFSpiTxRx(g_txBuf, |
||
323 | 1, |
||
324 | g_rxBuf, |
||
325 | 3); |
||
326 | |||
327 | WF_SpiDisableChipSelect(); |
||
328 | |||
329 | return (((UINT16)g_rxBuf[1]) << 8) | ((UINT16)(g_rxBuf[2])); |
||
330 | } |
||
331 | |||
332 | /***************************************************************************** |
||
333 | * FUNCTION: Write16BitWFRegister |
||
334 | * |
||
335 | * RETURNS: None |
||
336 | * |
||
337 | * PARAMS: |
||
338 | * regId -- ID of 16-bit register being written to |
||
339 | * value -- value to write |
||
340 | * |
||
341 | * NOTES: Writes WF 16-bit register |
||
342 | *****************************************************************************/ |
||
343 | void Write16BitWFRegister(UINT8 regId, UINT16 value) |
||
344 | { |
||
345 | g_txBuf[0] = regId | WF_WRITE_REGISTER_MASK; |
||
346 | g_txBuf[1] = (UINT8)(value >> 8); /* MS byte being written */ |
||
347 | g_txBuf[2] = (UINT8)(value & 0x00ff); /* LS byte being written */ |
||
348 | |||
349 | WF_SpiEnableChipSelect(); |
||
350 | |||
351 | WFSpiTxRx(g_txBuf, |
||
352 | 3, |
||
353 | g_rxBuf, |
||
354 | 1); |
||
355 | |||
356 | WF_SpiDisableChipSelect(); |
||
357 | } |
||
358 | |||
359 | /***************************************************************************** |
||
360 | * FUNCTION: WriteWFArray |
||
361 | * |
||
362 | * RETURNS: None |
||
363 | * |
||
364 | * PARAMS: |
||
365 | * regId -- Raw register being written to |
||
366 | * pBuf -- pointer to array of bytes being written |
||
367 | * length -- number of bytes in pBuf |
||
368 | * |
||
369 | * NOTES: Writes a data block to specified raw register |
||
370 | *****************************************************************************/ |
||
371 | void WriteWFArray(UINT8 regId, UINT8 *p_Buf, UINT16 length) |
||
372 | { |
||
373 | g_txBuf[0] = regId; |
||
374 | |||
375 | WF_SpiEnableChipSelect(); |
||
376 | |||
377 | /* output cmd byte */ |
||
378 | WFSpiTxRx(g_txBuf, |
||
379 | 1, |
||
380 | g_rxBuf, |
||
381 | 1); |
||
382 | |||
383 | /* output data array bytes */ |
||
384 | WFSpiTxRx(p_Buf, |
||
385 | length, |
||
386 | g_rxBuf, |
||
387 | 1); |
||
388 | |||
389 | WF_SpiDisableChipSelect(); |
||
390 | } |
||
391 | |||
392 | /***************************************************************************** |
||
393 | * FUNCTION: ReadWFArray |
||
394 | * |
||
395 | * RETURNS: None |
||
396 | * |
||
397 | * PARAMS: |
||
398 | * regId -- Raw register being read from |
||
399 | * pBuf -- pointer where to write out bytes |
||
400 | * length -- number of bytes to read |
||
401 | * |
||
402 | * NOTES: Reads a block of data from a raw register |
||
403 | *****************************************************************************/ |
||
404 | void ReadWFArray(UINT8 regId, UINT8 *p_Buf, UINT16 length) |
||
405 | { |
||
406 | WF_SpiEnableChipSelect(); |
||
407 | |||
408 | /* output command byte */ |
||
409 | g_txBuf[0] = regId | WF_READ_REGISTER_MASK; |
||
410 | WFSpiTxRx(g_txBuf, |
||
411 | 1, |
||
412 | g_rxBuf, |
||
413 | 1); |
||
414 | |||
415 | /* read data array */ |
||
416 | WFSpiTxRx(g_txBuf, |
||
417 | 1, /* garbage tx byte */ |
||
418 | p_Buf, |
||
419 | length); |
||
420 | |||
421 | WF_SpiDisableChipSelect(); |
||
422 | } |
||
423 | |||
424 | #if defined (__18CXX) |
||
425 | /***************************************************************************** |
||
426 | * FUNCTION: WriteWFROMArray |
||
427 | * |
||
428 | * RETURNS: None |
||
429 | * |
||
430 | * PARAMS: |
||
431 | * regId -- Raw register being written to |
||
432 | * pBuf -- pointer to array of bytes being written |
||
433 | * length -- number of bytes in pBuf |
||
434 | * |
||
435 | * NOTES: Writes a data block (in ROM) to specified raw register. This function |
||
436 | * is only needed for the Microchip PIC18. |
||
437 | *****************************************************************************/ |
||
438 | void WriteWFROMArray(UINT8 regId, ROM UINT8 *p_Buf, UINT16 length) |
||
439 | { |
||
440 | g_txBuf[0] = regId; |
||
441 | |||
442 | WF_SpiEnableChipSelect(); |
||
443 | |||
444 | /* output cmd byte */ |
||
445 | WFSpiTxRx(g_txBuf, |
||
446 | 1, |
||
447 | g_rxBuf, |
||
448 | 1); |
||
449 | |||
450 | /* output data array bytes */ |
||
451 | WFSpiTxRx_Rom(p_Buf, |
||
452 | length, |
||
453 | g_rxBuf, |
||
454 | 1); |
||
455 | |||
456 | |||
457 | WF_SpiDisableChipSelect(); |
||
458 | } |
||
459 | #endif |
||
460 | |||
461 | #include "TCPIP Stack/TCPIP.h" |
||
462 | |||
463 | |||
464 | |||
465 | /***************************************************************************** |
||
466 | * FUNCTION: ChipReset |
||
467 | * |
||
468 | * RETURNS: N/A |
||
469 | * |
||
470 | * PARAMS: |
||
471 | * N/A |
||
472 | * |
||
473 | * |
||
474 | * NOTES: Performs the necessary SPI operations to cause the MRF24WB0M to reset. |
||
475 | * This function also implements a delay so that it will not return until |
||
476 | * the MRF24WB0M is ready to receive messages again. The delay time will |
||
477 | * vary depending on the amount of code that must be loaded from serial |
||
478 | * flash. |
||
479 | *****************************************************************************/ |
||
480 | static void ChipReset(void) |
||
481 | { |
||
482 | UINT16 value; |
||
483 | UINT32 timeoutPeriod; |
||
484 | UINT32 startTickCount; |
||
485 | |||
486 | timeoutPeriod = TICKS_PER_SECOND; /* 1000 ms */ |
||
487 | |||
488 | #if 0 |
||
489 | /* THIS WAS OLD RESET CODE, BUT DOES NOT APPEAR TO WORK ON PICTAILS */ |
||
490 | // Enable regulator |
||
491 | XCEN33_IO = 0; // Set low to enable regulator |
||
492 | XCEN33_TRIS = 0; // Configure line as ouput |
||
493 | DelayMs(10); // wait a little |
||
494 | |||
495 | // take MRF24WB0M out of reset |
||
496 | WF_RST_IO = 0; // put the line in reset state |
||
497 | WF_RST_TRIS = 0; // configure the I/O as an output |
||
498 | DelayMs(10); // wait a little |
||
499 | WF_RST_IO = 1; // take MRF24WB0M out of reset |
||
500 | DelayMs(10); // wait a little |
||
501 | |||
502 | /* END TEST CODE */ |
||
503 | #endif |
||
504 | |||
505 | /* needed for Microchip PICTail (chip enable active low) */ |
||
506 | WF_SetCE_N(WF_LOW); /* set low to enable regulator */ |
||
507 | |||
508 | /* remove MRF24WB0M from reset */ |
||
509 | WF_SetRST_N(WF_HIGH); |
||
510 | |||
511 | /* clear the power bit to disable low power mode on the MRF24WB0M */ |
||
512 | Write16BitWFRegister(WF_PSPOLL_H_REG, 0x0000); |
||
513 | |||
514 | /* perform hard reset on MRF24WB0M */ |
||
515 | Write16BitWFRegister(WF_INDEX_ADDR_REG, WF_CONFIG_CTRL0_REG); |
||
516 | Write16BitWFRegister(WF_INDEX_DATA_REG, 0x80ff); |
||
517 | Write16BitWFRegister(WF_INDEX_ADDR_REG, WF_CONFIG_CTRL0_REG); |
||
518 | Write16BitWFRegister(WF_INDEX_DATA_REG, 0x0fff); |
||
519 | |||
520 | /* after reset is started poll register to determine when HW reset has completed */ |
||
521 | startTickCount = (UINT32)TickGet(); |
||
522 | do |
||
523 | { |
||
524 | Write16BitWFRegister(WF_INDEX_ADDR_REG, WF_HW_STATUS_REG); |
||
525 | value = Read16BitWFRegister(WF_INDEX_DATA_REG); |
||
526 | if (TickGet() - startTickCount >= timeoutPeriod) |
||
527 | { |
||
528 | WF_ASSERT(FALSE); |
||
529 | } |
||
530 | } while ( (value & WF_HW_STATUS_NOT_IN_RESET_MASK) == 0); |
||
531 | |||
532 | |||
533 | /* if SPI not connected will read all 1's */ |
||
534 | WF_ASSERT(value != 0xffff); |
||
535 | |||
536 | /* now that chip has come out of HW reset, poll the FIFO byte count register */ |
||
537 | /* which will be set to a non-zero value when the MRF24WB0M initialization is */ |
||
538 | /* complete. */ |
||
539 | startTickCount = (UINT32)TickGet(); |
||
540 | do |
||
541 | { |
||
542 | value = Read16BitWFRegister(WF_HOST_WFIFO_BCNT0_REG); |
||
543 | if (TickGet() - startTickCount >= timeoutPeriod) |
||
544 | { |
||
545 | WF_ASSERT(FALSE); |
||
546 | } |
||
547 | } while (value == 0); |
||
548 | |||
549 | } |
||
550 | |||
551 | /***************************************************************************** |
||
552 | * FUNCTION: HostInterrupt2RegInit |
||
553 | * |
||
554 | * RETURNS: N/A |
||
555 | * |
||
556 | * PARAMS: |
||
557 | * hostIntrMaskRegMask - The bit mask to be modified. |
||
558 | * state - One of WF_INT_DISABLE, WF_INT_ENABLE where |
||
559 | * Disable implies clearing the bits and enable sets the bits. |
||
560 | * |
||
561 | * |
||
562 | * NOTES: Initializes the 16-bit Host Interrupt register on the MRF24WB0M with the |
||
563 | * specified mask value either setting or clearing the mask register |
||
564 | * as determined by the input parameter state. |
||
565 | *****************************************************************************/ |
||
566 | static void HostInterrupt2RegInit(UINT16 hostIntMaskRegMask, |
||
567 | UINT8 state) |
||
568 | { |
||
569 | UINT16 int2MaskValue; |
||
570 | |||
571 | /* Host Int Register is a status register where each bit indicates a specific event */ |
||
572 | /* has occurred. In addition, writing a 1 to a bit location in this register clears */ |
||
573 | /* the event. */ |
||
574 | |||
575 | /* Host Int Mask Register is used to enable those events activated in Host Int Register */ |
||
576 | /* to cause an interrupt to the host */ |
||
577 | |||
578 | /* read current state of int2 mask reg */ |
||
579 | int2MaskValue = Read16BitWFRegister(WF_HOST_INTR2_MASK_REG); |
||
580 | |||
581 | /* if caller is disabling a set of interrupts */ |
||
582 | if (state == WF_INT_DISABLE) |
||
583 | { |
||
584 | /* zero out that set of interrupts in the interrupt mask copy */ |
||
585 | int2MaskValue &= ~hostIntMaskRegMask; |
||
586 | } |
||
587 | /* else caller is enabling a set of interrupts */ |
||
588 | else |
||
589 | { |
||
590 | /* set to 1 that set of interrupts in the interrupt mask copy */ |
||
591 | int2MaskValue |= hostIntMaskRegMask; |
||
592 | } |
||
593 | |||
594 | /* write out new interrupt mask value */ |
||
595 | Write16BitWFRegister(WF_HOST_INTR2_MASK_REG, int2MaskValue); |
||
596 | |||
597 | /* ensure that pending interrupts from those updated interrupts are cleared */ |
||
598 | Write16BitWFRegister(WF_HOST_INTR2_REG, hostIntMaskRegMask); |
||
599 | |||
600 | } |
||
601 | |||
602 | /***************************************************************************** |
||
603 | * FUNCTION: HostInterruptRegInit |
||
604 | * |
||
605 | * RETURNS: N/A |
||
606 | * |
||
607 | * PARAMS: |
||
608 | * hostIntrMaskRegMask - The bit mask to be modified. |
||
609 | * state - one of WF_EXINT_DISABLE, WF_EXINT_ENABLE where |
||
610 | * Disable implies clearing the bits and enable sets the bits. |
||
611 | * |
||
612 | * |
||
613 | * NOTES: Initializes the 8-bit Host Interrupt register on the MRF24WB0M with the |
||
614 | * specified mask value either setting or clearing the mask register |
||
615 | * as determined by the input parameter state. The process requires |
||
616 | * 2 spi operations which are performed in a blocking fashion. The |
||
617 | * function does not return until both spi operations have completed. |
||
618 | *****************************************************************************/ |
||
619 | static void HostInterruptRegInit(UINT8 hostIntrMaskRegMask, |
||
620 | UINT8 state) |
||
621 | { |
||
622 | UINT8 hostIntMaskValue; |
||
623 | |||
624 | /* Host Int Register is a status register where each bit indicates a specific event */ |
||
625 | /* has occurred. In addition, writing a 1 to a bit location in this register clears */ |
||
626 | /* the event. */ |
||
627 | |||
628 | /* Host Int Mask Register is used to enable those events activated in Host Int Register */ |
||
629 | /* to cause an interrupt to the host */ |
||
630 | |||
631 | /* read current state of Host Interrupt Mask register */ |
||
632 | hostIntMaskValue = Read8BitWFRegister(WF_HOST_MASK_REG); |
||
633 | |||
634 | /* if caller is disabling a set of interrupts */ |
||
635 | if (state == WF_INT_DISABLE) |
||
636 | { |
||
637 | /* zero out that set of interrupts in the interrupt mask copy */ |
||
638 | hostIntMaskValue = (hostIntMaskValue & ~hostIntrMaskRegMask); |
||
639 | } |
||
640 | /* else caller is enabling a set of interrupts */ |
||
641 | else |
||
642 | { |
||
643 | /* set to 1 that set of interrupts in the interrupt mask copy */ |
||
644 | hostIntMaskValue = (hostIntMaskValue & ~hostIntrMaskRegMask) | hostIntrMaskRegMask; |
||
645 | } |
||
646 | |||
647 | /* write out new interrupt mask value */ |
||
648 | Write8BitWFRegister(WF_HOST_MASK_REG, hostIntMaskValue); |
||
649 | |||
650 | /* ensure that pending interrupts from those updated interrupts are cleared */ |
||
651 | Write8BitWFRegister(WF_HOST_INTR_REG, hostIntrMaskRegMask); |
||
652 | |||
653 | |||
654 | } |
||
655 | |||
656 | |||
657 | /***************************************************************************** |
||
658 | * FUNCTION: WFEintHandler |
||
659 | * |
||
660 | * RETURNS: N/A |
||
661 | * |
||
662 | * PARAMS: |
||
663 | * N/A |
||
664 | * |
||
665 | * |
||
666 | * NOTES: This function must be called once, each time an external interrupt |
||
667 | * is received from the WiFi device. The WiFi Driver will schedule any |
||
668 | * subsequent SPI communication to process the interrupt. |
||
669 | * |
||
670 | * IMPORTANT NOTE: This function, and functions that are called by this function |
||
671 | * must NOT use local variables. The PIC18, or any other processor |
||
672 | * that uses overlay memory will corrupt the logical stack within |
||
673 | * overlay memory if the interrupt uses local variables. |
||
674 | * If local variables are used within an interrupt routine the toolchain |
||
675 | * cannot properly determine how not to overwrite local variables in |
||
676 | * non-interrupt releated functions, specifically the function that was |
||
677 | * interrupted. |
||
678 | *****************************************************************************/ |
||
679 | void WFEintHandler(void) |
||
680 | { |
||
681 | /*--------------------------------------------------------*/ |
||
682 | /* if driver is waiting for a RAW Move Complete interrupt */ |
||
683 | /*--------------------------------------------------------*/ |
||
684 | if (RawMoveState.waitingForRawMoveCompleteInterrupt) |
||
685 | { |
||
686 | /* read hostInt register and hostIntMask register to determine cause of interrupt */ |
||
687 | g_EintHostIntRegValue = Read8BitWFRegister(WF_HOST_INTR_REG); |
||
688 | g_EintHostIntMaskRegValue = Read8BitWFRegister(WF_HOST_MASK_REG); |
||
689 | |||
690 | // AND the two registers together to determine which active, enabled interrupt has occurred |
||
691 | g_EintHostInt = g_EintHostIntRegValue & g_EintHostIntMaskRegValue; |
||
692 | |||
693 | /* if a RAW0 or RAW1 interrupt occurred, signifying RAW Move completed */ |
||
694 | if(g_EintHostInt & (WF_HOST_INT_MASK_RAW_0_INT_0 | WF_HOST_INT_MASK_RAW_1_INT_0)) |
||
695 | { |
||
696 | /* save the copy of the active interrupts */ |
||
697 | RawMoveState.rawInterrupt = g_EintHostInt; |
||
698 | RawMoveState.waitingForRawMoveCompleteInterrupt = FALSE; |
||
699 | |||
700 | /* if no other interrupts occurred other than a RAW0 or RAW1 interrupt */ |
||
701 | if((g_EintHostInt & ~(WF_HOST_INT_MASK_RAW_0_INT_0 | WF_HOST_INT_MASK_RAW_1_INT_0)) == 0u) |
||
702 | { |
||
703 | /* clear the RAW interrupts, re-enable interrupts, and exit */ |
||
704 | Write8BitWFRegister(WF_HOST_INTR_REG, (WF_HOST_INT_MASK_RAW_0_INT_0 | WF_HOST_INT_MASK_RAW_1_INT_0)); |
||
705 | WF_EintEnable(); |
||
706 | return; |
||
707 | } |
||
708 | /* else we got a RAW0 or RAW1 interrupt, but, there is also at least one other interrupt present */ |
||
709 | else |
||
710 | { |
||
711 | // save the other interrupts and clear them for now |
||
712 | // keep interrupts disabled |
||
713 | g_HostIntSaved |= (g_EintHostInt & ~(WF_HOST_INT_MASK_RAW_0_INT_0 | WF_HOST_INT_MASK_RAW_1_INT_0)); |
||
714 | Write8BitWFRegister(WF_HOST_INTR_REG, g_EintHostInt); |
||
715 | } |
||
716 | } |
||
717 | /*----------------------------------------------------------------------------------*/ |
||
718 | /* else we did not get a RAW interrupt, but we did get at least one other interrupt */ |
||
719 | /*----------------------------------------------------------------------------------*/ |
||
720 | else |
||
721 | { |
||
722 | g_HostIntSaved |= g_EintHostInt; |
||
723 | Write8BitWFRegister(WF_HOST_INTR_REG, g_EintHostInt); |
||
724 | WF_EintEnable(); |
||
725 | } |
||
726 | } |
||
727 | |||
728 | // Once we're in here, external interrupts have already been disabled so no need to call WF_EintDisable() in here |
||
729 | |||
730 | /* notify state machine that an interrupt occurred */ |
||
731 | g_ExIntNeedsServicing = TRUE; |
||
732 | } |
||
733 | |||
734 | |||
735 | /***************************************************************************** |
||
736 | * FUNCTION: WFHardwareInit |
||
737 | * |
||
738 | * RETURNS: error code |
||
739 | * |
||
740 | * PARAMS: None |
||
741 | * |
||
742 | * NOTES: Initializes CPU Host hardware interfaces (SPI, External Interrupt). |
||
743 | * Also resets the MRF24WB0M. |
||
744 | *****************************************************************************/ |
||
745 | void WFHardwareInit(void) |
||
746 | { |
||
747 | g_MgmtReadMsgReady = FALSE; |
||
748 | g_ExIntNeedsServicing = FALSE; |
||
749 | |||
750 | RawMoveState.rawInterrupt = 0; |
||
751 | RawMoveState.waitingForRawMoveCompleteInterrupt = FALSE; /* not waiting for RAW move complete */ |
||
752 | |||
753 | /* initialize the SPI interface */ |
||
754 | WF_SpiInit(); |
||
755 | |||
756 | /* Reset the MRF24WB0M (using SPI bus to write/read MRF24WB0M registers */ |
||
757 | ChipReset(); |
||
758 | |||
759 | /* disable the interrupts gated by the 16-bit host int register */ |
||
760 | HostInterrupt2RegInit(WF_HOST_2_INT_MASK_ALL_INT, WF_INT_DISABLE); |
||
761 | |||
762 | /* disable the interrupts gated the by main 8-bit host int register */ |
||
763 | HostInterruptRegInit(WF_HOST_INT_MASK_ALL_INT, WF_INT_DISABLE); |
||
764 | |||
765 | /* Initialize the External Interrupt for the MRF24WB0M allowing the MRF24WB0M to interrupt |
||
766 | * the Host from this point forward. */ |
||
767 | WF_EintInit(); |
||
768 | WF_EintEnable(); |
||
769 | |||
770 | /* enable the following MRF24WB0M interrupts */ |
||
771 | HostInterruptRegInit((WF_HOST_INT_MASK_FIFO_1_THRESHOLD | /* Mgmt Rx Msg interrupt */ |
||
772 | WF_HOST_INT_MASK_FIFO_0_THRESHOLD | /* Data Rx Msg interrupt */ |
||
773 | WF_HOST_INT_MASK_RAW_0_INT_0 | /* RAW0 Move Complete interrupt */ |
||
774 | WF_HOST_INT_MASK_RAW_1_INT_0), /* RAW1 Move Complete interrupt */ |
||
775 | WF_INT_ENABLE); |
||
776 | |||
777 | /* Disable PS-Poll mode */ |
||
778 | WFConfigureLowPowerMode(WF_LOW_POWER_MODE_OFF); |
||
779 | |||
780 | } |
||
781 | |||
782 | |||
783 | |||
784 | static void ProcessMgmtRxMsg(void) |
||
785 | { |
||
786 | UINT8 msgType; |
||
787 | |||
788 | /* read first byte from Mgmt Rx message (msg type) */ |
||
789 | RawRead(RAW_RX_ID, 0, 1, &msgType); |
||
790 | |||
791 | /* if not a management response or management indicate then fatal error */ |
||
792 | WF_ASSERT( (msgType == WF_MGMT_CONFIRM_TYPE) || (msgType == WF_MGMT_INDICATE_TYPE) ); |
||
793 | |||
794 | if (msgType == WF_MGMT_CONFIRM_TYPE) |
||
795 | { |
||
796 | /* signal that a mgmt response has been received */ |
||
797 | SignalMgmtConfirmReceivedEvent(); |
||
798 | } |
||
799 | else /* must be WF_MGMT_INDICATE_TYPE */ |
||
800 | { |
||
801 | /* handle the mgmt indicate */ |
||
802 | WFProcessMgmtIndicateMsg(); |
||
803 | } |
||
804 | } |
||
805 | |||
806 | |||
807 | #else |
||
808 | // dummy func to keep compiler happy when module has no executeable code |
||
809 | void WFDriverCom_EmptyFunc(void) |
||
810 | { |
||
811 | } |
||
812 | |||
813 | #endif /* WF_CS_TRIS */ |
||
814 | |||
815 | |||
816 | |||
817 |
Powered by WebSVN v2.8.3