| Line No. | Rev | Author | Line |
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| 1 | 32 | kaklik | |
| 2 | /****************************************************************************** |
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| 3 | |||
| 4 | USB PIC24-Specific Header |
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| 5 | |||
| 6 | This file defines PIC24-specific items. |
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| 7 | |||
| 8 | Software License Agreement |
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| 9 | |||
| 10 | The software supplied herewith by Microchip Technology Incorporated |
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| 11 | (the Company) for its PICmicro® Microcontroller is intended and |
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| 12 | supplied to you, the Companys customer, for use solely and |
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| 13 | exclusively on Microchip PICmicro Microcontroller products. The |
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| 14 | software is owned by the Company and/or its supplier, and is |
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| 15 | protected under applicable copyright laws. All rights are reserved. |
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| 16 | Any use in violation of the foregoing restrictions may subject the |
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| 17 | user to criminal sanctions under applicable laws, as well as to |
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| 18 | civil liability for the breach of the terms and conditions of this |
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| 19 | license. |
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| 20 | |||
| 21 | THIS SOFTWARE IS PROVIDED IN AN AS IS CONDITION. NO WARRANTIES, |
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| 22 | WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED |
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| 23 | TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A |
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| 24 | PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. THE COMPANY SHALL NOT, |
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| 25 | IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL OR |
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| 26 | CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. |
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| 27 | |||
| 28 | Change History: |
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| 29 | Rev Description |
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| 30 | ---------- ---------------------------------------------------------- |
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| 31 | 2.6 - 2.7a No change |
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| 32 | |||
| 33 | *******************************************************************************/ |
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| 34 | |||
| 35 | // To Do: Put all PIC24-specific USB HW definitions here, |
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| 36 | |||
| 37 | #if defined(USB_SUPPORT_HOST) && !defined(USB_SUPPORT_OTG) |
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| 38 | //#error |
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| 39 | #define KVA_TO_PA(v) v |
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| 40 | #define PA_TO_KVA0(pa) pa |
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| 41 | #define PA_TO_KVA1(pa) pa |
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| 42 | #define GET_PHYSICAL_ADDRESS(v) (v) |
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| 43 | |||
| 44 | |||
| 45 | /* translate betwwen KSEG0 and KSEG1 virtual addresses */ |
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| 46 | #define KVA0_TO_KVA1(v) ((v) | 0x20000000) |
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| 47 | #define KVA1_TO_KVA0(v) ((v) & ~0x20000000) |
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| 48 | |||
| 49 | |||
| 50 | /******************************************************************** |
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| 51 | * USB - PIC Endpoint Definitions |
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| 52 | * PIC Endpoint Address Format: X:EP3:EP2:EP1:EP0:DIR:PPBI:X |
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| 53 | * This is used when checking the value read from USTAT |
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| 54 | * |
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| 55 | * NOTE: These definitions are not used in the descriptors. |
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| 56 | * EP addresses used in the descriptors have different format. |
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| 57 | *******************************************************************/ |
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| 58 | #define USTAT_EP0_PP_MASK ~0x04 |
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| 59 | #define USTAT_EP_MASK 0xFC |
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| 60 | #define USTAT_EP0_OUT 0x00 |
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| 61 | #define USTAT_EP0_OUT_EVEN 0x00 |
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| 62 | #define USTAT_EP0_OUT_ODD 0x04 |
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| 63 | |||
| 64 | #define USTAT_EP0_IN 0x08 |
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| 65 | #define USTAT_EP0_IN_EVEN 0x08 |
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| 66 | #define USTAT_EP0_IN_ODD 0x0C |
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| 67 | |||
| 68 | |||
| 69 | //****************************************************************************** |
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| 70 | // USB Endpoint Control Registers |
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| 71 | // |
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| 72 | // In USB Host mode, only EP0 control registers are used. The other registers |
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| 73 | // should be disabled. |
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| 74 | //****************************************************************************** |
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| 75 | /*typedef union |
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| 76 | { |
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| 77 | WORD UEP[16]; |
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| 78 | } _UEP;*/ |
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| 79 | |||
| 80 | #define UEP_STALL 0x0002 |
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| 81 | |||
| 82 | |||
| 83 | /******************************************************************** |
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| 84 | * Buffer Descriptor Status Register |
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| 85 | *******************************************************************/ |
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| 86 | |||
| 87 | /* Buffer Descriptor Status Register Initialization Parameters */ |
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| 88 | |||
| 89 | #if !defined(USB_SUPPORT_DEVICE) |
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| 90 | //The _BSTALL definition is changed from 0x04 to 0x00 to |
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| 91 | // fix a difference in the PIC18 and PIC24 definitions of this |
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| 92 | // bit. This should be changed back once the definitions are |
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| 93 | // synced. |
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| 94 | #define _BSTALL 0x04 //Buffer Stall enable |
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| 95 | #define _DTSEN 0x08 //Data Toggle Synch enable |
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| 96 | #define _DAT0 0x00 //DATA0 packet expected next |
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| 97 | #define _DAT1 0x40 //DATA1 packet expected next |
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| 98 | #define _DTSMASK 0x40 //DTS Mask |
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| 99 | #define _USIE 0x80 //SIE owns buffer |
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| 100 | #define _UCPU 0x00 //CPU owns buffer |
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| 101 | |||
| 102 | #define _STAT_MASK 0xFC |
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| 103 | |||
| 104 | // Buffer Descriptor Status Register layout. |
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| 105 | typedef union _BD_STAT |
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| 106 | { |
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| 107 | struct{ |
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| 108 | unsigned :2; //Byte count |
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| 109 | unsigned BSTALL :1; //Buffer Stall Enable |
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| 110 | unsigned DTSEN :1; //Data Toggle Synch Enable |
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| 111 | unsigned :2; //Reserved - write as 00 |
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| 112 | unsigned DTS :1; //Data Toggle Synch Value |
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| 113 | unsigned UOWN :1; //USB Ownership |
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| 114 | }; |
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| 115 | struct{ |
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| 116 | unsigned :2; |
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| 117 | unsigned PID0 :1; |
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| 118 | unsigned PID1 :1; |
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| 119 | unsigned PID2 :1; |
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| 120 | unsigned PID3 :1; |
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| 121 | }; |
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| 122 | struct{ |
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| 123 | unsigned :2; |
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| 124 | unsigned PID :4; // Packet Identifier |
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| 125 | }; |
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| 126 | BYTE Val; |
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| 127 | } BD_STAT; //Buffer Descriptor Status Register |
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| 128 | |||
| 129 | /******************************************************************** |
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| 130 | * Buffer Descriptor Table Mapping |
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| 131 | *******************************************************************/ |
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| 132 | // BDT Entry Layout |
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| 133 | typedef union __BDT |
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| 134 | { |
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| 135 | union |
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| 136 | { |
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| 137 | struct |
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| 138 | { |
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| 139 | BYTE CNT __attribute__ ((packed)); |
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| 140 | BD_STAT STAT __attribute__ ((packed)); |
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| 141 | }; |
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| 142 | struct |
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| 143 | { |
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| 144 | WORD count:10; //test |
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| 145 | BYTE :6; |
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| 146 | BYTE* ADR; //Buffer Address |
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| 147 | }; |
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| 148 | }; |
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| 149 | DWORD Val; |
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| 150 | WORD v[2]; |
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| 151 | } BDT_ENTRY; |
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| 152 | #endif |
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| 153 | |||
| 154 | |||
| 155 | /* Register Abstractions |
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| 156 | ************************************************************************* |
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| 157 | */ |
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| 158 | |||
| 159 | #define USBSetBDTAddress(addr) U1BDTP1 = (((unsigned int)addr)/256); |
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| 160 | #define USBPowerModule() U1PWRCbits.USBPWR = 1; |
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| 161 | #define USBPingPongBufferReset U1CONbits.PPBRST |
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| 162 | |||
| 163 | //#define USBTransactionCompleteIE U1IEbits.TRNIE |
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| 164 | //#define USBTransactionCompleteIF U1IRbits.TRNIF |
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| 165 | //#define USBTransactionCompleteIFReg (BYTE*)&U1IR |
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| 166 | //#define USBTransactionCompleteIFBitNum 3 |
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| 167 | |||
| 168 | #define USBResetIE U1IEbits.URSTIE |
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| 169 | #define USBResetIF U1IRbits.URSTIF |
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| 170 | #define USBResetIFReg (BYTE*)&U1IR |
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| 171 | #define USBResetIFBitNum 0 |
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| 172 | |||
| 173 | #define USBIdleIE U1IEbits.IDLEIE |
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| 174 | #define USBIdleIF U1IRbits.IDLEIF |
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| 175 | #define USBIdleIFReg (BYTE*)&U1IR |
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| 176 | #define USBIdleIFBitNum 4 |
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| 177 | |||
| 178 | #define USBActivityIE U1OTGIEbits.ACTVIE |
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| 179 | #define USBActivityIF U1OTGIRbits.ACTVIF |
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| 180 | #define USBActivityIFReg (BYTE*)&U1OTGIR |
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| 181 | #define USBActivityIFBitNum 4 |
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| 182 | |||
| 183 | #define USBSOFIE U1IEbits.SOFIE |
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| 184 | #define USBSOFIF U1IRbits.SOFIF |
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| 185 | #define USBSOFIFReg (BYTE*)&U1IR |
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| 186 | #define USBSOFIFBitNum 2 |
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| 187 | |||
| 188 | #define USBStallIE U1IEbits.STALLIE |
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| 189 | #define USBStallIF U1IRbits.STALLIF |
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| 190 | #define USBStallIFReg (BYTE*)&U1IR |
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| 191 | #define USBStallIFBitNum 7 |
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| 192 | |||
| 193 | #define USBErrorIE U1IEbits.UERRIE |
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| 194 | #define USBErrorIF U1IRbits.UERRIF |
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| 195 | #define USBErrorIFReg (BYTE*)&U1IR |
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| 196 | #define USBErrorIFBitNum 1 |
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| 197 | |||
| 198 | //#define USBSE0Event U1CONbits.SE0 |
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| 199 | #define USBSuspendControl U1PWRCbits.USUSPEND |
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| 200 | #define USBPacketDisable U1CONbits.PKTDIS |
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| 201 | #define USBResumeControl U1CONbits.RESUME |
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| 202 | |||
| 203 | #define USBT1MSECIE U1OTGIEbits.T1MSECIE |
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| 204 | #define USBT1MSECIF U1OTGIRbits.T1MSECIF |
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| 205 | #define USBT1MSECIFReg (BYTE*)&U1OTGIR |
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| 206 | #define USBT1MSECIFBitNum 6 |
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| 207 | |||
| 208 | #define USBIDIE U1OTGIEbits.IDIE |
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| 209 | #define USBIDIF U1OTGIRbits.IDIF |
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| 210 | #define USBIDIFReg (BYTE*)&U1OTGIR |
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| 211 | #define USBIDIFBitNum 7 |
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| 212 | |||
| 213 | #define USB_PING_PONG__ALL_BUT_EP0 0x03 // U1CFG1 - Ping-pong on all endpoints except EP0 |
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| 214 | #define USB_PING_PONG__FULL_PING_PONG 0x02 // U1CFG1 - Ping-pong on all endpoints |
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| 215 | #define USB_PING_PONG__EP0_OUT_ONLY 0x01 // U1CFG1 - Ping-pong on EP 0 out only |
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| 216 | #define USB_PING_PONG__NO_PING_PONG 0x00 // U1CFG1 - No ping-pong |
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| 217 | |||
| 218 | #endif |
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