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10 <h1>cs8900.h</h1><a href="cs8900_8h.html">Go to the documentation of this file.</a><div class="fragment"><pre class="fragment">00001 <span class="comment">/*! \file cs8900.h \brief Crystal CS8900 Ethernet Interface Driver. */</span>
11 00002 <span class="comment">//*****************************************************************************</span>
12 00003 <span class="comment">//</span>
13 00004 <span class="comment">// File Name : 'cs8900.h'</span>
14 00005 <span class="comment">// Title : Crystal CS8900 Ethernet Interface Driver</span>
15 00006 <span class="comment">// Author : Pascal Stang</span>
16 00007 <span class="comment">// Created : 11/7/2004</span>
17 00008 <span class="comment">// Revised : 8/22/2005</span>
18 00009 <span class="comment">// Version : 0.1</span>
19 00010 <span class="comment">// Target MCU : Atmel AVR series</span>
20 00011 <span class="comment">// Editor Tabs : 4</span>
21 00012 <span class="comment">//</span><span class="comment"></span>
22 00013 <span class="comment">/// \ingroup network</span>
23 00014 <span class="comment">/// \defgroup cs8900 Crystal CS8900 Ethernet Interface Driver (cs8900.c)</span>
24 00015 <span class="comment">/// \code #include "net/cs8900.h" \endcode</span>
25 00016 <span class="comment">/// \par Overview</span>
26 00017 <span class="comment">/// This driver provides initialization and transmit/receive</span>
27 00018 <span class="comment">/// functions for the Crystal CS8900 10Mb Ethernet Controller and PHY.</span>
28 00019 <span class="comment"></span><span class="comment">//</span>
29 00020 <span class="comment">//*****************************************************************************</span><span class="comment"></span>
30 00021 <span class="comment">//@{</span>
31 00022 <span class="comment"></span>
32 00023 <span class="preprocessor">#ifndef CS8900_H</span>
33 00024 <span class="preprocessor"></span><span class="preprocessor">#define CS8900_H</span>
34 00025 <span class="preprocessor"></span>
35 00026 <span class="preprocessor">#include "<a class="code" href="global_8h.html">global.h</a>"</span>
36 00027
37 00028 <span class="preprocessor">#define nop() asm volatile ("nop")</span>
38 00029 <span class="preprocessor"></span>
39 00030
40 00031 <span class="comment">// Crystal ESIA product ID</span>
41 00032 <span class="preprocessor">#define CS8900_ESIA_ID (0x630e)</span>
42 00033 <span class="preprocessor"></span>
43 00034 <span class="comment">// CS8900 IO Registers</span>
44 00035 <span class="preprocessor">#define CS8900_IO_RXTX_DATA_PORT0 (0x0000)</span>
45 00036 <span class="preprocessor"></span><span class="preprocessor">#define CS8900_IO_RXTX_DATA_PORT1 (0x0002)</span>
46 00037 <span class="preprocessor"></span><span class="preprocessor">#define CS8900_IO_TXCMD (0x0004)</span>
47 00038 <span class="preprocessor"></span><span class="preprocessor">#define CS8900_IO_TXLENGTH (0x0006)</span>
48 00039 <span class="preprocessor"></span><span class="preprocessor">#define CS8900_IO_ISQ (0x0008)</span>
49 00040 <span class="preprocessor"></span><span class="preprocessor">#define CS8900_IO_PP_PTR (0x000a)</span>
50 00041 <span class="preprocessor"></span><span class="preprocessor">#define CS8900_IO_PP_DATA_PORT0 (0x000c)</span>
51 00042 <span class="preprocessor"></span><span class="preprocessor">#define CS8900_IO_PP_DATA_PORT1 (0x000e)</span>
52 00043 <span class="preprocessor"></span>
53 00044 <span class="comment">// definitions for Crystal CS8900 ethernet-controller</span>
54 00045 <span class="comment">// based on linux-header by Russel Nelson</span>
55 00046
56 00047 <span class="preprocessor">#define PP_ChipID 0x0000 // offset 0h -&gt; Corp-ID</span>
57 00048 <span class="preprocessor"></span> <span class="comment">// offset 2h -&gt; Model/Product Number</span>
58 00049 <span class="comment">// offset 3h -&gt; Chip Revision Number</span>
59 00050
60 00051 <span class="preprocessor">#define PP_ISAIOB 0x0020 // IO base address</span>
61 00052 <span class="preprocessor"></span><span class="preprocessor">#define PP_CS8900_ISAINT 0x0022 // ISA interrupt select</span>
62 00053 <span class="preprocessor"></span><span class="preprocessor">#define PP_CS8900_ISADMA 0x0024 // ISA Rec DMA channel</span>
63 00054 <span class="preprocessor"></span><span class="preprocessor">#define PP_ISASOF 0x0026 // ISA DMA offset</span>
64 00055 <span class="preprocessor"></span><span class="preprocessor">#define PP_DmaFrameCnt 0x0028 // ISA DMA Frame count</span>
65 00056 <span class="preprocessor"></span><span class="preprocessor">#define PP_DmaByteCnt 0x002A // ISA DMA Byte count</span>
66 00057 <span class="preprocessor"></span><span class="preprocessor">#define PP_CS8900_ISAMemB 0x002C // Memory base</span>
67 00058 <span class="preprocessor"></span><span class="preprocessor">#define PP_ISABootBase 0x0030 // Boot Prom base</span>
68 00059 <span class="preprocessor"></span><span class="preprocessor">#define PP_ISABootMask 0x0034 // Boot Prom Mask</span>
69 00060 <span class="preprocessor"></span><span class="preprocessor">#define PP_RxFrameByteCnt 0x0050</span>
70 00061 <span class="preprocessor"></span>
71 00062 <span class="comment">// EEPROM data and command registers</span>
72 00063 <span class="preprocessor">#define PP_EECMD 0x0040 // NVR Interface Command register</span>
73 00064 <span class="preprocessor"></span><span class="preprocessor">#define PP_EEData 0x0042 // NVR Interface Data Register</span>
74 00065 <span class="preprocessor"></span>
75 00066 <span class="comment">// Configuration and control registers</span>
76 00067 <span class="preprocessor">#define PP_RxCFG 0x0102 // Rx Bus config</span>
77 00068 <span class="preprocessor"></span><span class="preprocessor">#define PP_RxCTL 0x0104 // Receive Control Register</span>
78 00069 <span class="preprocessor"></span><span class="preprocessor">#define PP_TxCFG 0x0106 // Transmit Config Register</span>
79 00070 <span class="preprocessor"></span><span class="preprocessor">#define PP_TxCMD 0x0108 // Transmit Command Register</span>
80 00071 <span class="preprocessor"></span><span class="preprocessor">#define PP_BufCFG 0x010A // Bus configuration Register</span>
81 00072 <span class="preprocessor"></span><span class="preprocessor">#define PP_LineCTL 0x0112 // Line Config Register</span>
82 00073 <span class="preprocessor"></span><span class="preprocessor">#define PP_SelfCTL 0x0114 // Self Command Register</span>
83 00074 <span class="preprocessor"></span><span class="preprocessor">#define PP_BusCTL 0x0116 // ISA bus control Register</span>
84 00075 <span class="preprocessor"></span><span class="preprocessor">#define PP_TestCTL 0x0118 // Test Register</span>
85 00076 <span class="preprocessor"></span>
86 00077 <span class="comment">// Status and Event Registers</span>
87 00078 <span class="preprocessor">#define PP_ISQ 0x0120 // Interrupt Status</span>
88 00079 <span class="preprocessor"></span><span class="preprocessor">#define PP_RxEvent 0x0124 // Rx Event Register</span>
89 00080 <span class="preprocessor"></span><span class="preprocessor">#define PP_TxEvent 0x0128 // Tx Event Register</span>
90 00081 <span class="preprocessor"></span><span class="preprocessor">#define PP_BufEvent 0x012C // Bus Event Register</span>
91 00082 <span class="preprocessor"></span><span class="preprocessor">#define PP_RxMiss 0x0130 // Receive Miss Count</span>
92 00083 <span class="preprocessor"></span><span class="preprocessor">#define PP_TxCol 0x0132 // Transmit Collision Count</span>
93 00084 <span class="preprocessor"></span><span class="preprocessor">#define PP_LineST 0x0134 // Line State Register</span>
94 00085 <span class="preprocessor"></span><span class="preprocessor">#define PP_SelfST 0x0136 // Self State register</span>
95 00086 <span class="preprocessor"></span><span class="preprocessor">#define PP_BusST 0x0138 // Bus Status</span>
96 00087 <span class="preprocessor"></span><span class="preprocessor">#define PP_TDR 0x013C // Time Domain Reflectometry</span>
97 00088 <span class="preprocessor"></span>
98 00089 <span class="comment">// Initiate Transmit Registers</span>
99 00090 <span class="preprocessor">#define PP_TxCommand 0x0144 // Tx Command</span>
100 00091 <span class="preprocessor"></span><span class="preprocessor">#define PP_TxLength 0x0146 // Tx Length</span>
101 00092 <span class="preprocessor"></span>
102 00093 <span class="comment">// Address Filter Registers</span>
103 00094 <span class="preprocessor">#define PP_LAF 0x0150 // Hash Table</span>
104 00095 <span class="preprocessor"></span><span class="preprocessor">#define PP_IA 0x0158 // Physical Address Register</span>
105 00096 <span class="preprocessor"></span>
106 00097 <span class="comment">// Frame Location</span>
107 00098 <span class="preprocessor">#define PP_RxStatus 0x0400 // Receive start of frame</span>
108 00099 <span class="preprocessor"></span><span class="preprocessor">#define PP_RxLength 0x0402 // Receive Length of frame</span>
109 00100 <span class="preprocessor"></span><span class="preprocessor">#define PP_RxFrame 0x0404 // Receive frame pointer</span>
110 00101 <span class="preprocessor"></span><span class="preprocessor">#define PP_TxFrame 0x0A00 // Transmit frame pointer</span>
111 00102 <span class="preprocessor"></span>
112 00103 <span class="comment">// Primary I/O Base Address. If no I/O base is supplied by the user, then this</span>
113 00104 <span class="comment">// can be used as the default I/O base to access the PacketPage Area.</span>
114 00105 <span class="preprocessor">#define DEFAULTIOBASE 0x0300</span>
115 00106 <span class="preprocessor"></span>
116 00107 <span class="comment">// PP_RxCFG - Receive Configuration and Interrupt Mask bit definition - Read/write</span>
117 00108 <span class="preprocessor">#define SKIP_1 0x0040</span>
118 00109 <span class="preprocessor"></span><span class="preprocessor">#define RX_STREAM_ENBL 0x0080</span>
119 00110 <span class="preprocessor"></span><span class="preprocessor">#define RX_OK_ENBL 0x0100</span>
120 00111 <span class="preprocessor"></span><span class="preprocessor">#define RX_DMA_ONLY 0x0200</span>
121 00112 <span class="preprocessor"></span><span class="preprocessor">#define AUTO_RX_DMA 0x0400</span>
122 00113 <span class="preprocessor"></span><span class="preprocessor">#define BUFFER_CRC 0x0800</span>
123 00114 <span class="preprocessor"></span><span class="preprocessor">#define RX_CRC_ERROR_ENBL 0x1000</span>
124 00115 <span class="preprocessor"></span><span class="preprocessor">#define RX_RUNT_ENBL 0x2000</span>
125 00116 <span class="preprocessor"></span><span class="preprocessor">#define RX_EXTRA_DATA_ENBL 0x4000</span>
126 00117 <span class="preprocessor"></span>
127 00118 <span class="comment">// PP_RxCTL - Receive Control bit definition - Read/write</span>
128 00119 <span class="preprocessor">#define RX_IA_HASH_ACCEPT 0x0040</span>
129 00120 <span class="preprocessor"></span><span class="preprocessor">#define RX_PROM_ACCEPT 0x0080</span>
130 00121 <span class="preprocessor"></span><span class="preprocessor">#define RX_OK_ACCEPT 0x0100</span>
131 00122 <span class="preprocessor"></span><span class="preprocessor">#define RX_MULTCAST_ACCEPT 0x0200</span>
132 00123 <span class="preprocessor"></span><span class="preprocessor">#define RX_IA_ACCEPT 0x0400</span>
133 00124 <span class="preprocessor"></span><span class="preprocessor">#define RX_BROADCAST_ACCEPT 0x0800</span>
134 00125 <span class="preprocessor"></span><span class="preprocessor">#define RX_BAD_CRC_ACCEPT 0x1000</span>
135 00126 <span class="preprocessor"></span><span class="preprocessor">#define RX_RUNT_ACCEPT 0x2000</span>
136 00127 <span class="preprocessor"></span><span class="preprocessor">#define RX_EXTRA_DATA_ACCEPT 0x4000</span>
137 00128 <span class="preprocessor"></span>
138 00129 <span class="comment">// PP_TxCFG - Transmit Configuration Interrupt Mask bit definition - Read/write</span>
139 00130 <span class="preprocessor">#define TX_LOST_CRS_ENBL 0x0040</span>
140 00131 <span class="preprocessor"></span><span class="preprocessor">#define TX_SQE_ERROR_ENBL 0x0080</span>
141 00132 <span class="preprocessor"></span><span class="preprocessor">#define TX_OK_ENBL 0x0100</span>
142 00133 <span class="preprocessor"></span><span class="preprocessor">#define TX_LATE_COL_ENBL 0x0200</span>
143 00134 <span class="preprocessor"></span><span class="preprocessor">#define TX_JBR_ENBL 0x0400</span>
144 00135 <span class="preprocessor"></span><span class="preprocessor">#define TX_ANY_COL_ENBL 0x0800</span>
145 00136 <span class="preprocessor"></span><span class="preprocessor">#define TX_16_COL_ENBL 0x8000</span>
146 00137 <span class="preprocessor"></span>
147 00138 <span class="comment">// PP_TxCMD - Transmit Command bit definition - Read-only and</span>
148 00139 <span class="comment">// PP_TxCommand - Write-only</span>
149 00140 <span class="preprocessor">#define TX_START_5_BYTES 0x0000</span>
150 00141 <span class="preprocessor"></span><span class="preprocessor">#define TX_START_381_BYTES 0x0040</span>
151 00142 <span class="preprocessor"></span><span class="preprocessor">#define TX_START_1021_BYTES 0x0080</span>
152 00143 <span class="preprocessor"></span><span class="preprocessor">#define TX_START_ALL_BYTES 0x00C0</span>
153 00144 <span class="preprocessor"></span><span class="preprocessor">#define TX_FORCE 0x0100</span>
154 00145 <span class="preprocessor"></span><span class="preprocessor">#define TX_ONE_COL 0x0200</span>
155 00146 <span class="preprocessor"></span><span class="preprocessor">#define TX_NO_CRC 0x1000</span>
156 00147 <span class="preprocessor"></span><span class="preprocessor">#define TX_RUNT 0x2000</span>
157 00148 <span class="preprocessor"></span>
158 00149 <span class="comment">// PP_BufCFG - Buffer Configuration Interrupt Mask bit definition - Read/write</span>
159 00150 <span class="preprocessor">#define GENERATE_SW_INTERRUPT 0x0040</span>
160 00151 <span class="preprocessor"></span><span class="preprocessor">#define RX_DMA_ENBL 0x0080</span>
161 00152 <span class="preprocessor"></span><span class="preprocessor">#define READY_FOR_TX_ENBL 0x0100</span>
162 00153 <span class="preprocessor"></span><span class="preprocessor">#define TX_UNDERRUN_ENBL 0x0200</span>
163 00154 <span class="preprocessor"></span><span class="preprocessor">#define RX_MISS_ENBL 0x0400</span>
164 00155 <span class="preprocessor"></span><span class="preprocessor">#define RX_128_BYTE_ENBL 0x0800</span>
165 00156 <span class="preprocessor"></span><span class="preprocessor">#define TX_COL_COUNT_OVRFLOW_ENBL 0x1000</span>
166 00157 <span class="preprocessor"></span><span class="preprocessor">#define RX_MISS_COUNT_OVRFLOW_ENBL 0x2000</span>
167 00158 <span class="preprocessor"></span><span class="preprocessor">#define RX_DEST_MATCH_ENBL 0x8000</span>
168 00159 <span class="preprocessor"></span>
169 00160 <span class="comment">// PP_LineCTL - Line Control bit definition - Read/write</span>
170 00161 <span class="preprocessor">#define SERIAL_RX_ON 0x0040</span>
171 00162 <span class="preprocessor"></span><span class="preprocessor">#define SERIAL_TX_ON 0x0080</span>
172 00163 <span class="preprocessor"></span><span class="preprocessor">#define AUI_ONLY 0x0100</span>
173 00164 <span class="preprocessor"></span><span class="preprocessor">#define AUTO_AUI_10BASET 0x0200</span>
174 00165 <span class="preprocessor"></span><span class="preprocessor">#define MODIFIED_BACKOFF 0x0800</span>
175 00166 <span class="preprocessor"></span><span class="preprocessor">#define NO_AUTO_POLARITY 0x1000</span>
176 00167 <span class="preprocessor"></span><span class="preprocessor">#define TWO_PART_DEFDIS 0x2000</span>
177 00168 <span class="preprocessor"></span><span class="preprocessor">#define LOW_RX_SQUELCH 0x4000</span>
178 00169 <span class="preprocessor"></span>
179 00170 <span class="comment">// PP_SelfCTL - Software Self Control bit definition - Read/write</span>
180 00171 <span class="preprocessor">#define POWER_ON_RESET 0x0040</span>
181 00172 <span class="preprocessor"></span><span class="preprocessor">#define SW_STOP 0x0100</span>
182 00173 <span class="preprocessor"></span><span class="preprocessor">#define SLEEP_ON 0x0200</span>
183 00174 <span class="preprocessor"></span><span class="preprocessor">#define AUTO_WAKEUP 0x0400</span>
184 00175 <span class="preprocessor"></span><span class="preprocessor">#define HCB0_ENBL 0x1000</span>
185 00176 <span class="preprocessor"></span><span class="preprocessor">#define HCB1_ENBL 0x2000</span>
186 00177 <span class="preprocessor"></span><span class="preprocessor">#define HCB0 0x4000</span>
187 00178 <span class="preprocessor"></span><span class="preprocessor">#define HCB1 0x8000</span>
188 00179 <span class="preprocessor"></span>
189 00180 <span class="comment">// PP_BusCTL - ISA Bus Control bit definition - Read/write</span>
190 00181 <span class="preprocessor">#define RESET_RX_DMA 0x0040</span>
191 00182 <span class="preprocessor"></span><span class="preprocessor">#define MEMORY_ON 0x0400</span>
192 00183 <span class="preprocessor"></span><span class="preprocessor">#define DMA_BURST_MODE 0x0800</span>
193 00184 <span class="preprocessor"></span><span class="preprocessor">#define IO_CHANNEL_READY_ON 0x1000</span>
194 00185 <span class="preprocessor"></span><span class="preprocessor">#define RX_DMA_SIZE_64K 0x2000</span>
195 00186 <span class="preprocessor"></span><span class="preprocessor">#define ENABLE_IRQ 0x8000</span>
196 00187 <span class="preprocessor"></span>
197 00188 <span class="comment">// PP_TestCTL - Test Control bit definition - Read/write</span>
198 00189 <span class="preprocessor">#define LINK_OFF 0x0080</span>
199 00190 <span class="preprocessor"></span><span class="preprocessor">#define ENDEC_LOOPBACK 0x0200</span>
200 00191 <span class="preprocessor"></span><span class="preprocessor">#define AUI_LOOPBACK 0x0400</span>
201 00192 <span class="preprocessor"></span><span class="preprocessor">#define BACKOFF_OFF 0x0800</span>
202 00193 <span class="preprocessor"></span><span class="preprocessor">#define FDX_8900 0x4000</span>
203 00194 <span class="preprocessor"></span>
204 00195 <span class="comment">// PP_RxEvent - Receive Event Bit definition - Read-only</span>
205 00196 <span class="preprocessor">#define RX_IA_HASHED 0x0040</span>
206 00197 <span class="preprocessor"></span><span class="preprocessor">#define RX_DRIBBLE 0x0080</span>
207 00198 <span class="preprocessor"></span><span class="preprocessor">#define RX_OK 0x0100</span>
208 00199 <span class="preprocessor"></span><span class="preprocessor">#define RX_HASHED 0x0200</span>
209 00200 <span class="preprocessor"></span><span class="preprocessor">#define RX_IA 0x0400</span>
210 00201 <span class="preprocessor"></span><span class="preprocessor">#define RX_BROADCAST 0x0800</span>
211 00202 <span class="preprocessor"></span><span class="preprocessor">#define RX_CRC_ERROR 0x1000</span>
212 00203 <span class="preprocessor"></span><span class="preprocessor">#define RX_RUNT 0x2000</span>
213 00204 <span class="preprocessor"></span><span class="preprocessor">#define RX_EXTRA_DATA 0x4000</span>
214 00205 <span class="preprocessor"></span><span class="preprocessor">#define HASH_INDEX_MASK 0xFC00 // Hash-Table Index Mask (6 Bit)</span>
215 00206 <span class="preprocessor"></span>
216 00207 <span class="comment">// PP_TxEvent - Transmit Event Bit definition - Read-only</span>
217 00208 <span class="preprocessor">#define TX_LOST_CRS 0x0040</span>
218 00209 <span class="preprocessor"></span><span class="preprocessor">#define TX_SQE_ERROR 0x0080</span>
219 00210 <span class="preprocessor"></span><span class="preprocessor">#define TX_OK 0x0100</span>
220 00211 <span class="preprocessor"></span><span class="preprocessor">#define TX_LATE_COL 0x0200</span>
221 00212 <span class="preprocessor"></span><span class="preprocessor">#define TX_JBR 0x0400</span>
222 00213 <span class="preprocessor"></span><span class="preprocessor">#define TX_16_COL 0x8000</span>
223 00214 <span class="preprocessor"></span><span class="preprocessor">#define TX_COL_COUNT_MASK 0x7800</span>
224 00215 <span class="preprocessor"></span>
225 00216 <span class="comment">// PP_BufEvent - Buffer Event Bit definition - Read-only</span>
226 00217 <span class="preprocessor">#define SW_INTERRUPT 0x0040</span>
227 00218 <span class="preprocessor"></span><span class="preprocessor">#define RX_DMA 0x0080</span>
228 00219 <span class="preprocessor"></span><span class="preprocessor">#define READY_FOR_TX 0x0100</span>
229 00220 <span class="preprocessor"></span><span class="preprocessor">#define TX_UNDERRUN 0x0200</span>
230 00221 <span class="preprocessor"></span><span class="preprocessor">#define RX_MISS 0x0400</span>
231 00222 <span class="preprocessor"></span><span class="preprocessor">#define RX_128_BYTE 0x0800</span>
232 00223 <span class="preprocessor"></span><span class="preprocessor">#define TX_COL_OVRFLW 0x1000</span>
233 00224 <span class="preprocessor"></span><span class="preprocessor">#define RX_MISS_OVRFLW 0x2000</span>
234 00225 <span class="preprocessor"></span><span class="preprocessor">#define RX_DEST_MATCH 0x8000</span>
235 00226 <span class="preprocessor"></span>
236 00227 <span class="comment">// PP_LineST - Ethernet Line Status bit definition - Read-only</span>
237 00228 <span class="preprocessor">#define LINK_OK 0x0080</span>
238 00229 <span class="preprocessor"></span><span class="preprocessor">#define AUI_ON 0x0100</span>
239 00230 <span class="preprocessor"></span><span class="preprocessor">#define TENBASET_ON 0x0200</span>
240 00231 <span class="preprocessor"></span><span class="preprocessor">#define POLARITY_OK 0x1000</span>
241 00232 <span class="preprocessor"></span><span class="preprocessor">#define CRS_OK 0x4000</span>
242 00233 <span class="preprocessor"></span>
243 00234 <span class="comment">// PP_SelfST - Chip Software Status bit definition</span>
244 00235 <span class="preprocessor">#define ACTIVE_33V 0x0040</span>
245 00236 <span class="preprocessor"></span><span class="preprocessor">#define INIT_DONE 0x0080</span>
246 00237 <span class="preprocessor"></span><span class="preprocessor">#define SI_BUSY 0x0100</span>
247 00238 <span class="preprocessor"></span><span class="preprocessor">#define EEPROM_PRESENT 0x0200</span>
248 00239 <span class="preprocessor"></span><span class="preprocessor">#define EEPROM_OK 0x0400</span>
249 00240 <span class="preprocessor"></span><span class="preprocessor">#define EL_PRESENT 0x0800</span>
250 00241 <span class="preprocessor"></span><span class="preprocessor">#define EE_SIZE_64 0x1000</span>
251 00242 <span class="preprocessor"></span>
252 00243 <span class="comment">// PP_BusST - ISA Bus Status bit definition</span>
253 00244 <span class="preprocessor">#define TX_BID_ERROR 0x0080</span>
254 00245 <span class="preprocessor"></span><span class="preprocessor">#define READY_FOR_TX_NOW 0x0100</span>
255 00246 <span class="preprocessor"></span>
256 00247 <span class="comment">// The following block defines the ISQ event types</span>
257 00248 <span class="preprocessor">#define ISQ_RX_EVENT 0x0004</span>
258 00249 <span class="preprocessor"></span><span class="preprocessor">#define ISQ_TX_EVENT 0x0008</span>
259 00250 <span class="preprocessor"></span><span class="preprocessor">#define ISQ_BUFFER_EVENT 0x000C</span>
260 00251 <span class="preprocessor"></span><span class="preprocessor">#define ISQ_RX_MISS_EVENT 0x0010</span>
261 00252 <span class="preprocessor"></span><span class="preprocessor">#define ISQ_TX_COL_EVENT 0x0012</span>
262 00253 <span class="preprocessor"></span>
263 00254 <span class="preprocessor">#define ISQ_EVENT_MASK 0x003F // ISQ mask to find out type of event</span>
264 00255 <span class="preprocessor"></span>
265 00256 <span class="preprocessor">#define AUTOINCREMENT 0x8000 // Bit mask to set Bit-15 for autoincrement</span>
266 00257 <span class="preprocessor"></span>
267 00258 <span class="comment">// EEProm Commands</span>
268 00259 <span class="preprocessor">#define EEPROM_WRITE_EN 0x00F0</span>
269 00260 <span class="preprocessor"></span><span class="preprocessor">#define EEPROM_WRITE_DIS 0x0000</span>
270 00261 <span class="preprocessor"></span><span class="preprocessor">#define EEPROM_WRITE_CMD 0x0100</span>
271 00262 <span class="preprocessor"></span><span class="preprocessor">#define EEPROM_READ_CMD 0x0200</span>
272 00263 <span class="preprocessor"></span>
273 00264 <span class="comment">// Receive Header of each packet in receive area of memory for DMA-Mode</span>
274 00265 <span class="preprocessor">#define RBUF_EVENT_LOW 0x0000 // Low byte of RxEvent</span>
275 00266 <span class="preprocessor"></span><span class="preprocessor">#define RBUF_EVENT_HIGH 0x0001 // High byte of RxEvent</span>
276 00267 <span class="preprocessor"></span><span class="preprocessor">#define RBUF_LEN_LOW 0x0002 // Length of received data - low byte</span>
277 00268 <span class="preprocessor"></span><span class="preprocessor">#define RBUF_LEN_HI 0x0003 // Length of received data - high byte</span>
278 00269 <span class="preprocessor"></span><span class="preprocessor">#define RBUF_HEAD_LEN 0x0004 // Length of this header</span>
279 00270 <span class="preprocessor"></span>
280 00271 <span class="comment">// typedefs</span>
281 00272
282 00273 <span class="comment">// constants</span>
283 00274
284 00275 <span class="comment">// prototypes</span>
285 00276
286 00277 <span class="preprocessor">#include "<a class="code" href="nic_8h.html">nic.h</a>"</span>
287 00278
288 00279 <span class="keywordtype">unsigned</span> <span class="keywordtype">int</span> cs8900BeginPacketRetreive(<span class="keywordtype">void</span>);
289 00280 <span class="keywordtype">void</span> cs8900RetreivePacketData(u08* packet, <span class="keywordtype">unsigned</span> <span class="keywordtype">int</span> packetLength);
290 00281 <span class="keywordtype">void</span> cs8900EndPacketRetreive(<span class="keywordtype">void</span>);
291 00282
292 00283
293 00284 <span class="keywordtype">void</span> cs8900Init(<span class="keywordtype">void</span>);
294 00285 <span class="keywordtype">void</span> cs8900Write(<span class="keywordtype">unsigned</span> <span class="keywordtype">char</span> address, <span class="keywordtype">unsigned</span> <span class="keywordtype">char</span> data);
295 00286 <span class="keywordtype">unsigned</span> <span class="keywordtype">char</span> cs8900Read(<span class="keywordtype">unsigned</span> <span class="keywordtype">char</span> address);
296 00287
297 00288 <span class="keywordtype">void</span> cs8900Write16(<span class="keywordtype">unsigned</span> <span class="keywordtype">char</span> address, <span class="keywordtype">unsigned</span> <span class="keywordtype">short</span> data);
298 00289 <span class="keywordtype">unsigned</span> <span class="keywordtype">short</span> cs8900Read16(<span class="keywordtype">unsigned</span> <span class="keywordtype">char</span> address);
299 00290
300 00291 <span class="keywordtype">void</span> cs8900WriteReg(<span class="keywordtype">unsigned</span> <span class="keywordtype">short</span> address, <span class="keywordtype">unsigned</span> <span class="keywordtype">short</span> data);
301 00292 <span class="keywordtype">unsigned</span> <span class="keywordtype">short</span> cs8900ReadReg(<span class="keywordtype">unsigned</span> <span class="keywordtype">short</span> address);
302 00293
303 00294 <span class="keywordtype">void</span> cs8900CopyToFrame(<span class="keywordtype">unsigned</span> <span class="keywordtype">char</span> *source, <span class="keywordtype">unsigned</span> <span class="keywordtype">short</span> size);
304 00295 <span class="keywordtype">void</span> cs8900CopyFromFrame(<span class="keywordtype">unsigned</span> <span class="keywordtype">char</span> *dest, <span class="keywordtype">unsigned</span> <span class="keywordtype">short</span> size);
305 00296
306 00297 u08 cs8900LinkStatus(<span class="keywordtype">void</span>);
307 00298
308 00299 <span class="keywordtype">void</span> cs8900IORegDump(<span class="keywordtype">void</span>);
309 00300 <span class="keywordtype">void</span> cs8900RegDump(<span class="keywordtype">void</span>);
310 00301
311 00302 <span class="preprocessor">#endif</span>
312 00303 <span class="preprocessor"></span><span class="comment">//@}</span>
313 00304 <span class="comment"></span>
314 00305
315 00306 <span class="comment">/****************</span>
316 00307 <span class="comment"></span>
317 00308 <span class="comment">// CS8900 device register definitions</span>
318 00309 <span class="comment"></span>
319 00310 <span class="comment">// Crystal ESIA product id.</span>
320 00311 <span class="comment"></span>
321 00312 <span class="comment">#define CS8900_ESIA_ID (0x630e)</span>
322 00313 <span class="comment"></span>
323 00314 <span class="comment">//IO Registers.</span>
324 00315 <span class="comment">#define CS8900_IO_RX_TX_DATA_PORT0 (0x0000)</span>
325 00316 <span class="comment">#define CS8900_IO_TX_TX_DATA_PORT1 (0x0002)</span>
326 00317 <span class="comment">#define CS8900_IO_TxCMD (0x0004)</span>
327 00318 <span class="comment">#define CS8900_IO_TxLength (0x0006)</span>
328 00319 <span class="comment">#define CS8900_IO_ISQ (0x0008)</span>
329 00320 <span class="comment">#define CS8900_IO_PACKET_PAGE_PTR (0x000a)</span>
330 00321 <span class="comment">#define CS8900_IO_PP_DATA_PORT0 (0x000c)</span>
331 00322 <span class="comment">#define CS8900_IO_PP_DATA_PORT1 (0x000e)</span>
332 00323 <span class="comment"></span>
333 00324 <span class="comment"> * Packet Page Registers.</span>
334 00325 <span class="comment"></span>
335 00326 <span class="comment"> * Bus Interface Registers.</span>
336 00327 <span class="comment"></span>
337 00328 <span class="comment">#define CS8900_PP_PROD_ID (0x0000)</span>
338 00329 <span class="comment">#define CS8900_PP_IO_BASE (0x0020)</span>
339 00330 <span class="comment">#define CS8900_PP_INT (0x0022)</span>
340 00331 <span class="comment">#define CS8900_PP_DMA_CHANNEL (0x0024)</span>
341 00332 <span class="comment">#define CS8900_PP_DMA_SOF (0x0026)</span>
342 00333 <span class="comment">#define CS8900_PP_DMA_FRM_CNT (0x0028)</span>
343 00334 <span class="comment">#define CS8900_PP_DMA_RX_BCNT (0x002a)</span>
344 00335 <span class="comment">#define CS8900_PP_MEM_BASE (0x002c)</span>
345 00336 <span class="comment">#define CS8900_PP_BPROM_BASE (0x0030)</span>
346 00337 <span class="comment">#define CS8900_PP_BPROM_AMASK (0x0034)</span>
347 00338 <span class="comment">#define CS8900_PP_EEPROM_CMD (0x0040)</span>
348 00339 <span class="comment">#define CS8900_PP_EEPROM_DATA (0x0042)</span>
349 00340 <span class="comment">#define CS8900_PP_RX_FRAME_BCNT (0x0050)</span>
350 00341 <span class="comment"></span>
351 00342 <span class="comment"> * Configuration and Control Registers.</span>
352 00343 <span class="comment"></span>
353 00344 <span class="comment">#define CS8900_PP_RxCFG (0x0102)</span>
354 00345 <span class="comment">#define CS8900_PP_RxCTL (0x0104)</span>
355 00346 <span class="comment">#define CS8900_PP_TxCFG (0x0106)</span>
356 00347 <span class="comment">#define CS8900_PP_TxCMD_READ (0x0108)</span>
357 00348 <span class="comment">#define CS8900_PP_BufCFG (0x010a)</span>
358 00349 <span class="comment">#define CS8900_PP_LineCFG (0x0112)</span>
359 00350 <span class="comment">#define CS8900_PP_SelfCTL (0x0114)</span>
360 00351 <span class="comment">#define CS8900_PP_BusCTL (0x0116)</span>
361 00352 <span class="comment">#define CS8900_PP_TestCTL (0x0118)</span>
362 00353 <span class="comment"></span>
363 00354 <span class="comment"> * Status and Event Registers.</span>
364 00355 <span class="comment"></span>
365 00356 <span class="comment">#define CS8900_PP_ISQ (0x0120)</span>
366 00357 <span class="comment">#define CS8900_PP_RxEvent (0x0124)</span>
367 00358 <span class="comment">#define CS8900_PP_TxEvent (0x0128)</span>
368 00359 <span class="comment">#define CS8900_PP_BufEvent (0x012c)</span>
369 00360 <span class="comment">#define CS8900_PP_RxMISS (0x0130)</span>
370 00361 <span class="comment">#define CS8900_PP_TxCol (0x0132)</span>
371 00362 <span class="comment">#define CS8900_PP_LineST (0x0134)</span>
372 00363 <span class="comment">#define CS8900_PP_SelfST (0x0136)</span>
373 00364 <span class="comment">#define CS8900_PP_BusST (0x0138)</span>
374 00365 <span class="comment">#define CS8900_PP_TDR (0x013c)</span>
375 00366 <span class="comment"></span>
376 00367 <span class="comment"> * Initiate Transmit Registers.</span>
377 00368 <span class="comment">#define CS8900_PP_TxCMD (0x0144)</span>
378 00369 <span class="comment">#define CS8900_PP_TxLength (0x0146)</span>
379 00370 <span class="comment"></span>
380 00371 <span class="comment">* Address Filter Registers.</span>
381 00372 <span class="comment">#define CS8900_PP_LAF (0x0150)</span>
382 00373 <span class="comment">#define CS8900_PP_IA (0x0158)</span>
383 00374 <span class="comment"></span>
384 00375 <span class="comment"> * Frame Location.</span>
385 00376 <span class="comment">#define CS8900_PP_RxStatus (0x0400)</span>
386 00377 <span class="comment">#define CS8900_PP_RxLength (0x0402)</span>
387 00378 <span class="comment">#define CS8900_PP_RxFrameLoc (0x0404)</span>
388 00379 <span class="comment">#define CS8900_PP_TxFrameLoc (0x0a00)</span>
389 00380 <span class="comment"></span>
390 00381 <span class="comment"> * Bit Definitions of Registers.</span>
391 00382 <span class="comment"> * IO Packet Page Pointer.</span>
392 00383 <span class="comment">#define CS8900_PPP_AUTO_INCREMENT (0x8000)</span>
393 00384 <span class="comment"></span>
394 00385 <span class="comment"> * Reg 3. Receiver Configuration.</span>
395 00386 <span class="comment">#define CS8900_RX_CONFIG_SKIP_1 (1 &lt;&lt; 6)</span>
396 00387 <span class="comment">#define CS8900_RX_CONFIG_STREAM_ENABLE (1 &lt;&lt; 7)</span>
397 00388 <span class="comment">#define CS8900_RX_CONFIG_RX_OK (1 &lt;&lt; 8)</span>
398 00389 <span class="comment">#define CS8900_RX_CONFIG_RX_DMA (1 &lt;&lt; 9)</span>
399 00390 <span class="comment">#define CS8900_RX_CONFIG_RX_AUTO_DMA (1 &lt;&lt; 10)</span>
400 00391 <span class="comment">#define CS8900_RX_CONFIG_BUFFER_CRC (1 &lt;&lt; 11)</span>
401 00392 <span class="comment">#define CS8900_RX_CONFIG_CRC_ERROR (1 &lt;&lt; 12)</span>
402 00393 <span class="comment">#define CS8900_RX_CONFIG_RUNT (1 &lt;&lt; 13)</span>
403 00394 <span class="comment">#define CS8900_RX_CONFIG_EXTRA_DATA (1 &lt;&lt; 14)</span>
404 00395 <span class="comment"></span>
405 00396 <span class="comment"> * Reg 4. Receiver Event.</span>
406 00397 <span class="comment">#define CS8900_RX_EVENT_HASH_IA_MATCH (1 &lt;&lt; 6)</span>
407 00398 <span class="comment">#define CS8900_RX_EVENT_DRIBBLE_BITS (1 &lt;&lt; 7)</span>
408 00399 <span class="comment">#define CS8900_RX_EVENT_RX_OK (1 &lt;&lt; 8)</span>
409 00400 <span class="comment">#define CS8900_RX_EVENT_HASHED (1 &lt;&lt; 9)</span>
410 00401 <span class="comment">#define CS8900_RX_EVENT_IA (1 &lt;&lt; 10)</span>
411 00402 <span class="comment">#define CS8900_RX_EVENT_BROADCAST (1 &lt;&lt; 11)</span>
412 00403 <span class="comment">#define CS8900_RX_EVENT_CRC_ERROR (1 &lt;&lt; 12)</span>
413 00404 <span class="comment">#define CS8900_RX_EVENT_RUNT (1 &lt;&lt; 13)</span>
414 00405 <span class="comment">#define CS8900_RX_EVENT_EXTRA_DATA (1 &lt;&lt; 14)</span>
415 00406 <span class="comment"></span>
416 00407 <span class="comment"> * Reg 5. Receiver Control.</span>
417 00408 <span class="comment">#define CS8900_RX_CTRL_HASH_IA_MATCH (1 &lt;&lt; 6)</span>
418 00409 <span class="comment">#define CS8900_RX_CTRL_PROMISCUOUS (1 &lt;&lt; 7)</span>
419 00410 <span class="comment">#define CS8900_RX_CTRL_RX_OK (1 &lt;&lt; 8)</span>
420 00411 <span class="comment">#define CS8900_RX_CTRL_MULTICAST (1 &lt;&lt; 9)</span>
421 00412 <span class="comment">#define CS8900_RX_CTRL_INDIVIDUAL (1 &lt;&lt; 10)</span>
422 00413 <span class="comment">#define CS8900_RX_CTRL_BROADCAST (1 &lt;&lt; 11)</span>
423 00414 <span class="comment">#define CS8900_RX_CTRL_CRC_ERROR (1 &lt;&lt; 12)</span>
424 00415 <span class="comment">#define CS8900_RX_CTRL_RUNT (1 &lt;&lt; 13)</span>
425 00416 <span class="comment">#define CS8900_RX_CTRL_EXTRA_DATA (1 &lt;&lt; 14)</span>
426 00417 <span class="comment"></span>
427 00418 <span class="comment"> * Reg 7. Transmit Configuration.</span>
428 00419 <span class="comment">#define CS8900_TX_CONFIG_LOSS_OF_CARRIER (1 &lt;&lt; 6)</span>
429 00420 <span class="comment">#define CS8900_TX_CONFIG_SQ_ERROR (1 &lt;&lt; 7)</span>
430 00421 <span class="comment">#define CS8900_TX_CONFIG_TX_OK (1 &lt;&lt; 8)</span>
431 00422 <span class="comment">#define CS8900_TX_CONFIG_OUT_OF_WINDOW (1 &lt;&lt; 9)</span>
432 00423 <span class="comment">#define CS8900_TX_CONFIG_JABBER (1 &lt;&lt; 10)</span>
433 00424 <span class="comment">#define CS8900_TX_CONFIG_ANY_COLLISION (1 &lt;&lt; 11)</span>
434 00425 <span class="comment">#define CS8900_TX_CONFIG_16_COLLISION (1 &lt;&lt; 15)</span>
435 00426 <span class="comment"></span>
436 00427 <span class="comment"> * Reg 8. Transmit Event.</span>
437 00428 <span class="comment">#define CS8900_TX_EVENT_LOSS_OF_CARRIER (1 &lt;&lt; 6)</span>
438 00429 <span class="comment">#define CS8900_TX_EVENT_SQ_ERROR (1 &lt;&lt; 7)</span>
439 00430 <span class="comment">#define CS8900_TX_EVENT_TX_OK (1 &lt;&lt; 8)</span>
440 00431 <span class="comment">#define CS8900_TX_EVENT_OUT_OF_WINDOW (1 &lt;&lt; 9)</span>
441 00432 <span class="comment">#define CS8900_TX_EVENT_JABBER (1 &lt;&lt; 10)</span>
442 00433 <span class="comment">#define CS8900_TX_EVENT_16_COLLISIONS (1 &lt;&lt; 15)</span>
443 00434 <span class="comment"></span>
444 00435 <span class="comment"> * Reg 9. Transmit Command Status.</span>
445 00436 <span class="comment">#define CS8900_TX_CMD_STATUS_TX_START_5 (0 &lt;&lt; 6)</span>
446 00437 <span class="comment">#define CS8900_TX_CMD_STATUS_TX_START_381 (1 &lt;&lt; 6)</span>
447 00438 <span class="comment">#define CS8900_TX_CMD_STATUS_TX_START_1021 (2 &lt;&lt; 6)</span>
448 00439 <span class="comment">#define CS8900_TX_CMD_STATUS_TX_START_ENTIRE (3 &lt;&lt; 6)</span>
449 00440 <span class="comment">#define CS8900_TX_CMD_STATUS_FORCE (1 &lt;&lt; 8)</span>
450 00441 <span class="comment">#define CS8900_TX_CMD_STATUS_ONE_COLLISION (1 &lt;&lt; 9)</span>
451 00442 <span class="comment">#define CS8900_TX_CMD_STATUS_INHIBIT_CRC (1 &lt;&lt; 12)</span>
452 00443 <span class="comment">#define CS8900_TX_CMD_STATUS_TX_PAD_DISABLED (1 &lt;&lt; 13)</span>
453 00444 <span class="comment"></span>
454 00445 <span class="comment"> * Reg B. Buffer Configuration.</span>
455 00446 <span class="comment">#define CS8900_BUFFER_CONFIG_SW_INT (1 &lt;&lt; 6)</span>
456 00447 <span class="comment">#define CS8900_BUFFER_CONFIG_RX_DMA_DONE (1 &lt;&lt; 7)</span>
457 00448 <span class="comment">#define CS8900_BUFFER_CONFIG_RDY_FOR_TX (1 &lt;&lt; 8)</span>
458 00449 <span class="comment">#define CS8900_BUFFER_CONFIG_TX_UNDERRUN (1 &lt;&lt; 9)</span>
459 00450 <span class="comment">#define CS8900_BUFFER_CONFIG_RX_MISSED (1 &lt;&lt; 10)</span>
460 00451 <span class="comment">#define CS8900_BUFFER_CONFIG_RX_128_BYTES (1 &lt;&lt; 11)</span>
461 00452 <span class="comment">#define CS8900_BUFFER_CONFIG_TX_COL_OVF (1 &lt;&lt; 12)</span>
462 00453 <span class="comment">#define CS8900_BUFFER_CONFIG_RX_MISSED_OVF (1 &lt;&lt; 13)</span>
463 00454 <span class="comment">#define CS8900_BUFFER_CONFIG_RX_DEST_MATCH (1 &lt;&lt; 15)</span>
464 00455 <span class="comment"></span>
465 00456 <span class="comment"> * Reg C. Buffer Event.</span>
466 00457 <span class="comment">#define CS8900_BUFFER_EVENT_SW_INT (1 &lt;&lt; 6)</span>
467 00458 <span class="comment">#define CS8900_BUFFER_EVENT_RX_DMA_DONE (1 &lt;&lt; 7)</span>
468 00459 <span class="comment">#define CS8900_BUFFER_EVENT_RDY_FOR_TX (1 &lt;&lt; 8)</span>
469 00460 <span class="comment">#define CS8900_BUFFER_EVENT_TX_UNDERRUN (1 &lt;&lt; 9)</span>
470 00461 <span class="comment">#define CS8900_BUFFER_EVENT_RX_MISSED (1 &lt;&lt; 10)</span>
471 00462 <span class="comment">#define CS8900_BUFFER_EVENT_RX_128_BYTES (1 &lt;&lt; 11)</span>
472 00463 <span class="comment">#define CS8900_BUFFER_EVENT_RX_DEST_MATCH (1 &lt;&lt; 15)</span>
473 00464 <span class="comment"></span>
474 00465 <span class="comment"> * Reg 13. Line Control.</span>
475 00466 <span class="comment">#define CS8900_LINE_CTRL_RX_ON (1 &lt;&lt; 6)</span>
476 00467 <span class="comment">#define CS8900_LINE_CTRL_TX_ON (1 &lt;&lt; 7)</span>
477 00468 <span class="comment">#define CS8900_LINE_CTRL_AUI (1 &lt;&lt; 8)</span>
478 00469 <span class="comment">#define CS8900_LINE_CTRL_10BASET (0 &lt;&lt; 9)</span>
479 00470 <span class="comment">#define CS8900_LINE_CTRL_AUTO_AUI_10BASET (1 &lt;&lt; 9)</span>
480 00471 <span class="comment">#define CS8900_LINE_CTRL_MOD_BACKOFF (1 &lt;&lt; 11)</span>
481 00472 <span class="comment">#define CS8900_LINE_CTRL_POLARITY_DISABLED (1 &lt;&lt; 12)</span>
482 00473 <span class="comment">#define CS8900_LINE_CTRL_2_PART_DEF_DISABLED (1 &lt;&lt; 13)</span>
483 00474 <span class="comment">#define CS8900_LINE_CTRL_LO_RX_SQUELCH (1 &lt;&lt; 14)</span>
484 00475 <span class="comment"></span>
485 00476 <span class="comment"> * Reg 14. Line Status.</span>
486 00477 <span class="comment">#define CS8900_LINE_STATUS_LINK_OK (1 &lt;&lt; 7)</span>
487 00478 <span class="comment">#define CS8900_LINE_STATUS_AUI (1 &lt;&lt; 8)</span>
488 00479 <span class="comment">#define CS8900_LINE_STATUS_10_BASE_T (1 &lt;&lt; 9)</span>
489 00480 <span class="comment">#define CS8900_LINE_STATUS_POLARITY_OK (1 &lt;&lt; 12)</span>
490 00481 <span class="comment">#define CS8900_LINE_STATUS_CRS (1 &lt;&lt; 14)</span>
491 00482 <span class="comment"></span>
492 00483 <span class="comment"> * Reg 15. Self Control.</span>
493 00484 <span class="comment">#define CS8900_SELF_CTRL_RESET (1 &lt;&lt; 6)</span>
494 00485 <span class="comment">#define CS8900_SELF_CTRL_SW_SUSPEND (1 &lt;&lt; 8)</span>
495 00486 <span class="comment">#define CS8900_SELF_CTRL_HW_SLEEP (1 &lt;&lt; 9)</span>
496 00487 <span class="comment">#define CS8900_SELF_CTRL_HW_STANDBY (1 &lt;&lt; 10)</span>
497 00488 <span class="comment">#define CS8900_SELF_CTRL_HC0E (1 &lt;&lt; 12)</span>
498 00489 <span class="comment">#define CS8900_SELF_CTRL_HC1E (1 &lt;&lt; 13)</span>
499 00490 <span class="comment">#define CS8900_SELF_CTRL_HCB0 (1 &lt;&lt; 14)</span>
500 00491 <span class="comment">#define CS8900_SELF_CTRL_HCB1 (1 &lt;&lt; 15)</span>
501 00492 <span class="comment"></span>
502 00493 <span class="comment"> * Reg 16. Self Status.</span>
503 00494 <span class="comment">#define CS8900_SELF_STATUS_3_3_V (1 &lt;&lt; 6)</span>
504 00495 <span class="comment">#define CS8900_SELF_STATUS_INITD (1 &lt;&lt; 7)</span>
505 00496 <span class="comment">#define CS8900_SELF_STATUS_SIBUST (1 &lt;&lt; 8)</span>
506 00497 <span class="comment">#define CS8900_SELF_STATUS_EEPROM_PRESENT (1 &lt;&lt; 9) </span>
507 00498 <span class="comment">#define CS8900_SELF_STATUS_EEPROM_OK (1 &lt;&lt; 10)</span>
508 00499 <span class="comment">#define CS8900_SELF_STATUS_EL_PRESENT (1 &lt;&lt; 11)</span>
509 00500 <span class="comment">#define CS8900_SELF_STATUS_EE_SIZE (1 &lt;&lt; 12)</span>
510 00501 <span class="comment"></span>
511 00502 <span class="comment"> * Reg 17. Bus Control.</span>
512 00503 <span class="comment">#define CS8900_BUS_CTRL_RESET_RX_DMA (1 &lt;&lt; 6)</span>
513 00504 <span class="comment">#define CS8900_BUS_CTRL_USE_SA (1 &lt;&lt; 9)</span>
514 00505 <span class="comment">#define CS8900_BUS_CTRL_MEMORY_ENABLE (1 &lt;&lt; 10)</span>
515 00506 <span class="comment">#define CS8900_BUS_CTRL_DMA_BURST (1 &lt;&lt; 11)</span>
516 00507 <span class="comment">#define CS8900_BUS_CTRL_IOCHRDYE (1 &lt;&lt; 12)</span>
517 00508 <span class="comment">#define CS8900_BUS_CTRL_RX_DMA_SIZE (1 &lt;&lt; 13)</span>
518 00509 <span class="comment">#define CS8900_BUS_CTRL_ENABLE_INT (1 &lt;&lt; 15)</span>
519 00510 <span class="comment"></span>
520 00511 <span class="comment"> * Reg 18. Bus Status.</span>
521 00512 <span class="comment">#define CS8900_BUS_STATUS_TX_BID_ERROR (1 &lt;&lt; 7)</span>
522 00513 <span class="comment">#define CS8900_BUS_STATUS_RDY_FOR_TX_NOW (1 &lt;&lt; 8)</span>
523 00514 <span class="comment"></span>
524 00515 <span class="comment">*/</span>
525 </pre></div><hr size="1"><address style="align: right;"><small>Generated on Sun Oct 29 03:41:07 2006 for Procyon AVRlib by&nbsp;
526 <a href="http://www.doxygen.org/index.html">
527 <img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.4.2 </small></address>
528 </body>
529 </html>
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