| Line No. | Rev | Author | Line |
|---|---|---|---|
| 1 | 6 | kaklik | /*! \file lis3l02.h \brief ST LIS3L02 3-axis I2C Accelerometer Library. */ |
| 2 | //***************************************************************************** |
||
| 3 | // |
||
| 4 | // File Name : 'lis3l02.h' |
||
| 5 | // Title : ST LIS3L02 3-axis I2C Accelerometer Library |
||
| 6 | // Author : Pascal Stang - Copyright (C) 2004 |
||
| 7 | // Created : 2004.10.23 |
||
| 8 | // Revised : 2004.12.14 |
||
| 9 | // Version : 0.1 |
||
| 10 | // Target MCU : Atmel AVR Series |
||
| 11 | // Editor Tabs : 4 |
||
| 12 | // |
||
| 13 | // NOTE: This code is currently below version 1.0, and therefore is considered |
||
| 14 | // to be lacking in some functionality or documentation, or may not be fully |
||
| 15 | // tested. Nonetheless, you can expect most functions to work. |
||
| 16 | // |
||
| 17 | /// \ingroup driver_hw |
||
| 18 | /// \defgroup lis3l02 ST LIS3L02 3-axis I2C Accelerometer Library (lis3l02.c) |
||
| 19 | /// \code #include "lis3l02.h" \endcode |
||
| 20 | /// \par Overview |
||
| 21 | /// This library provides an interface to the ST LIS3L02 integrated 3-axis |
||
| 22 | /// accelerometer. The LIS3L02 has a built-in A/D converter to capture analog |
||
| 23 | /// acceleration data and make it available over an I2C interface. |
||
| 24 | // |
||
| 25 | // This code is distributed under the GNU Public License |
||
| 26 | // which can be found at http://www.gnu.org/licenses/gpl.txt |
||
| 27 | // |
||
| 28 | //***************************************************************************** |
||
| 29 | |||
| 30 | #ifndef LIS3L02_H |
||
| 31 | #define LIS3L02_H |
||
| 32 | |||
| 33 | #include "global.h" |
||
| 34 | |||
| 35 | // constants/macros/typdefs |
||
| 36 | #define LIS3L02_I2C_ADDR 0x3A ///< Base I2C address of LIS3L02 device |
||
| 37 | |||
| 38 | // LIS3L02 register address defines |
||
| 39 | #define LIS3L02_REG_OFFSETX 0x16 ///< LIS3L02 X-axis digital offset trim |
||
| 40 | #define LIS3L02_REG_OFFSETY 0x17 ///< LIS3L02 Y-axis digital offset trim |
||
| 41 | #define LIS3L02_REG_OFFSETZ 0x18 ///< LIS3L02 Z-axis digital offset trim |
||
| 42 | #define LIS3L02_REG_GAINX 0x19 ///< LIS3L02 X-axis digital gain trim |
||
| 43 | #define LIS3L02_REG_GAINY 0x1A ///< LIS3L02 Y-axis digital gain trim |
||
| 44 | #define LIS3L02_REG_GAINZ 0x1B ///< LIS3L02 Z-axis digital gain trim |
||
| 45 | #define LIS3L02_REG_CTRLREG1 0x20 ///< LIS3L02 interface/operation control |
||
| 46 | #define LIS3L02_REG_CTRLREG2 0x21 ///< LIS3L02 interface/operation control |
||
| 47 | #define LIS3L02_REG_WAKEUPCFG 0x23 ///< LIS3L02 interrupt/wakeup config |
||
| 48 | #define LIS3L02_REG_WAKEUPSRC 0x24 ///< LIS3L02 interrupt/wakeup source indicator |
||
| 49 | #define LIS3L02_REG_WAKEUPACK 0x25 ///< LIS3L02 wakeup source clear |
||
| 50 | #define LIS3L02_REG_STATUS 0x27 ///< LIS3L02 Accelerometer Status |
||
| 51 | #define LIS3L02_REG_OUTXL 0x28 ///< LIS3L02 Accelerometer X Output Low-byte |
||
| 52 | #define LIS3L02_REG_OUTXH 0x29 ///< LIS3L02 Accelerometer X Output High-byte |
||
| 53 | #define LIS3L02_REG_OUTYL 0x2A ///< LIS3L02 Accelerometer Y Output Low-byte |
||
| 54 | #define LIS3L02_REG_OUTYH 0x2B ///< LIS3L02 Accelerometer Y Output High-byte |
||
| 55 | #define LIS3L02_REG_OUTZL 0x2C ///< LIS3L02 Accelerometer Z Output Low-byte |
||
| 56 | #define LIS3L02_REG_OUTZH 0x2D ///< LIS3L02 Accelerometer Z Output High-byte |
||
| 57 | #define LIS3L02_REG_THSL 0x2E ///< LIS3L02 Accelerometer Threshold Low-byte |
||
| 58 | #define LIS3L02_REG_THSH 0x2F ///< LIS3L02 Accelerometer Threshold High-byte |
||
| 59 | #define LIS3L02_REG_MULTIREAD 0x80 ///< LIS3L02 Mutliple Read Bit |
||
| 60 | |||
| 61 | // LIS3L02 control register 1 bit defines |
||
| 62 | #define LIS3L02_CTRLREG1_XEN 0x01 ///< LIS3L02 CtrlReg1 X-axis Enable |
||
| 63 | #define LIS3L02_CTRLREG1_YEN 0x02 ///< LIS3L02 CtrlReg1 Y-axis Enable |
||
| 64 | #define LIS3L02_CTRLREG1_ZEN 0x04 ///< LIS3L02 CtrlReg1 Z-axis Enable |
||
| 65 | #define LIS3L02_CTRLREG1_ST 0x08 ///< LIS3L02 CtrlReg1 Self-Test Enable |
||
| 66 | #define LIS3L02_CTRLREG1_DF0 0x10 ///< LIS3L02 CtrlReg1 Decimation Factor 0 |
||
| 67 | #define LIS3L02_CTRLREG1_DF1 0x20 ///< LIS3L02 CtrlReg1 Decimation Factor 0 |
||
| 68 | #define LIS3L02_CTRLREG1_PD0 0x40 ///< LIS3L02 CtrlReg1 Power-down Control 0 |
||
| 69 | #define LIS3L02_CTRLREG1_PD1 0x80 ///< LIS3L02 CtrlReg1 Power-down Control 1 |
||
| 70 | |||
| 71 | // LIS3L02 control register 2 bit defines |
||
| 72 | #define LIS3L02_CTRLREG2_DAS 0x01 ///< LIS3L02 CtrlReg2 Data Alignment Selection |
||
| 73 | #define LIS3L02_CTRLREG2_SIM 0x02 ///< LIS3L02 CtrlReg2 SPI Mode Select |
||
| 74 | #define LIS3L02_CTRLREG2_DRDY 0x04 ///< LIS3L02 CtrlReg2 Enable Data-Ready generation |
||
| 75 | #define LIS3L02_CTRLREG2_IEN 0x08 ///< LIS3L02 CtrlReg2 Interrupt Enable |
||
| 76 | #define LIS3L02_CTRLREG2_BOOT 0x10 ///< LIS3L02 CtrlReg2 Reboot from memory |
||
| 77 | #define LIS3L02_CTRLREG2_FS 0x80 ///< LIS3L02 CtrlReg2 Full-scale Select (0=2g, 1=6g) |
||
| 78 | |||
| 79 | // LIS3L02 WAKEUPCFG register bit defines |
||
| 80 | #define LIS3L02_WAKEUPCFG_MXL 0x01 ///< LIS3L02 WAKEUPCFG Mask X Low Interrupt |
||
| 81 | #define LIS3L02_WAKEUPCFG_MXH 0x02 ///< LIS3L02 WAKEUPCFG Mask X High Interrupt |
||
| 82 | #define LIS3L02_WAKEUPCFG_MYL 0x04 ///< LIS3L02 WAKEUPCFG Mask Y Low Interrupt |
||
| 83 | #define LIS3L02_WAKEUPCFG_MYH 0x08 ///< LIS3L02 WAKEUPCFG Mask Y High Interrupt |
||
| 84 | #define LIS3L02_WAKEUPCFG_MZL 0x10 ///< LIS3L02 WAKEUPCFG Mask Z Low Interrupt |
||
| 85 | #define LIS3L02_WAKEUPCFG_MZH 0x20 ///< LIS3L02 WAKEUPCFG Mask Z High Interrupt |
||
| 86 | #define LIS3L02_WAKEUPCFG_LIR 0x40 ///< LIS3L02 WAKEUPCFG Latch Intr Request |
||
| 87 | |||
| 88 | // LIS3L02 WAKEUPSRC register bit defines |
||
| 89 | #define LIS3L02_WAKEUPSRC_XL 0x01 ///< LIS3L02 WAKEUPSRC X Low Interrupt |
||
| 90 | #define LIS3L02_WAKEUPSRC_XH 0x02 ///< LIS3L02 WAKEUPSRC X High Interrupt |
||
| 91 | #define LIS3L02_WAKEUPSRC_YL 0x04 ///< LIS3L02 WAKEUPSRC Y Low Interrupt |
||
| 92 | #define LIS3L02_WAKEUPSRC_YH 0x08 ///< LIS3L02 WAKEUPSRC Y High Interrupt |
||
| 93 | #define LIS3L02_WAKEUPSRC_ZL 0x10 ///< LIS3L02 WAKEUPSRC Z Low Interrupt |
||
| 94 | #define LIS3L02_WAKEUPSRC_ZH 0x20 ///< LIS3L02 WAKEUPSRC Z High Interrupt |
||
| 95 | #define LIS3L02_WAKEUPSRC_IA 0x40 ///< LIS3L02 WAKEUPSRC Interrupt Active |
||
| 96 | |||
| 97 | // LIS3L02 WAKEUPSRC register bit defines |
||
| 98 | #define LIS3L02_STATUS_XDA 0x01 ///< LIS3L02 STATUS X New Data Available |
||
| 99 | #define LIS3L02_STATUS_YDA 0x02 ///< LIS3L02 STATUS Y New Data Available |
||
| 100 | #define LIS3L02_STATUS_ZDA 0x04 ///< LIS3L02 STATUS Z New Data Available |
||
| 101 | #define LIS3L02_STATUS_ZYXDA 0x08 ///< LIS3L02 STATUS XYZ New Data Available |
||
| 102 | #define LIS3L02_STATUS_XOR 0x10 ///< LIS3L02 STATUS X-axis Data Overrun |
||
| 103 | #define LIS3L02_STATUS_YOR 0x20 ///< LIS3L02 STATUS Y-axis Data Overrun |
||
| 104 | #define LIS3L02_STATUS_ZOR 0x40 ///< LIS3L02 STATUS Z-axis Data Overrun |
||
| 105 | #define LIS3L02_STATUS_ZYXOR 0x80 ///< LIS3L02 STATUS XYZ-axis Data Overrun |
||
| 106 | |||
| 107 | // functions |
||
| 108 | |||
| 109 | //! Initialize the LIS3L02 chip. |
||
| 110 | /// returns: |
||
| 111 | /// 0 if successful, |
||
| 112 | /// non-zero if unsuccessful (chip not present). |
||
| 113 | u08 lis3l02Init(void); |
||
| 114 | |||
| 115 | //! Reset the LIS3L02 chip. |
||
| 116 | u08 lis3l02Reset(void); |
||
| 117 | |||
| 118 | //! Read a LIS3L02 register. |
||
| 119 | u08 lis3l02ReadReg(u08 reg); |
||
| 120 | |||
| 121 | //! Write a LIS3L02 register. |
||
| 122 | u08 lis3l02WriteReg(u08 reg, u08 data); |
||
| 123 | |||
| 124 | //! Get an acceleration reading from the LIS3L02 sensor. |
||
| 125 | s16 lis3l02GetAccel(u08 chxyz); |
||
| 126 | |||
| 127 | #endif |
Powered by WebSVN v2.8.3