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Blame information for rev 6

Line No.	Rev	Author	Line
1	6	kaklik	`/! \file megaioreg.h \brief MegaIO register definitions. /`
2			`//*****************************************************************************`
3			`//`
4			`// File Name : 'megaioreg.h'`
5			`// Title : MegaIO register definitions`
6			`// Author : Pascal Stang - Copyright (C) 2003`
7			`// Created : 2003.07.16`
8			`// Revised : 2003.07.17`
9			`// Version : 0.1`
10			`// Target MCU : Atmel AVR series`
11			`// Editor Tabs : 4`
12			`//`
13			`// This code is distributed under the GNU Public License`
14			`// which can be found at http://www.gnu.org/licenses/gpl.txt`
15			`//`
16			`//*****************************************************************************`
17
18			`#ifndef MEGAIOREG_H`
19			`#define MEGAIOREG_H`
20
21			`// define MEGAIO I2C address`
22			`#define MEGAIO_I2C_ADDR 0x4C`
23
24			`// define MEGAIO registers`
25			`// General Registers`
26			`#define MEGAIOREG_IDSTRING 0x00`
27
28			`// UART Registers`
29			`#define MEGAIOREG_UARTDATA 0x10`
30			`#define MEGAIOREG_UARTBAUD 0x14`
31			`#define MEGAIOREG_UARTBAUDSEL 0x15`
32			`#define MEGAIOREG_UARTRXBUFBYTES 0x18`
33			`#define MEGAIOREG_UARTTXBUFBYTES 0x19`
34
35			`// PWM Registers`
36			`#define MEGAIOREG_PWM1CTRL 0x20`
37			`#define MEGAIOREG_PWM1FREQ 0x21`
38			`#define MEGAIOREG_PWM1ADUTY 0x24`
39			`#define MEGAIOREG_PWM1BDUTY 0x25`
40
41			`// A/D Converter Registers`
42			`#define MEGAIOREG_ADCCTRL 0x30`
43			`#define MEGAIOREG_ADCCHSEL 0x31`
44			`#define MEGAIOREG_ADCRESULT 0x32`
45
46			`// PORT Access Registers`
47			`#define MEGAIOREG_PORTA 0x40`
48			`#define MEGAIOREG_DDRA 0x41`
49			`#define MEGAIOREG_PINA 0x42`
50			`#define MEGAIOREG_PORTB 0x43`
51			`#define MEGAIOREG_DDRB 0x44`
52			`#define MEGAIOREG_PINB 0x45`
53			`#define MEGAIOREG_PORTC 0x46`
54			`#define MEGAIOREG_DDRC 0x47`
55			`#define MEGAIOREG_PINC 0x48`
56			`#define MEGAIOREG_PORTD 0x49`
57			`#define MEGAIOREG_DDRD 0x4A`
58			`#define MEGAIOREG_PIND 0x4B`
59			`#define MEGAIOREG_PORTE 0x4C`
60			`#define MEGAIOREG_DDRE 0x4D`
61			`#define MEGAIOREG_PINE 0x4E`
62			`#define MEGAIOREG_PORTF 0x4F`
63			`#define MEGAIOREG_DDRF 0x50`
64			`#define MEGAIOREG_PINF 0x51`
65
66			`// Direct Access Registers`
67			`#define MEGAIOREG_DIRECTIO 0x80`
68			`#define MEGAIOREG_DIRECTMEM 0x81`
69
70			`// MegaIO configuration`
71			`#define MEGAIOREG_I2CADDR 0xF0`
72			`#define MEGAIOREG_OSCCAL 0xF1`
73
74			`// MegaIO configuration cookie`
75			`// You must send this cookie to validate all configuration requests`
76			`#define MEGAIO_CONFIG_COOKIE 0xB4C3`
77
78			`// define MEGAIO register values`
79			`#define UARTBAUDSEL_300 0x00`
80			`#define UARTBAUDSEL_600 0x01`
81			`#define UARTBAUDSEL_1200 0x02`
82			`#define UARTBAUDSEL_2400 0x03`
83			`#define UARTBAUDSEL_4800 0x04`
84			`#define UARTBAUDSEL_9600 0x05`
85			`#define UARTBAUDSEL_19200 0x06`
86			`#define UARTBAUDSEL_38400 0x07`
87			`#define UARTBAUDSEL_115200 0x08`
88
89			`#define PWM1FREQ_STOP 0x00`
90			`#define PWM1FREQ_MAX 0x01`
91			`#define PWM1FREQ_DIV8 0x02`
92			`#define PWM1FREQ_DIV64 0x03`
93			`#define PWM1FREQ_DIV256 0x04`
94			`#define PWM1FREQ_DIV1024 0x05`
95
96			`#endif`