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library

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Blame information for rev 6

Line No. Rev Author Line
1 6 kaklik /*! \file ax88796.h \brief ASIX AX88796 Ethernet Interface Driver. */
2 //*****************************************************************************
3 //
4 // File Name : 'ax88796.h'
5 // Title : ASIX AX88796 Ethernet Interface Driver
6 // Author : Pascal Stang
7 // Created : 10/22/2002
8 // Revised : 8/22/2005
9 // Version : 0.1
10 // Target MCU : Atmel AVR series
11 // Editor Tabs : 4
12 //
13 /// \ingroup network
14 /// \defgroup ax88796 ASIX AX88796 Ethernet Interface Driver (ax88796.c)
15 /// \code #include "net/ax88796.h" \endcode
16 /// \par Overview
17 /// This driver provides initialization and transmit/receive
18 /// functions for the ASIX AX88796 10/100Mb Ethernet Controller and PHY.
19 ///
20 /// Based in part on code by Louis Beaudoin (www.embedded-creations.com).
21 /// Thanks to Adam Dunkels and Louis Beaudoin for providing the initial
22 /// structure in which to write this driver.
23 //
24 //*****************************************************************************
25 //@{
26  
27 #ifndef AX88796_H
28 #define AX88796_H
29  
30 #include "global.h"
31  
32 #define nop() asm volatile ("nop")
33  
34 // AX88796/NE2000 Control Register Offsets
35 // Page 0 - Read/Write
36 #define CR 0x00 // Command Register
37 #define PSTART 0x01 // Page Start Register
38 #define PSTOP 0x02 // Page Stop Register
39 #define BNRY 0x03 // Boundary Pointer
40 #define RDMAPORT 0x10 // DMA Data Port
41 #define MEMR 0x14 // MII/EEPROM Access Register
42 #define TR 0x15 // Test Register
43 #define SPP_DPR 0x18 // Standard Printer Port Data
44 #define SSP_SPR 0x19 // Standard Printer Port Status
45 #define SSP_CPR 0x1A // Standard Printer Port Control
46 // Page 0 - Read
47 #define TSR 0x04 // Transmit Status Register
48 #define NCR 0x05 // Number of Collisions Register
49 #define ISR 0x07 // Interrupt Status Register
50 #define CRDA0 0x08 // Current Remote DMA Address 0
51 #define CRDA1 0x09 // Current Remote DMA Address 1
52 #define RSR 0x0C // Receive Status Register
53 #define CNTR0 0x0D
54 #define CNTR1 0x0E
55 #define CNTR2 0x0F
56 #define GPI 0x17 // General-Purpose Input
57 #define RSTPORT 0x1F // Reset
58 // Page 0 - Write
59 #define TPSR 0x04 // Transmit Page Start Address
60 #define TBCR0 0x05 // Transmit Byte Count Register 0
61 #define TBCR1 0x06 // Transmit Byte Count Register 1
62 #define RSAR0 0x08 // Remote Start Address Register 0
63 #define RSAR1 0x09 // Remote Start Address Register 1
64 #define RBCR0 0x0A // Remote Byte Count 0
65 #define RBCR1 0x0B // Remote Byte Count 1
66 #define RCR 0x0C // Receive Config Register
67 #define TCR 0x0D // Transmit Config Register
68 #define DCR 0x0E // Data Config Register
69 #define IMR 0x0F // Interrupt Mask Register
70 #define GPOC 0x17 // General-Purpose Output Control
71 // Page 1 - Read/Write
72 #define PAR0 0x01 // Physical Address Register 0
73 #define PAR1 0x02 // Physical Address Register 0
74 #define PAR2 0x03 // Physical Address Register 0
75 #define PAR3 0x04 // Physical Address Register 0
76 #define PAR4 0x05 // Physical Address Register 0
77 #define PAR5 0x06 // Physical Address Register 0
78 #define CURR 0x07 // Page 1
79 #define CPR 0x07 // Current Page Register
80  
81 // AX88796 CR Register Bit Definitions
82 #define PS1 0x80
83 #define PS0 0x40
84 #define RD2 0x20
85 #define RD1 0x10
86 #define RD0 0x08
87 #define TXP 0x04
88 #define START 0x02
89 #define STOP 0x01
90 // AX88796 RCR Register Bit Definitions
91 #define INTT 0x40
92 #define MON 0x20
93 #define PRO 0x10
94 #define AM 0x08
95 #define AB 0x04
96 #define AR 0x02
97 #define SEP 0x01
98 // AX88796 ISR Register Bit Definitions
99 #define RST 0x80
100 #define RDC 0x40
101 #define OVW 0x10
102 #define RXE 0x08
103 #define TXE 0x04
104 #define PTX 0x02
105 #define PRX 0x01
106 // AX88796 TEST Register Bit Definitions
107 #define AUTOD 0x01
108 #define RST_B 0x02
109 #define RST_10B 0x04
110 #define RST_TXB 0x08
111 // AX88796 GPOC Register Bit Definitions
112 #define GPO0 0x01
113 #define MPSEL 0x10
114 #define MPSET 0x20
115 #define PPDSET 0x40
116 // AX88796 MEMR Register Bit Definitions
117 #define MDC 0x01
118 #define MDIR 0x02
119 #define MDI 0x04
120 #define MDO 0x08
121 #define EECS 0x10
122 #define EEI 0x20
123 #define EEO 0x40
124 #define EECLK 0x80
125 // AX88796 GPI Register Bit Definitions
126 #define GPI2 0x40
127 #define GPI1 0x20
128 #define GPI0 0x10
129 #define I_SPD 0x04
130 #define I_DPX 0x02
131 #define I_LINK 0x01
132 // AX88796 TCR Register Bit Definitions
133 #define FDU 0x80 // full duplex
134 #define PD 0x40 // pad disable
135 #define RLO 0x20 // retry of late collisions
136 #define LB1 0x04 // loopback 1
137 #define LB0 0x02 // loopback 0
138 #define CRC 0x01 // generate CRC
139  
140 // AX88796 Initial Register Values
141 // RCR : INT trigger active high and Accept Broadcast ENET packets
142 #define RCR_INIT (INTT | AB)
143 #define DCR_INIT 0x00 // was 0x58 for realtek RTL8019
144 // TCR : default transmit operation - CRC is generated
145 #define TCR_INIT 0x00
146 // IMR : interrupt enabled for receive and overrun events
147 #define IMR_INIT 0x11 // PRX and OVW interrupt enabled
148 // buffer boundaries
149 // transmit has 6 256-byte pages
150 // receive has 26 256-byte pages
151 // entire available packet buffer space is allocated
152 #define TXSTART_INIT 0x40
153 #define RXSTART_INIT 0x46
154 #define RXSTOP_INIT 0x60
155  
156 // Ethernet constants
157 #define ETHERNET_MIN_PACKET_LENGTH 0x3C
158 //#define ETHERNET_HEADER_LENGTH 0x0E
159  
160 // offsets into ax88796 ethernet packet header
161 #define PKTHEADER_STATUS 0x00 // packet status
162 #define PKTHEADER_NEXTPAGE 0x01 // next buffer page
163 #define PKTHEADER_PKTLENL 0x02 // packet length low
164 #define PKTHEADER_PKTLENH 0x03 // packet length high
165  
166  
167 // functions
168 #include "nic.h"
169  
170 // setup ports for I/O
171 void ax88796SetupPorts(void);
172  
173 // read ax88796 register
174 u08 ax88796Read(u08 address);
175  
176 // write ax88796 register
177 void ax88796Write(u08 address, u08 data);
178  
179 // initialize the ethernet interface for transmit/receive
180 void ax88796Init(void);
181  
182 // packet transmit functions
183 void ax88796BeginPacketSend(unsigned int packetLength);
184 void ax88796SendPacketData(unsigned char * localBuffer, unsigned int length);
185 void ax88796EndPacketSend(void);
186  
187 // packet receive functions
188 unsigned int ax88796BeginPacketRetreive(void);
189 void ax88796RetreivePacketData(unsigned char *localBuffer, unsigned int length);
190 void ax88796EndPacketRetreive(void);
191  
192 // Processes AX88796 interrupts.
193 // Currently, this function looks only for a receive overflow condition.
194 // The function need not be called in response to an interrupt,
195 // but can be executed just before checking the receive buffer for incoming packets.
196 void ax88796ProcessInterrupt(void);
197  
198 // execute procedure for recovering from a receive overflow
199 // this should be done when the receive memory fills up with packets
200 void ax88796ReceiveOverflowRecover(void);
201  
202 // Write MII Registers
203 void ax88796WriteMii(unsigned char phyad,unsigned char regad,unsigned int mii_data);
204 // Read MII Registers
205 unsigned int ax88796ReadMii(unsigned char phyad,unsigned char regad);
206  
207 // formatted print of all important AX88796 registers
208 void ax88796RegDump(void);
209  
210 #endif
211 //@}
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