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Blame information for rev 6

Line No.	Rev	Author	Line
1	6	kaklik	`/! \file ax88796conf.h \brief ASIX AX88796 Ethernet Interface Driver Configuration. /`
2			`//*****************************************************************************`
3			`//`
4			`// File Name : 'ax88796conf.h'`
5			`// Title : ASIX AX88796 Ethernet Interface Driver Configuration`
6			`// Author : Pascal Stang`
7			`// Created : 10/22/2002`
8			`// Revised : 8/22/2005`
9			`// Version : 0.1`
10			`// Target MCU : Atmel AVR series`
11			`// Editor Tabs : 4`
12			`//`
13			`// Description : This driver provides initialization and transmit/receive`
14			`// functions for the ASIX AX88796 10/100Mb Ethernet Controller and PHY.`
15			`//`
16			`// This code is distributed under the GNU Public License`
17			`// which can be found at http://www.gnu.org/licenses/gpl.txt`
18			`//`
19			`//*****************************************************************************`
20
21			`#ifndef AX88796CONF_H`
22			`#define AX88796CONF_H`
23
24			`// This driver supports an AX88796 connected in memory-mapped or direct I/O mode.`
25			`//`
26			`#define GENERAL_IO 0`
27			`// Direct I/O mode assumes the AX88796 address, data, and control lines are`
28			`// connected directly to processor I/O pins. The memory-bus accesses are`
29			`// software emulated.`
30			`//`
31			`#define MEMORY_MAPPED 1`
32			`// Memory-mapped mode assumes that the AX88796 is connected the processor via`
33			`// the external memory bus, and that the AX88796 address space starts at the`
34			`// memory location AX88796_MEMORY_MAPPED_OFFSET.`
35			`//`
36			`// In either mode, a seperate I/O pins is required for control of the AX88796's`
37			`// hardware RESET line.`
38
39			`// set the connection type used to communicate with the NIC`
40			`#define NIC_CONNECTION GENERAL_IO`
41
42
43			`#if NIC_CONNECTION != GENERAL_IO`
44			`// NIC is memory-mapped starting at this address`
45			`#define AX88796_MEMORY_MAPPED_OFFSET 0x2000`
46			`#else // NIC Interface through General I/O`
47			`// AX88796 address port`
48			`#define AX88796_ADDRESS_PORT PORTB`
49			`#define AX88796_ADDRESS_DDR DDRB`
50			`#define AX88796_ADDRESS_MASK 0x1F`
51			`// AX88796 data port`
52			`#define AX88796_DATA_PORT PORTA`
53			`#define AX88796_DATA_DDR DDRA`
54			`#define AX88796_DATA_PIN PINA`
55			`// AX88796 control port`
56			`#define AX88796_CONTROL_PORT PORTD`
57			`#define AX88796_CONTROL_DDR DDRD`
58			`#define AX88796_CONTROL_READPIN PD5`
59			`#define AX88796_CONTROL_WRITEPIN PD4`
60			`#endif`
61
62			`// AX88796 RESET pin`
63			`#define AX88796_RESET_PORT PORTD`
64			`#define AX88796_RESET_DDR DDRD`
65			`#define AX88796_RESET_PIN PD6`
66
67			`// MAC address for this interface`
68			`#ifdef ETHADDR0`
69			`#define AX88796_MAC0 ETHADDR0`
70			`#define AX88796_MAC1 ETHADDR1`
71			`#define AX88796_MAC2 ETHADDR2`
72			`#define AX88796_MAC3 ETHADDR3`
73			`#define AX88796_MAC4 ETHADDR4`
74			`#define AX88796_MAC5 ETHADDR5`
75			`#else`
76			`#define AX88796_MAC0 '0'`
77			`#define AX88796_MAC1 'F'`
78			`#define AX88796_MAC2 'F'`
79			`#define AX88796_MAC3 'I'`
80			`#define AX88796_MAC4 'C'`
81			`#define AX88796_MAC5 'E'`
82			`#endif`
83
84			`#endif`