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library

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Blame information for rev 6

Line No.	Rev	Author	Line
1	6	kaklik	`/! \file prism2conf.h \brief Prism2 802.11b Wireless-LAN Interface Driver Configuration. /`
2			`//*****************************************************************************`
3			`//`
4			`// File Name : 'prism2conf.h'`
5			`// Title : Prism2 802.11b Wireless-LAN Interface Driver Configuration`
6			`// Author : Pascal Stang`
7			`// Created : 12/27/2004`
8			`// Revised : 1/7/2005`
9			`// Version : 0.1`
10			`// Target MCU : Atmel AVR series`
11			`// Editor Tabs : 4`
12			`//`
13			`/// \ingroup network`
14			`//`
15			`// Description : This is the configuration file for the Prism2 802.11b`
16			`// Wireless-LAN Controller Driver.`
17			`//`
18			`//*****************************************************************************`
19
20			`#ifndef PRISM2CONF_H`
21			`#define PRISM2CONF_H`
22
23			`// This driver supports a PRISM2 NIC connected in memory-mapped or direct I/O mode.`
24			`//`
25			`#define GENERAL_IO 0`
26			`// Direct I/O mode assumes the NIC address, data, and control lines are`
27			`// connected directly to processor I/O pins. The memory-bus accesses are`
28			`// software emulated.`
29			`//`
30			`#define MEMORY_MAPPED 1`
31			`// * MEMORY-MAPPED NOT YET IMPLEMENTED *`
32			`// Memory-mapped mode assumes that the NIC is connected the processor via`
33			`// the external memory bus, and that the NIC address space starts at the`
34			`// memory location PRISM2_MEMORY_MAPPED_OFFSET.`
35			`//`
36			`// In either mode, a seperate I/O pins is required for control of the NIC's`
37			`// hardware RESET line.`
38
39			`// set the connection type used to communicate with the NIC`
40			`#define NIC_CONNECTION GENERAL_IO`
41
42			`#if NIC_CONNECTION != GENERAL_IO`
43			`// NIC is memory-mapped starting at this address`
44			`#define PRISM2_MEMORY_MAPPED_OFFSET 0x8000`
45			`#else // NIC Interface through General I/O`
46			`// PRISM2 address port`
47			`#define PRISM2_ADDRESS_PORT PORTA`
48			`#define PRISM2_ADDRESS_DDR DDRA`
49			`#define PRISM2_ADDRESS_MASK 0xFF`
50			`// PRISM2 high address port`
51			`#define PRISM2_HADDRESS_PORT PORTF`
52			`#define PRISM2_HADDRESS_DDR DDRF`
53			`#define PRISM2_HADDRESS_MASK 0x07`
54			`// PRISM2 data port`
55			`#define PRISM2_DATA_PORT PORTC`
56			`#define PRISM2_DATA_DDR DDRC`
57			`#define PRISM2_DATA_PIN PINC`
58			`// PRISM2 control port`
59			`#define PRISM2_CONTROL_PORT PORTG`
60			`#define PRISM2_CONTROL_DDR DDRG`
61			`#define PRISM2_CONTROL_IORD 1`
62			`#define PRISM2_CONTROL_IOWR 2`
63			`#define PRISM2_CONTROL_MEMRD 0`
64			`#define PRISM2_CONTROL_MEMWR 3`
65			`// Set PRISM2 memory and I/O bus access delay`
66			`// NOTE: PRISM2 cards may not respond correctly if access time is too short or too long`
67			`// Typically good settings: MEM = ~12us, I/O = ~1us`
68			`#define PRISM2_MEM_ACCESS_DELAY delay_us(12)`
69			`#define PRISM2_IO_ACCESS_DELAY { nop(); nop(); nop(); nop(); nop(); nop(); nop(); nop(); }`
70			`//#define PRISM2_IO_ACCESS_DELAY { nop(); nop(); nop(); nop(); nop(); nop(); nop(); nop(); nop(); nop(); nop(); nop(); }`
71			`#endif`
72
73			`// PRISM2 RESET pin`
74			`#define PRISM2_RESET_PORT PORTG`
75			`#define PRISM2_RESET_DDR DDRG`
76			`#define PRISM2_RESET_PIN 4`
77
78
79
80			`// MAC address for this interface`
81			`#ifdef ETHADDR0`
82			`#define PRISM2_MAC0 ETHADDR0`
83			`#define PRISM2_MAC1 ETHADDR1`
84			`#define PRISM2_MAC2 ETHADDR2`
85			`#define PRISM2_MAC3 ETHADDR3`
86			`#define PRISM2_MAC4 ETHADDR4`
87			`#define PRISM2_MAC5 ETHADDR5`
88			`#else`
89			`#define PRISM2_MAC0 '0'`
90			`#define PRISM2_MAC1 'F'`
91			`#define PRISM2_MAC2 'F'`
92			`#define PRISM2_MAC3 'I'`
93			`#define PRISM2_MAC4 'C'`
94			`#define PRISM2_MAC5 'E'`
95			`#endif`
96
97			`#endif`