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Blame information for rev 6

Line No.	Rev	Author	Line
1	6	kaklik	`/! \file cs8900.h \brief Crystal CS8900 Ethernet Interface Driver. /`
2			`//*****************************************************************************`
3			`//`
4			`// File Name : 'cs8900.h'`
5			`// Title : Crystal CS8900 Ethernet Interface Driver`
6			`// Author : Pascal Stang`
7			`// Created : 11/7/2004`
8			`// Revised : 8/22/2005`
9			`// Version : 0.1`
10			`// Target MCU : Atmel AVR series`
11			`// Editor Tabs : 4`
12			`//`
13			`/// \ingroup network`
14			`/// \defgroup cs8900 Crystal CS8900 Ethernet Interface Driver (cs8900.c)`
15			`/// \code #include "net/cs8900.h" \endcode`
16			`/// \par Overview`
17			`/// This driver provides initialization and transmit/receive`
18			`/// functions for the Crystal CS8900 10Mb Ethernet Controller and PHY.`
19			`//`
20			`//*****************************************************************************`
21			`//@{`
22
23			`#ifndef CS8900_H`
24			`#define CS8900_H`
25
26			`#include "global.h"`
27
28			`#define nop() asm volatile ("nop")`
29
30
31			`// Crystal ESIA product ID`
32			`#define CS8900_ESIA_ID (0x630e)`
33
34			`// CS8900 IO Registers`
35			`#define CS8900_IO_RXTX_DATA_PORT0 (0x0000)`
36			`#define CS8900_IO_RXTX_DATA_PORT1 (0x0002)`
37			`#define CS8900_IO_TXCMD (0x0004)`
38			`#define CS8900_IO_TXLENGTH (0x0006)`
39			`#define CS8900_IO_ISQ (0x0008)`
40			`#define CS8900_IO_PP_PTR (0x000a)`
41			`#define CS8900_IO_PP_DATA_PORT0 (0x000c)`
42			`#define CS8900_IO_PP_DATA_PORT1 (0x000e)`
43
44			`// definitions for Crystal CS8900 ethernet-controller`
45			`// based on linux-header by Russel Nelson`
46
47			`#define PP_ChipID 0x0000 // offset 0h -> Corp-ID`
48			`// offset 2h -> Model/Product Number`
49			`// offset 3h -> Chip Revision Number`
50
51			`#define PP_ISAIOB 0x0020 // IO base address`
52			`#define PP_CS8900_ISAINT 0x0022 // ISA interrupt select`
53			`#define PP_CS8900_ISADMA 0x0024 // ISA Rec DMA channel`
54			`#define PP_ISASOF 0x0026 // ISA DMA offset`
55			`#define PP_DmaFrameCnt 0x0028 // ISA DMA Frame count`
56			`#define PP_DmaByteCnt 0x002A // ISA DMA Byte count`
57			`#define PP_CS8900_ISAMemB 0x002C // Memory base`
58			`#define PP_ISABootBase 0x0030 // Boot Prom base`
59			`#define PP_ISABootMask 0x0034 // Boot Prom Mask`
60			`#define PP_RxFrameByteCnt 0x0050`
61
62			`// EEPROM data and command registers`
63			`#define PP_EECMD 0x0040 // NVR Interface Command register`
64			`#define PP_EEData 0x0042 // NVR Interface Data Register`
65
66			`// Configuration and control registers`
67			`#define PP_RxCFG 0x0102 // Rx Bus config`
68			`#define PP_RxCTL 0x0104 // Receive Control Register`
69			`#define PP_TxCFG 0x0106 // Transmit Config Register`
70			`#define PP_TxCMD 0x0108 // Transmit Command Register`
71			`#define PP_BufCFG 0x010A // Bus configuration Register`
72			`#define PP_LineCTL 0x0112 // Line Config Register`
73			`#define PP_SelfCTL 0x0114 // Self Command Register`
74			`#define PP_BusCTL 0x0116 // ISA bus control Register`
75			`#define PP_TestCTL 0x0118 // Test Register`
76
77			`// Status and Event Registers`
78			`#define PP_ISQ 0x0120 // Interrupt Status`
79			`#define PP_RxEvent 0x0124 // Rx Event Register`
80			`#define PP_TxEvent 0x0128 // Tx Event Register`
81			`#define PP_BufEvent 0x012C // Bus Event Register`
82			`#define PP_RxMiss 0x0130 // Receive Miss Count`
83			`#define PP_TxCol 0x0132 // Transmit Collision Count`
84			`#define PP_LineST 0x0134 // Line State Register`
85			`#define PP_SelfST 0x0136 // Self State register`
86			`#define PP_BusST 0x0138 // Bus Status`
87			`#define PP_TDR 0x013C // Time Domain Reflectometry`
88
89			`// Initiate Transmit Registers`
90			`#define PP_TxCommand 0x0144 // Tx Command`
91			`#define PP_TxLength 0x0146 // Tx Length`
92
93			`// Address Filter Registers`
94			`#define PP_LAF 0x0150 // Hash Table`
95			`#define PP_IA 0x0158 // Physical Address Register`
96
97			`// Frame Location`
98			`#define PP_RxStatus 0x0400 // Receive start of frame`
99			`#define PP_RxLength 0x0402 // Receive Length of frame`
100			`#define PP_RxFrame 0x0404 // Receive frame pointer`
101			`#define PP_TxFrame 0x0A00 // Transmit frame pointer`
102
103			`// Primary I/O Base Address. If no I/O base is supplied by the user, then this`
104			`// can be used as the default I/O base to access the PacketPage Area.`
105			`#define DEFAULTIOBASE 0x0300`
106
107			`// PP_RxCFG - Receive Configuration and Interrupt Mask bit definition - Read/write`
108			`#define SKIP_1 0x0040`
109			`#define RX_STREAM_ENBL 0x0080`
110			`#define RX_OK_ENBL 0x0100`
111			`#define RX_DMA_ONLY 0x0200`
112			`#define AUTO_RX_DMA 0x0400`
113			`#define BUFFER_CRC 0x0800`
114			`#define RX_CRC_ERROR_ENBL 0x1000`
115			`#define RX_RUNT_ENBL 0x2000`
116			`#define RX_EXTRA_DATA_ENBL 0x4000`
117
118			`// PP_RxCTL - Receive Control bit definition - Read/write`
119			`#define RX_IA_HASH_ACCEPT 0x0040`
120			`#define RX_PROM_ACCEPT 0x0080`
121			`#define RX_OK_ACCEPT 0x0100`
122			`#define RX_MULTCAST_ACCEPT 0x0200`
123			`#define RX_IA_ACCEPT 0x0400`
124			`#define RX_BROADCAST_ACCEPT 0x0800`
125			`#define RX_BAD_CRC_ACCEPT 0x1000`
126			`#define RX_RUNT_ACCEPT 0x2000`
127			`#define RX_EXTRA_DATA_ACCEPT 0x4000`
128
129			`// PP_TxCFG - Transmit Configuration Interrupt Mask bit definition - Read/write`
130			`#define TX_LOST_CRS_ENBL 0x0040`
131			`#define TX_SQE_ERROR_ENBL 0x0080`
132			`#define TX_OK_ENBL 0x0100`
133			`#define TX_LATE_COL_ENBL 0x0200`
134			`#define TX_JBR_ENBL 0x0400`
135			`#define TX_ANY_COL_ENBL 0x0800`
136			`#define TX_16_COL_ENBL 0x8000`
137
138			`// PP_TxCMD - Transmit Command bit definition - Read-only and`
139			`// PP_TxCommand - Write-only`
140			`#define TX_START_5_BYTES 0x0000`
141			`#define TX_START_381_BYTES 0x0040`
142			`#define TX_START_1021_BYTES 0x0080`
143			`#define TX_START_ALL_BYTES 0x00C0`
144			`#define TX_FORCE 0x0100`
145			`#define TX_ONE_COL 0x0200`
146			`#define TX_NO_CRC 0x1000`
147			`#define TX_RUNT 0x2000`
148
149			`// PP_BufCFG - Buffer Configuration Interrupt Mask bit definition - Read/write`
150			`#define GENERATE_SW_INTERRUPT 0x0040`
151			`#define RX_DMA_ENBL 0x0080`
152			`#define READY_FOR_TX_ENBL 0x0100`
153			`#define TX_UNDERRUN_ENBL 0x0200`
154			`#define RX_MISS_ENBL 0x0400`
155			`#define RX_128_BYTE_ENBL 0x0800`
156			`#define TX_COL_COUNT_OVRFLOW_ENBL 0x1000`
157			`#define RX_MISS_COUNT_OVRFLOW_ENBL 0x2000`
158			`#define RX_DEST_MATCH_ENBL 0x8000`
159
160			`// PP_LineCTL - Line Control bit definition - Read/write`
161			`#define SERIAL_RX_ON 0x0040`
162			`#define SERIAL_TX_ON 0x0080`
163			`#define AUI_ONLY 0x0100`
164			`#define AUTO_AUI_10BASET 0x0200`
165			`#define MODIFIED_BACKOFF 0x0800`
166			`#define NO_AUTO_POLARITY 0x1000`
167			`#define TWO_PART_DEFDIS 0x2000`
168			`#define LOW_RX_SQUELCH 0x4000`
169
170			`// PP_SelfCTL - Software Self Control bit definition - Read/write`
171			`#define POWER_ON_RESET 0x0040`
172			`#define SW_STOP 0x0100`
173			`#define SLEEP_ON 0x0200`
174			`#define AUTO_WAKEUP 0x0400`
175			`#define HCB0_ENBL 0x1000`
176			`#define HCB1_ENBL 0x2000`
177			`#define HCB0 0x4000`
178			`#define HCB1 0x8000`
179
180			`// PP_BusCTL - ISA Bus Control bit definition - Read/write`
181			`#define RESET_RX_DMA 0x0040`
182			`#define MEMORY_ON 0x0400`
183			`#define DMA_BURST_MODE 0x0800`
184			`#define IO_CHANNEL_READY_ON 0x1000`
185			`#define RX_DMA_SIZE_64K 0x2000`
186			`#define ENABLE_IRQ 0x8000`
187
188			`// PP_TestCTL - Test Control bit definition - Read/write`
189			`#define LINK_OFF 0x0080`
190			`#define ENDEC_LOOPBACK 0x0200`
191			`#define AUI_LOOPBACK 0x0400`
192			`#define BACKOFF_OFF 0x0800`
193			`#define FDX_8900 0x4000`
194
195			`// PP_RxEvent - Receive Event Bit definition - Read-only`
196			`#define RX_IA_HASHED 0x0040`
197			`#define RX_DRIBBLE 0x0080`
198			`#define RX_OK 0x0100`
199			`#define RX_HASHED 0x0200`
200			`#define RX_IA 0x0400`
201			`#define RX_BROADCAST 0x0800`
202			`#define RX_CRC_ERROR 0x1000`
203			`#define RX_RUNT 0x2000`
204			`#define RX_EXTRA_DATA 0x4000`
205			`#define HASH_INDEX_MASK 0xFC00 // Hash-Table Index Mask (6 Bit)`
206
207			`// PP_TxEvent - Transmit Event Bit definition - Read-only`
208			`#define TX_LOST_CRS 0x0040`
209			`#define TX_SQE_ERROR 0x0080`
210			`#define TX_OK 0x0100`
211			`#define TX_LATE_COL 0x0200`
212			`#define TX_JBR 0x0400`
213			`#define TX_16_COL 0x8000`
214			`#define TX_COL_COUNT_MASK 0x7800`
215
216			`// PP_BufEvent - Buffer Event Bit definition - Read-only`
217			`#define SW_INTERRUPT 0x0040`
218			`#define RX_DMA 0x0080`
219			`#define READY_FOR_TX 0x0100`
220			`#define TX_UNDERRUN 0x0200`
221			`#define RX_MISS 0x0400`
222			`#define RX_128_BYTE 0x0800`
223			`#define TX_COL_OVRFLW 0x1000`
224			`#define RX_MISS_OVRFLW 0x2000`
225			`#define RX_DEST_MATCH 0x8000`
226
227			`// PP_LineST - Ethernet Line Status bit definition - Read-only`
228			`#define LINK_OK 0x0080`
229			`#define AUI_ON 0x0100`
230			`#define TENBASET_ON 0x0200`
231			`#define POLARITY_OK 0x1000`
232			`#define CRS_OK 0x4000`
233
234			`// PP_SelfST - Chip Software Status bit definition`
235			`#define ACTIVE_33V 0x0040`
236			`#define INIT_DONE 0x0080`
237			`#define SI_BUSY 0x0100`
238			`#define EEPROM_PRESENT 0x0200`
239			`#define EEPROM_OK 0x0400`
240			`#define EL_PRESENT 0x0800`
241			`#define EE_SIZE_64 0x1000`
242
243			`// PP_BusST - ISA Bus Status bit definition`
244			`#define TX_BID_ERROR 0x0080`
245			`#define READY_FOR_TX_NOW 0x0100`
246
247			`// The following block defines the ISQ event types`
248			`#define ISQ_RX_EVENT 0x0004`
249			`#define ISQ_TX_EVENT 0x0008`
250			`#define ISQ_BUFFER_EVENT 0x000C`
251			`#define ISQ_RX_MISS_EVENT 0x0010`
252			`#define ISQ_TX_COL_EVENT 0x0012`
253
254			`#define ISQ_EVENT_MASK 0x003F // ISQ mask to find out type of event`
255
256			`#define AUTOINCREMENT 0x8000 // Bit mask to set Bit-15 for autoincrement`
257
258			`// EEProm Commands`
259			`#define EEPROM_WRITE_EN 0x00F0`
260			`#define EEPROM_WRITE_DIS 0x0000`
261			`#define EEPROM_WRITE_CMD 0x0100`
262			`#define EEPROM_READ_CMD 0x0200`
263
264			`// Receive Header of each packet in receive area of memory for DMA-Mode`
265			`#define RBUF_EVENT_LOW 0x0000 // Low byte of RxEvent`
266			`#define RBUF_EVENT_HIGH 0x0001 // High byte of RxEvent`
267			`#define RBUF_LEN_LOW 0x0002 // Length of received data - low byte`
268			`#define RBUF_LEN_HI 0x0003 // Length of received data - high byte`
269			`#define RBUF_HEAD_LEN 0x0004 // Length of this header`
270
271			`// typedefs`
272
273			`// constants`
274
275			`// prototypes`
276
277			`#include "nic.h"`
278
279			`unsigned int cs8900BeginPacketRetreive(void);`
280			`void cs8900RetreivePacketData(u08* packet, unsigned int packetLength);`
281			`void cs8900EndPacketRetreive(void);`
282
283
284			`void cs8900Init(void);`
285			`void cs8900Write(unsigned char address, unsigned char data);`
286			`unsigned char cs8900Read(unsigned char address);`
287
288			`void cs8900Write16(unsigned char address, unsigned short data);`
289			`unsigned short cs8900Read16(unsigned char address);`
290
291			`void cs8900WriteReg(unsigned short address, unsigned short data);`
292			`unsigned short cs8900ReadReg(unsigned short address);`
293
294			`void cs8900CopyToFrame(unsigned char *source, unsigned short size);`
295			`void cs8900CopyFromFrame(unsigned char *dest, unsigned short size);`
296
297			`u08 cs8900LinkStatus(void);`
298
299			`void cs8900IORegDump(void);`
300			`void cs8900RegDump(void);`
301
302			`#endif`
303			`//@}`
304
305
306			`/****************`
307
308			`// CS8900 device register definitions`
309
310			`// Crystal ESIA product id.`
311
312			`#define CS8900_ESIA_ID (0x630e)`
313
314			`//IO Registers.`
315			`#define CS8900_IO_RX_TX_DATA_PORT0 (0x0000)`
316			`#define CS8900_IO_TX_TX_DATA_PORT1 (0x0002)`
317			`#define CS8900_IO_TxCMD (0x0004)`
318			`#define CS8900_IO_TxLength (0x0006)`
319			`#define CS8900_IO_ISQ (0x0008)`
320			`#define CS8900_IO_PACKET_PAGE_PTR (0x000a)`
321			`#define CS8900_IO_PP_DATA_PORT0 (0x000c)`
322			`#define CS8900_IO_PP_DATA_PORT1 (0x000e)`
323
324			`* Packet Page Registers.`
325
326			`* Bus Interface Registers.`
327
328			`#define CS8900_PP_PROD_ID (0x0000)`
329			`#define CS8900_PP_IO_BASE (0x0020)`
330			`#define CS8900_PP_INT (0x0022)`
331			`#define CS8900_PP_DMA_CHANNEL (0x0024)`
332			`#define CS8900_PP_DMA_SOF (0x0026)`
333			`#define CS8900_PP_DMA_FRM_CNT (0x0028)`
334			`#define CS8900_PP_DMA_RX_BCNT (0x002a)`
335			`#define CS8900_PP_MEM_BASE (0x002c)`
336			`#define CS8900_PP_BPROM_BASE (0x0030)`
337			`#define CS8900_PP_BPROM_AMASK (0x0034)`
338			`#define CS8900_PP_EEPROM_CMD (0x0040)`
339			`#define CS8900_PP_EEPROM_DATA (0x0042)`
340			`#define CS8900_PP_RX_FRAME_BCNT (0x0050)`
341
342			`* Configuration and Control Registers.`
343
344			`#define CS8900_PP_RxCFG (0x0102)`
345			`#define CS8900_PP_RxCTL (0x0104)`
346			`#define CS8900_PP_TxCFG (0x0106)`
347			`#define CS8900_PP_TxCMD_READ (0x0108)`
348			`#define CS8900_PP_BufCFG (0x010a)`
349			`#define CS8900_PP_LineCFG (0x0112)`
350			`#define CS8900_PP_SelfCTL (0x0114)`
351			`#define CS8900_PP_BusCTL (0x0116)`
352			`#define CS8900_PP_TestCTL (0x0118)`
353
354			`* Status and Event Registers.`
355
356			`#define CS8900_PP_ISQ (0x0120)`
357			`#define CS8900_PP_RxEvent (0x0124)`
358			`#define CS8900_PP_TxEvent (0x0128)`
359			`#define CS8900_PP_BufEvent (0x012c)`
360			`#define CS8900_PP_RxMISS (0x0130)`
361			`#define CS8900_PP_TxCol (0x0132)`
362			`#define CS8900_PP_LineST (0x0134)`
363			`#define CS8900_PP_SelfST (0x0136)`
364			`#define CS8900_PP_BusST (0x0138)`
365			`#define CS8900_PP_TDR (0x013c)`
366
367			`* Initiate Transmit Registers.`
368			`#define CS8900_PP_TxCMD (0x0144)`
369			`#define CS8900_PP_TxLength (0x0146)`
370
371			`* Address Filter Registers.`
372			`#define CS8900_PP_LAF (0x0150)`
373			`#define CS8900_PP_IA (0x0158)`
374
375			`* Frame Location.`
376			`#define CS8900_PP_RxStatus (0x0400)`
377			`#define CS8900_PP_RxLength (0x0402)`
378			`#define CS8900_PP_RxFrameLoc (0x0404)`
379			`#define CS8900_PP_TxFrameLoc (0x0a00)`
380
381			`* Bit Definitions of Registers.`
382			`* IO Packet Page Pointer.`
383			`#define CS8900_PPP_AUTO_INCREMENT (0x8000)`
384
385			`* Reg 3. Receiver Configuration.`
386			`#define CS8900_RX_CONFIG_SKIP_1 (1 << 6)`
387			`#define CS8900_RX_CONFIG_STREAM_ENABLE (1 << 7)`
388			`#define CS8900_RX_CONFIG_RX_OK (1 << 8)`
389			`#define CS8900_RX_CONFIG_RX_DMA (1 << 9)`
390			`#define CS8900_RX_CONFIG_RX_AUTO_DMA (1 << 10)`
391			`#define CS8900_RX_CONFIG_BUFFER_CRC (1 << 11)`
392			`#define CS8900_RX_CONFIG_CRC_ERROR (1 << 12)`
393			`#define CS8900_RX_CONFIG_RUNT (1 << 13)`
394			`#define CS8900_RX_CONFIG_EXTRA_DATA (1 << 14)`
395
396			`* Reg 4. Receiver Event.`
397			`#define CS8900_RX_EVENT_HASH_IA_MATCH (1 << 6)`
398			`#define CS8900_RX_EVENT_DRIBBLE_BITS (1 << 7)`
399			`#define CS8900_RX_EVENT_RX_OK (1 << 8)`
400			`#define CS8900_RX_EVENT_HASHED (1 << 9)`
401			`#define CS8900_RX_EVENT_IA (1 << 10)`
402			`#define CS8900_RX_EVENT_BROADCAST (1 << 11)`
403			`#define CS8900_RX_EVENT_CRC_ERROR (1 << 12)`
404			`#define CS8900_RX_EVENT_RUNT (1 << 13)`
405			`#define CS8900_RX_EVENT_EXTRA_DATA (1 << 14)`
406
407			`* Reg 5. Receiver Control.`
408			`#define CS8900_RX_CTRL_HASH_IA_MATCH (1 << 6)`
409			`#define CS8900_RX_CTRL_PROMISCUOUS (1 << 7)`
410			`#define CS8900_RX_CTRL_RX_OK (1 << 8)`
411			`#define CS8900_RX_CTRL_MULTICAST (1 << 9)`
412			`#define CS8900_RX_CTRL_INDIVIDUAL (1 << 10)`
413			`#define CS8900_RX_CTRL_BROADCAST (1 << 11)`
414			`#define CS8900_RX_CTRL_CRC_ERROR (1 << 12)`
415			`#define CS8900_RX_CTRL_RUNT (1 << 13)`
416			`#define CS8900_RX_CTRL_EXTRA_DATA (1 << 14)`
417
418			`* Reg 7. Transmit Configuration.`
419			`#define CS8900_TX_CONFIG_LOSS_OF_CARRIER (1 << 6)`
420			`#define CS8900_TX_CONFIG_SQ_ERROR (1 << 7)`
421			`#define CS8900_TX_CONFIG_TX_OK (1 << 8)`
422			`#define CS8900_TX_CONFIG_OUT_OF_WINDOW (1 << 9)`
423			`#define CS8900_TX_CONFIG_JABBER (1 << 10)`
424			`#define CS8900_TX_CONFIG_ANY_COLLISION (1 << 11)`
425			`#define CS8900_TX_CONFIG_16_COLLISION (1 << 15)`
426
427			`* Reg 8. Transmit Event.`
428			`#define CS8900_TX_EVENT_LOSS_OF_CARRIER (1 << 6)`
429			`#define CS8900_TX_EVENT_SQ_ERROR (1 << 7)`
430			`#define CS8900_TX_EVENT_TX_OK (1 << 8)`
431			`#define CS8900_TX_EVENT_OUT_OF_WINDOW (1 << 9)`
432			`#define CS8900_TX_EVENT_JABBER (1 << 10)`
433			`#define CS8900_TX_EVENT_16_COLLISIONS (1 << 15)`
434
435			`* Reg 9. Transmit Command Status.`
436			`#define CS8900_TX_CMD_STATUS_TX_START_5 (0 << 6)`
437			`#define CS8900_TX_CMD_STATUS_TX_START_381 (1 << 6)`
438			`#define CS8900_TX_CMD_STATUS_TX_START_1021 (2 << 6)`
439			`#define CS8900_TX_CMD_STATUS_TX_START_ENTIRE (3 << 6)`
440			`#define CS8900_TX_CMD_STATUS_FORCE (1 << 8)`
441			`#define CS8900_TX_CMD_STATUS_ONE_COLLISION (1 << 9)`
442			`#define CS8900_TX_CMD_STATUS_INHIBIT_CRC (1 << 12)`
443			`#define CS8900_TX_CMD_STATUS_TX_PAD_DISABLED (1 << 13)`
444
445			`* Reg B. Buffer Configuration.`
446			`#define CS8900_BUFFER_CONFIG_SW_INT (1 << 6)`
447			`#define CS8900_BUFFER_CONFIG_RX_DMA_DONE (1 << 7)`
448			`#define CS8900_BUFFER_CONFIG_RDY_FOR_TX (1 << 8)`
449			`#define CS8900_BUFFER_CONFIG_TX_UNDERRUN (1 << 9)`
450			`#define CS8900_BUFFER_CONFIG_RX_MISSED (1 << 10)`
451			`#define CS8900_BUFFER_CONFIG_RX_128_BYTES (1 << 11)`
452			`#define CS8900_BUFFER_CONFIG_TX_COL_OVF (1 << 12)`
453			`#define CS8900_BUFFER_CONFIG_RX_MISSED_OVF (1 << 13)`
454			`#define CS8900_BUFFER_CONFIG_RX_DEST_MATCH (1 << 15)`
455
456			`* Reg C. Buffer Event.`
457			`#define CS8900_BUFFER_EVENT_SW_INT (1 << 6)`
458			`#define CS8900_BUFFER_EVENT_RX_DMA_DONE (1 << 7)`
459			`#define CS8900_BUFFER_EVENT_RDY_FOR_TX (1 << 8)`
460			`#define CS8900_BUFFER_EVENT_TX_UNDERRUN (1 << 9)`
461			`#define CS8900_BUFFER_EVENT_RX_MISSED (1 << 10)`
462			`#define CS8900_BUFFER_EVENT_RX_128_BYTES (1 << 11)`
463			`#define CS8900_BUFFER_EVENT_RX_DEST_MATCH (1 << 15)`
464
465			`* Reg 13. Line Control.`
466			`#define CS8900_LINE_CTRL_RX_ON (1 << 6)`
467			`#define CS8900_LINE_CTRL_TX_ON (1 << 7)`
468			`#define CS8900_LINE_CTRL_AUI (1 << 8)`
469			`#define CS8900_LINE_CTRL_10BASET (0 << 9)`
470			`#define CS8900_LINE_CTRL_AUTO_AUI_10BASET (1 << 9)`
471			`#define CS8900_LINE_CTRL_MOD_BACKOFF (1 << 11)`
472			`#define CS8900_LINE_CTRL_POLARITY_DISABLED (1 << 12)`
473			`#define CS8900_LINE_CTRL_2_PART_DEF_DISABLED (1 << 13)`
474			`#define CS8900_LINE_CTRL_LO_RX_SQUELCH (1 << 14)`
475
476			`* Reg 14. Line Status.`
477			`#define CS8900_LINE_STATUS_LINK_OK (1 << 7)`
478			`#define CS8900_LINE_STATUS_AUI (1 << 8)`
479			`#define CS8900_LINE_STATUS_10_BASE_T (1 << 9)`
480			`#define CS8900_LINE_STATUS_POLARITY_OK (1 << 12)`
481			`#define CS8900_LINE_STATUS_CRS (1 << 14)`
482
483			`* Reg 15. Self Control.`
484			`#define CS8900_SELF_CTRL_RESET (1 << 6)`
485			`#define CS8900_SELF_CTRL_SW_SUSPEND (1 << 8)`
486			`#define CS8900_SELF_CTRL_HW_SLEEP (1 << 9)`
487			`#define CS8900_SELF_CTRL_HW_STANDBY (1 << 10)`
488			`#define CS8900_SELF_CTRL_HC0E (1 << 12)`
489			`#define CS8900_SELF_CTRL_HC1E (1 << 13)`
490			`#define CS8900_SELF_CTRL_HCB0 (1 << 14)`
491			`#define CS8900_SELF_CTRL_HCB1 (1 << 15)`
492
493			`* Reg 16. Self Status.`
494			`#define CS8900_SELF_STATUS_3_3_V (1 << 6)`
495			`#define CS8900_SELF_STATUS_INITD (1 << 7)`
496			`#define CS8900_SELF_STATUS_SIBUST (1 << 8)`
497			`#define CS8900_SELF_STATUS_EEPROM_PRESENT (1 << 9)`
498			`#define CS8900_SELF_STATUS_EEPROM_OK (1 << 10)`
499			`#define CS8900_SELF_STATUS_EL_PRESENT (1 << 11)`
500			`#define CS8900_SELF_STATUS_EE_SIZE (1 << 12)`
501
502			`* Reg 17. Bus Control.`
503			`#define CS8900_BUS_CTRL_RESET_RX_DMA (1 << 6)`
504			`#define CS8900_BUS_CTRL_USE_SA (1 << 9)`
505			`#define CS8900_BUS_CTRL_MEMORY_ENABLE (1 << 10)`
506			`#define CS8900_BUS_CTRL_DMA_BURST (1 << 11)`
507			`#define CS8900_BUS_CTRL_IOCHRDYE (1 << 12)`
508			`#define CS8900_BUS_CTRL_RX_DMA_SIZE (1 << 13)`
509			`#define CS8900_BUS_CTRL_ENABLE_INT (1 << 15)`
510
511			`* Reg 18. Bus Status.`
512			`#define CS8900_BUS_STATUS_TX_BID_ERROR (1 << 7)`
513			`#define CS8900_BUS_STATUS_RDY_FOR_TX_NOW (1 << 8)`
514
515			`*/`